llvm.org GIT mirror llvm / 8521a3b
[X86] Stop promoting vector ISD::SELECT to vXi64. The additional patterns needed for this aren't overwhelming and introducing extra bitcasts during lowering limits our ability to do computeNumSignBits. Not that I have a good example of that for select. I'm just becoming increasingly grumpy about promotion of AND/OR/XOR. SELECT was just a lot easier to fix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343723 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 1 year, 9 months ago
2 changed file(s) with 41 addition(s) and 3 deletion(s). Raw diff Collapse all Expand all
875875 setOperationPromotedToType(ISD::OR, VT, MVT::v2i64);
876876 setOperationPromotedToType(ISD::XOR, VT, MVT::v2i64);
877877 setOperationPromotedToType(ISD::LOAD, VT, MVT::v2i64);
878 setOperationPromotedToType(ISD::SELECT, VT, MVT::v2i64);
879878 }
880879
881880 // Custom lower v2i64 and v2f64 selects.
882881 setOperationAction(ISD::SELECT, MVT::v2f64, Custom);
883882 setOperationAction(ISD::SELECT, MVT::v2i64, Custom);
883 setOperationAction(ISD::SELECT, MVT::v4i32, Custom);
884 setOperationAction(ISD::SELECT, MVT::v8i16, Custom);
885 setOperationAction(ISD::SELECT, MVT::v16i8, Custom);
884886
885887 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
886888 setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom);
10571059
10581060 setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
10591061 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
1062 setOperationAction(ISD::SELECT, MVT::v8i32, Custom);
1063 setOperationAction(ISD::SELECT, MVT::v16i16, Custom);
1064 setOperationAction(ISD::SELECT, MVT::v32i8, Custom);
10601065 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
10611066
10621067 for (auto VT : { MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
11731178 setOperationPromotedToType(ISD::OR, VT, MVT::v4i64);
11741179 setOperationPromotedToType(ISD::XOR, VT, MVT::v4i64);
11751180 setOperationPromotedToType(ISD::LOAD, VT, MVT::v4i64);
1176 setOperationPromotedToType(ISD::SELECT, VT, MVT::v4i64);
11771181 }
11781182
11791183 if (HasInt256) {
13461350
13471351 setOperationAction(ISD::SELECT, MVT::v8f64, Custom);
13481352 setOperationAction(ISD::SELECT, MVT::v8i64, Custom);
1353 setOperationAction(ISD::SELECT, MVT::v16i32, Custom);
1354 setOperationAction(ISD::SELECT, MVT::v32i16, Custom);
1355 setOperationAction(ISD::SELECT, MVT::v64i8, Custom);
13491356 setOperationAction(ISD::SELECT, MVT::v16f32, Custom);
13501357
13511358 for (auto VT : { MVT::v16i32, MVT::v8i64 }) {
14201427 }
14211428 for (auto VT : { MVT::v64i8, MVT::v32i16, MVT::v16i32 }) {
14221429 setOperationPromotedToType(ISD::LOAD, VT, MVT::v8i64);
1423 setOperationPromotedToType(ISD::SELECT, VT, MVT::v8i64);
14241430 }
14251431
14261432 // Need to custom split v32i16/v64i8 bitcasts.
610610 (CMOV_VR128 VR128:$t, VR128:$f, imm:$cond)>;
611611
612612 let Predicates = [NoVLX] in {
613 def : Pat<(v16i8 (X86cmov VR128:$t, VR128:$f, imm:$cond, EFLAGS)),
614 (CMOV_VR128 VR128:$t, VR128:$f, imm:$cond)>;
615 def : Pat<(v8i16 (X86cmov VR128:$t, VR128:$f, imm:$cond, EFLAGS)),
616 (CMOV_VR128 VR128:$t, VR128:$f, imm:$cond)>;
617 def : Pat<(v4i32 (X86cmov VR128:$t, VR128:$f, imm:$cond, EFLAGS)),
618 (CMOV_VR128 VR128:$t, VR128:$f, imm:$cond)>;
613619 def : Pat<(v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond, EFLAGS)),
614620 (CMOV_VR128 VR128:$t, VR128:$f, imm:$cond)>;
615621 def : Pat<(v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond, EFLAGS)),
616622 (CMOV_VR128 VR128:$t, VR128:$f, imm:$cond)>;
623
624 def : Pat<(v32i8 (X86cmov VR256:$t, VR256:$f, imm:$cond, EFLAGS)),
625 (CMOV_VR256 VR256:$t, VR256:$f, imm:$cond)>;
626 def : Pat<(v16i16 (X86cmov VR256:$t, VR256:$f, imm:$cond, EFLAGS)),
627 (CMOV_VR256 VR256:$t, VR256:$f, imm:$cond)>;
628 def : Pat<(v8i32 (X86cmov VR256:$t, VR256:$f, imm:$cond, EFLAGS)),
629 (CMOV_VR256 VR256:$t, VR256:$f, imm:$cond)>;
617630 def : Pat<(v8f32 (X86cmov VR256:$t, VR256:$f, imm:$cond, EFLAGS)),
618631 (CMOV_VR256 VR256:$t, VR256:$f, imm:$cond)>;
619632 def : Pat<(v4f64 (X86cmov VR256:$t, VR256:$f, imm:$cond, EFLAGS)),
620633 (CMOV_VR256 VR256:$t, VR256:$f, imm:$cond)>;
621634 }
622635 let Predicates = [HasVLX] in {
636 def : Pat<(v16i8 (X86cmov VR128X:$t, VR128X:$f, imm:$cond, EFLAGS)),
637 (CMOV_VR128X VR128X:$t, VR128X:$f, imm:$cond)>;
638 def : Pat<(v8i16 (X86cmov VR128X:$t, VR128X:$f, imm:$cond, EFLAGS)),
639 (CMOV_VR128X VR128X:$t, VR128X:$f, imm:$cond)>;
640 def : Pat<(v4i32 (X86cmov VR128X:$t, VR128X:$f, imm:$cond, EFLAGS)),
641 (CMOV_VR128X VR128X:$t, VR128X:$f, imm:$cond)>;
623642 def : Pat<(v4f32 (X86cmov VR128X:$t, VR128X:$f, imm:$cond, EFLAGS)),
624643 (CMOV_VR128X VR128X:$t, VR128X:$f, imm:$cond)>;
625644 def : Pat<(v2f64 (X86cmov VR128X:$t, VR128X:$f, imm:$cond, EFLAGS)),
626645 (CMOV_VR128X VR128X:$t, VR128X:$f, imm:$cond)>;
646
647 def : Pat<(v32i8 (X86cmov VR256X:$t, VR256X:$f, imm:$cond, EFLAGS)),
648 (CMOV_VR256X VR256X:$t, VR256X:$f, imm:$cond)>;
649 def : Pat<(v16i16 (X86cmov VR256X:$t, VR256X:$f, imm:$cond, EFLAGS)),
650 (CMOV_VR256X VR256X:$t, VR256X:$f, imm:$cond)>;
651 def : Pat<(v8i32 (X86cmov VR256X:$t, VR256X:$f, imm:$cond, EFLAGS)),
652 (CMOV_VR256X VR256X:$t, VR256X:$f, imm:$cond)>;
627653 def : Pat<(v8f32 (X86cmov VR256X:$t, VR256X:$f, imm:$cond, EFLAGS)),
628654 (CMOV_VR256X VR256X:$t, VR256X:$f, imm:$cond)>;
629655 def : Pat<(v4f64 (X86cmov VR256X:$t, VR256X:$f, imm:$cond, EFLAGS)),
630656 (CMOV_VR256X VR256X:$t, VR256X:$f, imm:$cond)>;
631657 }
632658
659 def : Pat<(v64i8 (X86cmov VR512:$t, VR512:$f, imm:$cond, EFLAGS)),
660 (CMOV_VR512 VR512:$t, VR512:$f, imm:$cond)>;
661 def : Pat<(v32i16 (X86cmov VR512:$t, VR512:$f, imm:$cond, EFLAGS)),
662 (CMOV_VR512 VR512:$t, VR512:$f, imm:$cond)>;
663 def : Pat<(v16i32 (X86cmov VR512:$t, VR512:$f, imm:$cond, EFLAGS)),
664 (CMOV_VR512 VR512:$t, VR512:$f, imm:$cond)>;
633665 def : Pat<(v16f32 (X86cmov VR512:$t, VR512:$f, imm:$cond, EFLAGS)),
634666 (CMOV_VR512 VR512:$t, VR512:$f, imm:$cond)>;
635667 def : Pat<(v8f64 (X86cmov VR512:$t, VR512:$f, imm:$cond, EFLAGS)),