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[ARM] [Assembler] Support negative immediates: cover few missing cases Support for negative immediates was implemented in https://reviews.llvm.org/rL298380, however few instruction options were missing. This change adds negative immediates support and respective tests for the following: ADD ADDS ADDS.W AND.W ANDS BIC.W BICS BICS.W SUB SUBS SUBS.W Differential Revision: https://reviews.llvm.org/D48649 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336286 91177308-0d34-0410-b5e6-96231b3b80d8 Volodymyr Turanskyy 2 years ago
3 changed file(s) with 74 addition(s) and 2 deletion(s). Raw diff Collapse all Expand all
21022102 def : t2InstSubst<"sub${s}${p}.w $rd, $rn, $imm",
21032103 (t2ADDri GPRnopc:$rd, GPRnopc:$rn, t2_so_imm_neg:$imm, pred:$p, s_cc_out:$s)>;
21042104 def : t2InstSubst<"subw${p} $rd, $rn, $imm",
2105 (t2ADDri12 GPRnopc:$rd, GPR:$rn, t2_so_imm_neg:$imm, pred:$p)>;
2106 def : t2InstSubst<"subw${p} $Rd, $Rn, $imm",
2107 (t2ADDri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095_neg:$imm, pred:$p)>;
2108 def : t2InstSubst<"sub${s}${p} $rd, $rn, $imm",
2109 (t2ADDri GPRnopc:$rd, GPRnopc:$rn, t2_so_imm_neg:$imm, pred:$p, s_cc_out:$s)>;
2110 def : t2InstSubst<"sub${p} $rd, $rn, $imm",
21052111 (t2ADDri12 GPRnopc:$rd, GPR:$rn, t2_so_imm_neg:$imm, pred:$p)>;
21062112 // RSB
21072113 defm t2RSB : T2I_rbin_irs <0b1110, "rsb", sub>;
47304736 def : t2InstSubst<"bic${s}${p} $Rdn, $imm",
47314737 (t2ANDri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm,
47324738 pred:$p, cc_out:$s)>;
4739 def : t2InstSubst<"bic${s}${p}.w $Rd, $Rn, $imm",
4740 (t2ANDri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm,
4741 pred:$p, cc_out:$s)>;
4742 def : t2InstSubst<"bic${s}${p}.w $Rdn, $imm",
4743 (t2ANDri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm,
4744 pred:$p, cc_out:$s)>;
47334745 def : t2InstSubst<"and${s}${p} $Rd, $Rn, $imm",
47344746 (t2BICri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm,
47354747 pred:$p, cc_out:$s)>;
47364748 def : t2InstSubst<"and${s}${p} $Rdn, $imm",
4749 (t2BICri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm,
4750 pred:$p, cc_out:$s)>;
4751 def : t2InstSubst<"and${s}${p}.w $Rd, $Rn, $imm",
4752 (t2BICri rGPR:$Rd, rGPR:$Rn, t2_so_imm_not:$imm,
4753 pred:$p, cc_out:$s)>;
4754 def : t2InstSubst<"and${s}${p}.w $Rdn, $imm",
47374755 (t2BICri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm_not:$imm,
47384756 pred:$p, cc_out:$s)>;
47394757 // And ORR <--> ORN
10291029 if (!isImm()) return false;
10301030 const MCConstantExpr *CE = dyn_cast(getImm());
10311031 if (!CE) return false;
1032 int64_t Value = -CE->getValue();
1032 // isImm0_4095Neg is used with 32-bit immediates only.
1033 // 32-bit immediates are zero extended to 64-bit when parsed,
1034 // thus simple -CE->getValue() results in a big negative number,
1035 // not a small positive number as intended
1036 if ((CE->getValue() >> 32) > 0) return false;
1037 uint32_t Value = -static_cast(CE->getValue());
10331038 return Value > 0 && Value < 4096;
10341039 }
10351040
22412246 // The operand is actually an imm0_4095, but we have its
22422247 // negation in the assembly source, so twiddle it here.
22432248 const MCConstantExpr *CE = dyn_cast(getImm());
2244 Inst.addOperand(MCOperand::createImm(-CE->getValue()));
2249 Inst.addOperand(MCOperand::createImm(-(uint32_t)CE->getValue()));
22452250 }
22462251
22472252 void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
4949
5050 .thumb
5151
52 ADD r0, r1, #0xFFFFFF00
53 # CHECK: subw r0, r1, #256
54 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
55 # CHECK-DISABLED: ADD
56 ADDS r0, r1, #0xFFFFFF00
57 # CHECK: subs.w r0, r1, #256
58 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
59 # CHECK-DISABLED: ADDS
60 ADDS.W r0, r1, #0xFFFFFF00
61 # CHECK: subs.w r0, r1, #256
62 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
63 # CHECK-DISABLED: ADDS.W
5264 ADC r0, r1, #0xFFFFFF00
5365 # CHECK: sbc r0, r1, #255
5466 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
89101 # CHECK: bic r0, r1, #16777472 @ encoding: [0x21,0xf0,0x01,0x20]
90102 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
91103 # CHECK-DISABLED: AND
104 AND.W r0, r1, #0xFFFFFF00
105 # CHECK: bic r0, r1, #255
106 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
107 # CHECK-DISABLED: AND.W
108 ANDS r0, r1, #0xFFFFFF00
109 # CHECK: bics r0, r1, #255
110 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
111 # CHECK-DISABLED: ANDS
92112 BIC r0, r1, #0xFFFFFF00
93113 # CHECK: and r0, r1, #255
94114 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
95115 # CHECK-DISABLED: BIC
116 BIC.W r0, r1, #0xFFFFFF00
117 # CHECK: and r0, r1, #255
118 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
119 # CHECK-DISABLED: BIC.W
120 BICS r0, r1, #0xFFFFFF00
121 # CHECK: ands r0, r1, #255
122 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
123 # CHECK-DISABLED: BICS
124 BICS.W r0, r1, #0xFFFFFF00
125 # CHECK: ands r0, r1, #255
126 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
127 # CHECK-DISABLED: BICS.W
96128 BIC r0, r1, #0xFEFFFEFF
97129 # CHECK: and r0, r1, #16777472 @ encoding: [0x01,0xf0,0x01,0x20]
98130 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
141173 # CHECK: add.w r0, r1, #255
142174 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
143175 # CHECK-DISABLED: SUB.W
176 SUB r0, r1, #0xFFFFFF00
177 # CHECK: addw r0, r1, #256
178 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
179 # CHECK-DISABLED: SUB
180 SUBS r0, r1, #0xFFFFFF00
181 # CHECK: adds.w r0, r1, #256
182 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
183 # CHECK-DISABLED: SUBS
184 SUBS.W r0, r1, #0xFFFFFF00
185 # CHECK: adds.w r0, r1, #256
186 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
187 # CHECK-DISABLED: SUBS.W
188
189 ADD r0, r1, #-13
190 # CHECK: subw r0, r1, #13
191 # CHECK-DISABLED: note: instruction requires: NegativeImmediates
192 # CHECK-DISABLED: ADD