llvm.org GIT mirror llvm / 84f7f35
Make consistent use of MCPhysReg instead of uint16_t throughout the tree. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205610 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 5 years ago
63 changed file(s) with 175 addition(s) and 175 deletion(s). Raw diff Collapse all Expand all
278278
279279 /// getFirstUnallocated - Return the first unallocated register in the set, or
280280 /// NumRegs if they are all allocated.
281 unsigned getFirstUnallocated(const uint16_t *Regs, unsigned NumRegs) const {
281 unsigned getFirstUnallocated(const MCPhysReg *Regs, unsigned NumRegs) const {
282282 for (unsigned i = 0; i != NumRegs; ++i)
283283 if (!isAllocated(Regs[i]))
284284 return i;
305305 /// AllocateReg - Attempt to allocate one of the specified registers. If none
306306 /// are available, return zero. Otherwise, return the first one available,
307307 /// marking it and any aliases as allocated.
308 unsigned AllocateReg(const uint16_t *Regs, unsigned NumRegs) {
308 unsigned AllocateReg(const MCPhysReg *Regs, unsigned NumRegs) {
309309 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs);
310310 if (FirstUnalloc == NumRegs)
311311 return 0; // Didn't find the reg.
317317 }
318318
319319 /// Version of AllocateReg with list of registers to be shadowed.
320 unsigned AllocateReg(const uint16_t *Regs, const uint16_t *ShadowRegs,
320 unsigned AllocateReg(const MCPhysReg *Regs, const MCPhysReg *ShadowRegs,
321321 unsigned NumRegs) {
322322 unsigned FirstUnalloc = getFirstUnallocated(Regs, NumRegs);
323323 if (FirstUnalloc == NumRegs)
350350 /// Version of AllocateStack with list of extra registers to be shadowed.
351351 /// Note that, unlike AllocateReg, this shadows ALL of the shadow registers.
352352 unsigned AllocateStack(unsigned Size, unsigned Align,
353 const uint16_t *ShadowRegs, unsigned NumShadowRegs) {
353 const MCPhysReg *ShadowRegs, unsigned NumShadowRegs) {
354354 for (unsigned i = 0; i < NumShadowRegs; ++i)
355355 MarkAllocated(ShadowRegs[i]);
356356 return AllocateStack(Size, Align);
5353
5454 // Callee saved registers of last MF. Assumed to be valid until the next
5555 // runOnFunction() call.
56 const uint16_t *CalleeSaved;
56 const MCPhysReg *CalleeSaved;
5757
5858 // Map register number to CalleeSaved index + 1;
5959 SmallVector CSRNum;
158158 const MCRegisterClass *Classes; // Pointer to the regclass array
159159 unsigned NumClasses; // Number of entries in the array
160160 unsigned NumRegUnits; // Number of regunits.
161 const uint16_t (*RegUnitRoots)[2]; // Pointer to regunit root table.
161 const MCPhysReg (*RegUnitRoots)[2]; // Pointer to regunit root table.
162162 const MCPhysReg *DiffLists; // Pointer to the difflists array
163163 const char *RegStrings; // Pointer to the string table.
164164 const uint16_t *SubRegIndices; // Pointer to the subreg lookup
238238 void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA,
239239 unsigned PC,
240240 const MCRegisterClass *C, unsigned NC,
241 const uint16_t (*RURoots)[2],
241 const MCPhysReg (*RURoots)[2],
242242 unsigned NRU,
243243 const MCPhysReg *DL,
244244 const char *Strings,
3030 #include "llvm/IR/CallSite.h"
3131 #include "llvm/IR/CallingConv.h"
3232 #include "llvm/IR/InlineAsm.h"
33 #include "llvm/MC/MCRegisterInfo.h"
3334 #include "llvm/Target/TargetCallingConv.h"
3435 #include "llvm/Target/TargetMachine.h"
3536 #include
21692170
21702171 /// Returns a 0 terminated array of registers that can be safely used as
21712172 /// scratch registers.
2172 virtual const uint16_t *getScratchRegisters(CallingConv::ID CC) const {
2173 virtual const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const {
21732174 return NULL;
21742175 }
21752176
168168 // callee-saved register that is not saved in the prolog.
169169 const MachineFrameInfo *MFI = MF.getFrameInfo();
170170 BitVector Pristine = MFI->getPristineRegs(BB);
171 for (const uint16_t *I = TRI->getCalleeSavedRegs(&MF); *I; ++I) {
171 for (const MCPhysReg *I = TRI->getCalleeSavedRegs(&MF); *I; ++I) {
172172 unsigned Reg = *I;
173173 if (!IsReturnBlock && !Pristine.test(Reg)) continue;
174174 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
7474 // callee-saved register that is not saved in the prolog.
7575 const MachineFrameInfo *MFI = MF.getFrameInfo();
7676 BitVector Pristine = MFI->getPristineRegs(BB);
77 for (const uint16_t *I = TRI->getCalleeSavedRegs(&MF); *I; ++I) {
77 for (const MCPhysReg *I = TRI->getCalleeSavedRegs(&MF); *I; ++I) {
7878 if (!IsReturnBlock && !Pristine.test(*I)) continue;
7979 for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) {
8080 unsigned Reg = *AI;
582582 if (!isCalleeSavedInfoValid())
583583 return BV;
584584
585 for (const uint16_t *CSR = TRI->getCalleeSavedRegs(MF); CSR && *CSR; ++CSR)
585 for (const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF); CSR && *CSR; ++CSR)
586586 BV.set(*CSR);
587587
588588 // The entry MBB always has all CSRs pristine.
242242 MachineFrameInfo *MFI = F.getFrameInfo();
243243
244244 // Get the callee saved register list...
245 const uint16_t *CSRegs = RegInfo->getCalleeSavedRegs(&F);
245 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&F);
246246
247247 // These are used to keep track the callee-save area. Initialize them.
248248 MinCSFrameIndex = INT_MAX;
214214 // Compute an initial allowed set for the current vreg.
215215 typedef std::vector VRAllowed;
216216 VRAllowed vrAllowed;
217 ArrayRef<uint16_t> rawOrder = trc->getRawAllocationOrder(*mf);
217 ArrayRef<MCPhysReg> rawOrder = trc->getRawAllocationOrder(*mf);
218218 for (unsigned i = 0; i != rawOrder.size(); ++i) {
219219 unsigned preg = rawOrder[i];
220220 if (mri->isReserved(preg))
9090
9191 // Create callee-saved registers bitvector.
9292 CalleeSavedRegs.resize(NumPhysRegs);
93 const uint16_t *CSRegs = TRI->getCalleeSavedRegs(&MF);
93 const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF);
9494 if (CSRegs != NULL)
9595 for (unsigned i = 0; CSRegs[i]; ++i)
9696 CalleeSavedRegs.set(CSRegs[i]);
737737 const MCInstrDesc &II = TII->get(Opc);
738738 unsigned NumResults = CountResults(Node);
739739 unsigned NumDefs = II.getNumDefs();
740 const uint16_t *ScratchRegs = NULL;
740 const MCPhysReg *ScratchRegs = NULL;
741741
742742 // Handle STACKMAP and PATCHPOINT specially and then use the generic code.
743743 if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
129129 static void getAllocatableSetForRC(const MachineFunction &MF,
130130 const TargetRegisterClass *RC, BitVector &R){
131131 assert(RC->isAllocatable() && "invalid for nonallocatable sets");
132 ArrayRef<uint16_t> Order = RC->getRawAllocationOrder(MF);
132 ArrayRef<MCPhysReg> Order = RC->getRawAllocationOrder(MF);
133133 for (unsigned i = 0; i != Order.size(); ++i)
134134 R.set(Order[i]);
135135 }
368368
369369 // We certainly need some slack space for the scavenger, preferably an extra
370370 // register.
371 const uint16_t *CSRegs = RegInfo->getCalleeSavedRegs();
372 uint16_t ExtraReg = AArch64::NoRegister;
371 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs();
372 MCPhysReg ExtraReg = AArch64::NoRegister;
373373
374374 for (unsigned i = 0; CSRegs[i]; ++i) {
375375 if (AArch64::GPR64RegClass.contains(CSRegs[i]) &&
11861186 }
11871187 }
11881188
1189 static const uint16_t AArch64FPRArgRegs[] = {
1189 static const MCPhysReg AArch64FPRArgRegs[] = {
11901190 AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3,
11911191 AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7
11921192 };
11931193 static const unsigned NumFPRArgRegs = llvm::array_lengthof(AArch64FPRArgRegs);
11941194
1195 static const uint16_t AArch64ArgRegs[] = {
1195 static const MCPhysReg AArch64ArgRegs[] = {
11961196 AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3,
11971197 AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7
11981198 };
3232 : AArch64GenRegisterInfo(AArch64::X30) {
3333 }
3434
35 const uint16_t *
35 const MCPhysReg *
3636 AArch64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
3737 return CSR_PCS_SaveList;
3838 }
2626 struct AArch64RegisterInfo : public AArch64GenRegisterInfo {
2727 AArch64RegisterInfo();
2828
29 const uint16_t *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
29 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
3030 const uint32_t *getCallPreservedMask(CallingConv::ID) const;
3131
3232 const uint32_t *getTLSDescCallPreservedMask() const;
4848 BasePtr(ARM::R6) {
4949 }
5050
51 const uint16_t*
51 const MCPhysReg*
5252 ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
53 const uint16_t *RegList = (STI.isTargetIOS() && !STI.isAAPCS_ABI())
53 const MCPhysReg *RegList = (STI.isTargetIOS() && !STI.isAAPCS_ABI())
5454 ? CSR_iOS_SaveList
5555 : CSR_AAPCS_SaveList;
5656
9999
100100 public:
101101 /// Code Generation virtual methods...
102 const uint16_t *
102 const MCPhysReg *
103103 getCalleeSavedRegs(const MachineFunction *MF = 0) const override;
104104 const uint32_t *getCallPreservedMask(CallingConv::ID) const override;
105105 const uint32_t *getNoPreservedMask() const;
2727 static bool f64AssignAPCS(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
2828 CCValAssign::LocInfo &LocInfo,
2929 CCState &State, bool CanFail) {
30 static const uint16_t RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
30 static const MCPhysReg RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
3131
3232 // Try to get the first register.
3333 if (unsigned Reg = State.AllocateReg(RegList, 4))
7070 static bool f64AssignAAPCS(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
7171 CCValAssign::LocInfo &LocInfo,
7272 CCState &State, bool CanFail) {
73 static const uint16_t HiRegList[] = { ARM::R0, ARM::R2 };
74 static const uint16_t LoRegList[] = { ARM::R1, ARM::R3 };
75 static const uint16_t ShadowRegList[] = { ARM::R0, ARM::R1 };
76 static const uint16_t GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
73 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 };
74 static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 };
75 static const MCPhysReg ShadowRegList[] = { ARM::R0, ARM::R1 };
76 static const MCPhysReg GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
7777
7878 unsigned Reg = State.AllocateReg(HiRegList, ShadowRegList, 2);
7979 if (Reg == 0) {
122122
123123 static bool f64RetAssign(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
124124 CCValAssign::LocInfo &LocInfo, CCState &State) {
125 static const uint16_t HiRegList[] = { ARM::R0, ARM::R2 };
126 static const uint16_t LoRegList[] = { ARM::R1, ARM::R3 };
125 static const MCPhysReg HiRegList[] = { ARM::R0, ARM::R2 };
126 static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 };
127127
128128 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
129129 if (Reg == 0)
8686
8787 static bool isCSRestore(MachineInstr *MI,
8888 const ARMBaseInstrInfo &TII,
89 const uint16_t *CSRegs) {
89 const MCPhysReg *CSRegs) {
9090 // Integer spill area is handled with "pop".
9191 if (isPopOpcode(MI->getOpcode())) {
9292 // The first two operands are predicates. The last two are
536536 emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes - ArgRegsSaveSize);
537537 } else {
538538 // Unwind MBBI to point to first LDR / VLDRD.
539 const uint16_t *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
539 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
540540 if (MBBI != MBB.begin()) {
541541 do {
542542 --MBBI;
13671367
13681368 // Don't spill FP if the frame can be eliminated. This is determined
13691369 // by scanning the callee-save registers to see if any is used.
1370 const uint16_t *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
1370 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
13711371 for (unsigned i = 0; CSRegs[i]; ++i) {
13721372 unsigned Reg = CSRegs[i];
13731373 bool Spilled = false;
7878 }
7979
8080 // The APCS parameter registers.
81 static const uint16_t GPRArgRegs[] = {
81 static const MCPhysReg GPRArgRegs[] = {
8282 ARM::R0, ARM::R1, ARM::R2, ARM::R3
8383 };
8484
65576557 }
65586558
65596559 // N.B. the order the invoke BBs are processed in doesn't matter here.
6560 const uint16_t *SavedRegs = RI.getCalleeSavedRegs(MF);
6560 const MCPhysReg *SavedRegs = RI.getCalleeSavedRegs(MF);
65616561 SmallVector MBBLPads;
65626562 for (SmallPtrSet::iterator
65636563 I = InvokeBBs.begin(), E = InvokeBBs.end(); I != E; ++I) {
292292 AFI->setShouldRestoreSPFromFP(true);
293293 }
294294
295 static bool isCSRestore(MachineInstr *MI, const uint16_t *CSRegs) {
295 static bool isCSRestore(MachineInstr *MI, const MCPhysReg *CSRegs) {
296296 if (MI->getOpcode() == ARM::tLDRspi &&
297297 MI->getOperand(1).isFI() &&
298298 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs))
327327 int NumBytes = (int)MFI->getStackSize();
328328 assert((unsigned)NumBytes >= ArgRegsSaveSize &&
329329 "ArgRegsSaveSize is included in NumBytes");
330 const uint16_t *CSRegs = RegInfo->getCalleeSavedRegs();
330 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs();
331331 unsigned FramePtr = RegInfo->getFrameRegister(MF);
332332
333333 if (!AFI->hasStackFrame()) {
3030 ISD::ArgFlagsTy ArgFlags,
3131 CCState &State,
3232 bool IsWebKitJS = false) {
33 static const uint16_t RegList1[] = { ARM64::W0, ARM64::W1, ARM64::W2,
34 ARM64::W3, ARM64::W4, ARM64::W5,
35 ARM64::W6, ARM64::W7 };
36 static const uint16_t RegList2[] = { ARM64::X0, ARM64::X1, ARM64::X2,
37 ARM64::X3, ARM64::X4, ARM64::X5,
38 ARM64::X6, ARM64::X7 };
39 static const uint16_t WebKitRegList1[] = { ARM64::W0 };
40 static const uint16_t WebKitRegList2[] = { ARM64::X0 };
33 static const MCPhysReg RegList1[] = { ARM64::W0, ARM64::W1, ARM64::W2,
34 ARM64::W3, ARM64::W4, ARM64::W5,
35 ARM64::W6, ARM64::W7 };
36 static const MCPhysReg RegList2[] = { ARM64::X0, ARM64::X1, ARM64::X2,
37 ARM64::X3, ARM64::X4, ARM64::X5,
38 ARM64::X6, ARM64::X7 };
39 static const MCPhysReg WebKitRegList1[] = { ARM64::W0 };
40 static const MCPhysReg WebKitRegList2[] = { ARM64::X0 };
4141
42 const uint16_t *List1 = IsWebKitJS ? WebKitRegList1 : RegList1;
43 const uint16_t *List2 = IsWebKitJS ? WebKitRegList2 : RegList2;
42 const MCPhysReg *List1 = IsWebKitJS ? WebKitRegList1 : RegList1;
43 const MCPhysReg *List2 = IsWebKitJS ? WebKitRegList2 : RegList2;
4444
4545 if (unsigned Reg = State.AllocateReg(List1, List2, 8)) {
4646 // Customized extra section for handling i1/i8/i16:
387387 }
388388 }
389389
390 static bool isCalleeSavedRegister(unsigned Reg, const uint16_t *CSRegs) {
390 static bool isCalleeSavedRegister(unsigned Reg, const MCPhysReg *CSRegs) {
391391 for (unsigned i = 0; CSRegs[i]; ++i)
392392 if (Reg == CSRegs[i])
393393 return true;
394394 return false;
395395 }
396396
397 static bool isCSRestore(MachineInstr *MI, const uint16_t *CSRegs) {
397 static bool isCSRestore(MachineInstr *MI, const MCPhysReg *CSRegs) {
398398 if (MI->getOpcode() == ARM64::LDPXpost ||
399399 MI->getOpcode() == ARM64::LDPDpost || MI->getOpcode() == ARM64::LDPXi ||
400400 MI->getOpcode() == ARM64::LDPDi) {
423423 unsigned NumRestores = 0;
424424 // Move past the restores of the callee-saved registers.
425425 MachineBasicBlock::iterator LastPopI = MBBI;
426 const uint16_t *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
426 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
427427 if (LastPopI != MBB.begin()) {
428428 do {
429429 ++NumRestores;
707707 bool ExtraCSSpill = false;
708708 bool CanEliminateFrame = true;
709709 DEBUG(dbgs() << "*** processFunctionBeforeCalleeSavedScan\nUsed CSRs:");
710 const uint16_t *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
710 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(&MF);
711711
712712 // Check pairs of consecutive callee-saved registers.
713713 for (unsigned i = 0; CSRegs[i]; i += 2) {
21822182
21832183 SmallVector MemOps;
21842184
2185 static const uint16_t GPRArgRegs[] = { ARM64::X0, ARM64::X1, ARM64::X2,
2186 ARM64::X3, ARM64::X4, ARM64::X5,
2187 ARM64::X6, ARM64::X7 };
2185 static const MCPhysReg GPRArgRegs[] = { ARM64::X0, ARM64::X1, ARM64::X2,
2186 ARM64::X3, ARM64::X4, ARM64::X5,
2187 ARM64::X6, ARM64::X7 };
21882188 static const unsigned NumGPRArgRegs = array_lengthof(GPRArgRegs);
21892189 unsigned FirstVariadicGPR =
21902190 CCInfo.getFirstUnallocated(GPRArgRegs, NumGPRArgRegs);
21912191
2192 static const uint16_t FPRArgRegs[] = { ARM64::Q0, ARM64::Q1, ARM64::Q2,
2193 ARM64::Q3, ARM64::Q4, ARM64::Q5,
2194 ARM64::Q6, ARM64::Q7 };
2192 static const MCPhysReg FPRArgRegs[] = { ARM64::Q0, ARM64::Q1, ARM64::Q2,
2193 ARM64::Q3, ARM64::Q4, ARM64::Q5,
2194 ARM64::Q6, ARM64::Q7 };
21952195 static const unsigned NumFPRArgRegs = array_lengthof(FPRArgRegs);
21962196 unsigned FirstVariadicFPR =
21972197 CCInfo.getFirstUnallocated(FPRArgRegs, NumFPRArgRegs);
62346234 return false;
62356235 }
62366236
6237 const uint16_t *
6237 const MCPhysReg *
62386238 ARM64TargetLowering::getScratchRegisters(CallingConv::ID) const {
62396239 // LR is a callee-save register, but we must treat it as clobbered by any call
62406240 // site. Hence we include LR in the scratch registers, which are in turn added
62416241 // as implicit-defs for stackmaps and patchpoints.
6242 static const uint16_t ScratchRegs[] = {
6242 static const MCPhysReg ScratchRegs[] = {
62436243 ARM64::X16, ARM64::X17, ARM64::LR, 0
62446244 };
62456245 return ScratchRegs;
290290 /// expanded to fmul + fadd.
291291 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
292292
293 const uint16_t *getScratchRegisters(CallingConv::ID CC) const override;
293 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
294294
295295 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
296296 Type *Ty) const override;
3535 const ARM64Subtarget *sti)
3636 : ARM64GenRegisterInfo(ARM64::LR), TII(tii), STI(sti) {}
3737
38 const uint16_t *
38 const MCPhysReg *
3939 ARM64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
4040 assert(MF && "Invalid MachineFunction pointer.");
4141 if (MF->getFunction()->getCallingConv() == CallingConv::AnyReg)
3535 bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
3636
3737 /// Code Generation virtual methods...
38 const uint16_t *
38 const MCPhysReg *
3939 getCalleeSavedRegs(const MachineFunction *MF = 0) const override;
4040 const uint32_t *getCallPreservedMask(CallingConv::ID) const override;
4141
181181 MVT LocVT, CCValAssign::LocInfo LocInfo,
182182 ISD::ArgFlagsTy ArgFlags, CCState &State) {
183183
184 static const uint16_t RegList[] = {
184 static const MCPhysReg RegList[] = {
185185 Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,
186186 Hexagon::R5
187187 };
204204 return false;
205205 }
206206
207 static const uint16_t RegList1[] = {
207 static const MCPhysReg RegList1[] = {
208208 Hexagon::D1, Hexagon::D2
209209 };
210 static const uint16_t RegList2[] = {
210 static const MCPhysReg RegList2[] = {
211211 Hexagon::R1, Hexagon::R3
212212 };
213213 if (unsigned Reg = State.AllocateReg(RegList1, RegList2, 2)) {
4242 Subtarget(st) {
4343 }
4444
45 const uint16_t* HexagonRegisterInfo::getCalleeSavedRegs(const MachineFunction
46 *MF)
47 const {
48 static const uint16_t CalleeSavedRegsV2[] = {
45 const MCPhysReg *
46 HexagonRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
47 static const MCPhysReg CalleeSavedRegsV2[] = {
4948 Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0
5049 };
51 static const uint16_t CalleeSavedRegsV3[] = {
50 static const MCPhysReg CalleeSavedRegsV3[] = {
5251 Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
5352 Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23,
5453 Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0
4747 HexagonRegisterInfo(HexagonSubtarget &st);
4848
4949 /// Code Generation virtual methods...
50 const uint16_t *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
50 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
5151
5252 const TargetRegisterClass* const* getCalleeSavedRegClasses(
5353 const MachineFunction *MF = 0) const;
389389 /// callee-saved register.
390390 static bool DoesModifyCalleeSavedReg(MachineInstr *MI,
391391 const TargetRegisterInfo *TRI) {
392 for (const uint16_t *CSR = TRI->getCalleeSavedRegs(); *CSR; ++CSR) {
392 for (const MCPhysReg *CSR = TRI->getCalleeSavedRegs(); *CSR; ++CSR) {
393393 unsigned CalleeSavedReg = *CSR;
394394 if (MI->modifiesRegister(CalleeSavedReg, TRI))
395395 return true;
283283 static void AnalyzeArguments(CCState &State,
284284 SmallVectorImpl &ArgLocs,
285285 const SmallVectorImpl &Args) {
286 static const uint16_t RegList[] = {
286 static const MCPhysReg RegList[] = {
287287 MSP430::R15W, MSP430::R14W, MSP430::R13W, MSP430::R12W
288288 };
289289 static const unsigned NbRegs = array_lengthof(RegList);
3636 StackAlign = TM.getFrameLowering()->getStackAlignment();
3737 }
3838
39 const uint16_t*
39 const MCPhysReg*
4040 MSP430RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
4141 const TargetFrameLowering *TFI = MF->getTarget().getFrameLowering();
4242 const Function* F = MF->getFunction();
43 static const uint16_t CalleeSavedRegs[] = {
43 static const MCPhysReg CalleeSavedRegs[] = {
4444 MSP430::FPW, MSP430::R5W, MSP430::R6W, MSP430::R7W,
4545 MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W,
4646 0
4747 };
48 static const uint16_t CalleeSavedRegsFP[] = {
48 static const MCPhysReg CalleeSavedRegsFP[] = {
4949 MSP430::R5W, MSP430::R6W, MSP430::R7W,
5050 MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W,
5151 0
5252 };
53 static const uint16_t CalleeSavedRegsIntr[] = {
53 static const MCPhysReg CalleeSavedRegsIntr[] = {
5454 MSP430::FPW, MSP430::R5W, MSP430::R6W, MSP430::R7W,
5555 MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W,
5656 MSP430::R12W, MSP430::R13W, MSP430::R14W, MSP430::R15W,
5757 0
5858 };
59 static const uint16_t CalleeSavedRegsIntrFP[] = {
59 static const MCPhysReg CalleeSavedRegsIntrFP[] = {
6060 MSP430::R5W, MSP430::R6W, MSP430::R7W,
6161 MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W,
6262 MSP430::R12W, MSP430::R13W, MSP430::R14W, MSP430::R15W,
3434 MSP430RegisterInfo(MSP430TargetMachine &tm);
3535
3636 /// Code Generation virtual methods...
37 const uint16_t *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
37 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
3838
3939 BitVector getReservedRegs(const MachineFunction &MF) const;
4040 const TargetRegisterClass*
109109 Offset = std::max(Offset, -MFI->getObjectOffset(I));
110110
111111 // Conservatively assume all callee-saved registers will be saved.
112 for (const uint16_t *R = TRI.getCalleeSavedRegs(&MF); *R; ++R) {
112 for (const MCPhysReg *R = TRI.getCalleeSavedRegs(&MF); *R; ++R) {
113113 unsigned Size = TRI.getMinimalPhysRegClass(*R)->getSize();
114114 Offset = RoundUpToAlignment(Offset + Size, Size);
115115 }
4949 cl::desc("MIPS: Don't trap on integer division by zero."),
5050 cl::init(false));
5151
52 static const uint16_t O32IntRegs[4] = {
52 static const MCPhysReg O32IntRegs[4] = {
5353 Mips::A0, Mips::A1, Mips::A2, Mips::A3
5454 };
5555
56 static const uint16_t Mips64IntRegs[8] = {
56 static const MCPhysReg Mips64IntRegs[8] = {
5757 Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64,
5858 Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64
5959 };
6060
61 static const uint16_t Mips64DPRegs[8] = {
61 static const MCPhysReg Mips64DPRegs[8] = {
6262 Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
6363 Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64
6464 };
21762176
21772177 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, MVT LocVT,
21782178 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
2179 CCState &State, const uint16_t *F64Regs) {
2179 CCState &State, const MCPhysReg *F64Regs) {
21802180
21812181 static const unsigned IntRegsSize = 4, FloatRegsSize = 2;
21822182
2183 static const uint16_t IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 };
2184 static const uint16_t F32Regs[] = { Mips::F12, Mips::F14 };
2183 static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 };
2184 static const MCPhysReg F32Regs[] = { Mips::F12, Mips::F14 };
21852185
21862186 // Do not process byval args here.
21872187 if (ArgFlags.isByVal())
22532253 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT,
22542254 MVT LocVT, CCValAssign::LocInfo LocInfo,
22552255 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2256 static const uint16_t F64Regs[] = { Mips::D6, Mips::D7 };
2256 static const MCPhysReg F64Regs[] = { Mips::D6, Mips::D7 };
22572257
22582258 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
22592259 }
22612261 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT,
22622262 MVT LocVT, CCValAssign::LocInfo LocInfo,
22632263 ISD::ArgFlagsTy ArgFlags, CCState &State) {
2264 static const uint16_t F64Regs[] = { Mips::D12_64, Mips::D14_64 };
2264 static const MCPhysReg F64Regs[] = { Mips::D12_64, Mips::D14_64 };
22652265
22662266 return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);
22672267 }
34253425 return (IsO32 && (CallConv != CallingConv::Fast)) ? 16 : 0;
34263426 }
34273427
3428 const uint16_t *MipsTargetLowering::MipsCC::intArgRegs() const {
3428 const MCPhysReg *MipsTargetLowering::MipsCC::intArgRegs() const {
34293429 return IsO32 ? O32IntRegs : Mips64IntRegs;
34303430 }
34313431
34423442 return IsO32 ? (IsFP64 ? CC_MipsO32_FP64 : CC_MipsO32_FP32) : CC_MipsN_VarArg;
34433443 }
34443444
3445 const uint16_t *MipsTargetLowering::MipsCC::shadowRegs() const {
3445 const MCPhysReg *MipsTargetLowering::MipsCC::shadowRegs() const {
34463446 return IsO32 ? O32IntRegs : Mips64DPRegs;
34473447 }
34483448
34503450 unsigned ByValSize,
34513451 unsigned Align) {
34523452 unsigned RegSize = regSize(), NumIntArgRegs = numIntArgRegs();
3453 const uint16_t *IntArgRegs = intArgRegs(), *ShadowRegs = shadowRegs();
3453 const MCPhysReg *IntArgRegs = intArgRegs(), *ShadowRegs = shadowRegs();
34543454 assert(!(ByValSize % RegSize) && !(Align % RegSize) &&
34553455 "Byval argument's size and alignment should be a multiple of"
34563456 "RegSize.");
35423542 EVT PtrTy = getPointerTy(), RegTy = MVT::getIntegerVT(RegSize * 8);
35433543
35443544 if (ByVal.NumRegs) {
3545 const uint16_t *ArgRegs = CC.intArgRegs();
3545 const MCPhysReg *ArgRegs = CC.intArgRegs();
35463546 bool LeftoverBytes = (ByVal.NumRegs * RegSize > ByValSize);
35473547 unsigned I = 0;
35483548
36273627 const MipsCC &CC, SDValue Chain,
36283628 SDLoc DL, SelectionDAG &DAG) const {
36293629 unsigned NumRegs = CC.numIntArgRegs();
3630 const uint16_t *ArgRegs = CC.intArgRegs();
3630 const MCPhysReg *ArgRegs = CC.intArgRegs();
36313631 const CCState &CCInfo = CC.getCCInfo();
36323632 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs, NumRegs);
36333633 unsigned RegSize = CC.regSize();
381381 unsigned reservedArgArea() const;
382382
383383 /// Return pointer to array of integer argument registers.
384 const uint16_t *intArgRegs() const;
384 const MCPhysReg *intArgRegs() const;
385385
386386 typedef SmallVectorImpl::const_iterator byval_iterator;
387387 byval_iterator byval_begin() const { return ByValArgs.begin(); }
402402 /// Return the function that analyzes variable argument list functions.
403403 llvm::CCAssignFn *varArgFn() const;
404404
405 const uint16_t *shadowRegs() const;
405 const MCPhysReg *shadowRegs() const;
406406
407407 void allocateRegs(ByValArgInfo &ByVal, unsigned ByValSize,
408408 unsigned Align);
7878 //===----------------------------------------------------------------------===//
7979
8080 /// Mips Callee Saved Registers
81 const uint16_t* MipsRegisterInfo::
82 getCalleeSavedRegs(const MachineFunction *MF) const {
81 const MCPhysReg *
82 MipsRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
8383 if (Subtarget.isSingleFloat())
8484 return CSR_SingleFloatOnly_SaveList;
8585
118118
119119 BitVector MipsRegisterInfo::
120120 getReservedRegs(const MachineFunction &MF) const {
121 static const uint16_t ReservedGPR32[] = {
121 static const MCPhysReg ReservedGPR32[] = {
122122 Mips::ZERO, Mips::K0, Mips::K1, Mips::SP
123123 };
124124
125 static const uint16_t ReservedGPR64[] = {
125 static const MCPhysReg ReservedGPR64[] = {
126126 Mips::ZERO_64, Mips::K0_64, Mips::K1_64, Mips::SP_64
127127 };
128128
4646
4747 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
4848 MachineFunction &MF) const;
49 const uint16_t *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
49 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
5050 const uint32_t *getCallPreservedMask(CallingConv::ID) const;
5151 static const uint32_t *getMips16RetHelperMask();
5252
7777 #include "NVPTXGenRegisterInfo.inc"
7878
7979 /// NVPTX Callee Saved Registers
80 const uint16_t *
80 const MCPhysReg *
8181 NVPTXRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
82 static const uint16_t CalleeSavedRegs[] = { 0 };
82 static const MCPhysReg CalleeSavedRegs[] = { 0 };
8383 return CalleeSavedRegs;
8484 }
8585
4141 //------------------------------------------------------
4242
4343 // NVPTX callee saved registers
44 virtual const uint16_t *
44 virtual const MCPhysReg *
4545 getCalleeSavedRegs(const MachineFunction *MF = 0) const;
4646
4747 // NVPTX callee saved register classes
20152015 CCValAssign::LocInfo &LocInfo,
20162016 ISD::ArgFlagsTy &ArgFlags,
20172017 CCState &State) {
2018 static const uint16_t ArgRegs[] = {
2018 static const MCPhysReg ArgRegs[] = {
20192019 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
20202020 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
20212021 };
20422042 CCValAssign::LocInfo &LocInfo,
20432043 ISD::ArgFlagsTy &ArgFlags,
20442044 CCState &State) {
2045 static const uint16_t ArgRegs[] = {
2045 static const MCPhysReg ArgRegs[] = {
20462046 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
20472047 PPC::F8
20482048 };
20662066
20672067 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
20682068 /// on Darwin.
2069 static const uint16_t *GetFPR() {
2070 static const uint16_t FPR[] = {
2069 static const MCPhysReg *GetFPR() {
2070 static const MCPhysReg FPR[] = {
20712071 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
20722072 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
20732073 };
22642264 // If the function takes variable number of arguments, make a frame index for
22652265 // the start of the first vararg value... for expansion of llvm.va_start.
22662266 if (isVarArg) {
2267 static const uint16_t GPArgRegs[] = {
2267 static const MCPhysReg GPArgRegs[] = {
22682268 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
22692269 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
22702270 };
22712271 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
22722272
2273 static const uint16_t FPArgRegs[] = {
2273 static const MCPhysReg FPArgRegs[] = {
22742274 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
22752275 PPC::F8
22762276 };
24042404 // Area that is at least reserved in caller of this function.
24052405 unsigned MinReservedArea = ArgOffset;
24062406
2407 static const uint16_t GPR[] = {
2407 static const MCPhysReg GPR[] = {
24082408 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
24092409 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
24102410 };
24112411
2412 static const uint16_t *FPR = GetFPR();
2413
2414 static const uint16_t VR[] = {
2412 static const MCPhysReg *FPR = GetFPR();
2413
2414 static const MCPhysReg VR[] = {
24152415 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
24162416 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
24172417 };
2418 static const uint16_t VSRH[] = {
2418 static const MCPhysReg VSRH[] = {
24192419 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
24202420 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
24212421 };
27132713 // Area that is at least reserved in caller of this function.
27142714 unsigned MinReservedArea = ArgOffset;
27152715
2716 static const uint16_t GPR_32[] = { // 32-bit registers.
2716 static const MCPhysReg GPR_32[] = { // 32-bit registers.
27172717 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
27182718 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
27192719 };
2720 static const uint16_t GPR_64[] = { // 64-bit registers.
2720 static const MCPhysReg GPR_64[] = { // 64-bit registers.
27212721 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
27222722 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
27232723 };
27242724
2725 static const uint16_t *FPR = GetFPR();
2726
2727 static const uint16_t VR[] = {
2725 static const MCPhysReg *FPR = GetFPR();
2726
2727 static const MCPhysReg VR[] = {
27282728 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
27292729 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
27302730 };
27352735
27362736 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
27372737
2738 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32;
2738 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
27392739
27402740 // In 32-bit non-varargs functions, the stack space for vectors is after the
27412741 // stack space for non-vectors. We do not use this space unless we have
40434043 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true);
40444044 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
40454045
4046 static const uint16_t GPR[] = {
4046 static const MCPhysReg GPR[] = {
40474047 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
40484048 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
40494049 };
4050 static const uint16_t *FPR = GetFPR();
4051
4052 static const uint16_t VR[] = {
4050 static const MCPhysReg *FPR = GetFPR();
4051
4052 static const MCPhysReg VR[] = {
40534053 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
40544054 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
40554055 };
4056 static const uint16_t VSRH[] = {
4056 static const MCPhysReg VSRH[] = {
40574057 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
40584058 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
40594059 };
44474447 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
44484448 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
44494449
4450 static const uint16_t GPR_32[] = { // 32-bit registers.
4450 static const MCPhysReg GPR_32[] = { // 32-bit registers.
44514451 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
44524452 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
44534453 };
4454 static const uint16_t GPR_64[] = { // 64-bit registers.
4454 static const MCPhysReg GPR_64[] = { // 64-bit registers.
44554455 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
44564456 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
44574457 };
4458 static const uint16_t *FPR = GetFPR();
4459
4460 static const uint16_t VR[] = {
4458 static const MCPhysReg *FPR = GetFPR();
4459
4460 static const MCPhysReg VR[] = {
44614461 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
44624462 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
44634463 };
44654465 const unsigned NumFPRs = 13;
44664466 const unsigned NumVRs = array_lengthof(VR);
44674467
4468 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32;
4468 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
44694469
44704470 SmallVector, 8> RegsToPass;
44714471 SmallVector TailCallArguments;
9595 return &PPC::GPRCRegClass;
9696 }
9797
98 const uint16_t*
98 const MCPhysReg*
9999 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
100100 if (Subtarget.isDarwinABI())
101101 return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ?
4343 getLargestLegalSuperClass(const TargetRegisterClass *RC) const;
4444
4545 /// Code Generation virtual methods...
46 const uint16_t *getCalleeSavedRegs(const MachineFunction* MF = 0) const;
46 const MCPhysReg *getCalleeSavedRegs(const MachineFunction* MF = 0) const;
4747 const uint32_t *getCallPreservedMask(CallingConv::ID CC) const;
4848 const uint32_t *getNoPreservedMask() const;
4949
2626 // they are not supported at this time.
2727 //===----------------------------------------------------------------------===//
2828
29 const uint16_t AMDGPURegisterInfo::CalleeSavedReg = AMDGPU::NoRegister;
29 const MCPhysReg AMDGPURegisterInfo::CalleeSavedReg = AMDGPU::NoRegister;
3030
31 const uint16_t* AMDGPURegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
32 const {
31 const MCPhysReg*
32 AMDGPURegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
3333 return &CalleeSavedReg;
3434 }
3535
2929
3030 struct AMDGPURegisterInfo : public AMDGPUGenRegisterInfo {
3131 TargetMachine &TM;
32 static const uint16_t CalleeSavedReg;
32 static const MCPhysReg CalleeSavedReg;
3333
3434 AMDGPURegisterInfo(TargetMachine &tm);
3535
5757 /// (e.g. getSubRegFromChannel(0) -> AMDGPU::sub0)
5858 unsigned getSubRegFromChannel(unsigned Channel) const;
5959
60 const uint16_t* getCalleeSavedRegs(const MachineFunction *MF) const;
60 const MCPhysReg* getCalleeSavedRegs(const MachineFunction *MF) const;
6161 void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
6262 unsigned FIOperandNum,
6363 RegScavenger *RS) const;
5252 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
5353 ISD::ArgFlagsTy &ArgFlags, CCState &State)
5454 {
55 static const uint16_t RegList[] = {
55 static const MCPhysReg RegList[] = {
5656 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
5757 };
5858 // Try to get first reg.
492492
493493 // Store remaining ArgRegs to the stack if this is a varargs function.
494494 if (isVarArg) {
495 static const uint16_t ArgRegs[] = {
495 static const MCPhysReg ArgRegs[] = {
496496 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
497497 };
498498 unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs, 6);
499 const uint16_t *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6;
499 const MCPhysReg *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6;
500500 unsigned ArgOffset = CCInfo.getNextStackOffset();
501501 if (NumAllocated == 6)
502502 ArgOffset += StackOffset;
3737 : SparcGenRegisterInfo(SP::O7), Subtarget(st) {
3838 }
3939
40 const uint16_t* SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
41 const {
40 const MCPhysReg*
41 SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
4242 return CSR_SaveList;
4343 }
4444
3030 SparcRegisterInfo(SparcSubtarget &st);
3131
3232 /// Code Generation virtual methods...
33 const uint16_t *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
33 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
3434 const uint32_t* getCallPreservedMask(CallingConv::ID CC) const;
3535
3636 const uint32_t* getRTCallPreservedMask(CallingConv::ID CC) const;
9292 // save and restore the stack pointer at the same time, via STMG and LMG.
9393 // This allows the deallocation to be done by the LMG, rather than needing
9494 // a separate %r15 addition.
95 const uint16_t *CSRegs = TRI->getCalleeSavedRegs(&MF);
95 const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF);
9696 for (unsigned I = 0; CSRegs[I]; ++I) {
9797 unsigned Reg = CSRegs[I];
9898 if (SystemZ::GR64BitRegClass.contains(Reg) && MRI.isPhysRegUsed(Reg)) {
1919 SystemZRegisterInfo::SystemZRegisterInfo(SystemZTargetMachine &tm)
2020 : SystemZGenRegisterInfo(SystemZ::R14D), TM(tm) {}
2121
22 const uint16_t*
22 const MCPhysReg*
2323 SystemZRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
24 static const uint16_t CalleeSavedRegs[] = {
24 static const MCPhysReg CalleeSavedRegs[] = {
2525 SystemZ::R6D, SystemZ::R7D, SystemZ::R8D, SystemZ::R9D,
2626 SystemZ::R10D, SystemZ::R11D, SystemZ::R12D, SystemZ::R13D,
2727 SystemZ::R14D, SystemZ::R15D,
4848 bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override {
4949 return true;
5050 }
51 const uint16_t *getCalleeSavedRegs(const MachineFunction *MF = 0) const
51 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF = 0) const
5252 override;
5353 BitVector getReservedRegs(const MachineFunction &MF) const override;
5454 void eliminateFrameIndex(MachineBasicBlock::iterator MI,
18201820 }
18211821 }
18221822
1823 static const uint16_t GPR32ArgRegs[] = {
1823 static const MCPhysReg GPR32ArgRegs[] = {
18241824 X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D
18251825 };
1826 static const uint16_t GPR64ArgRegs[] = {
1826 static const MCPhysReg GPR64ArgRegs[] = {
18271827 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8 , X86::R9
18281828 };
18291829
21622162
21632163 if (Subtarget->is64Bit() && isVarArg && !isWin64) {
21642164 // Count the number of XMM registers allocated.
2165 static const uint16_t XMMArgRegs[] = {
2165 static const MCPhysReg XMMArgRegs[] = {
21662166 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
21672167 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
21682168 };
18051805 return CCInfo.CheckReturn(Outs, RetCC_X86);
18061806 }
18071807
1808 const uint16_t *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1809 static const uint16_t ScratchRegs[] = { X86::R11, 0 };
1808 const MCPhysReg *X86TargetLowering::getScratchRegisters(CallingConv::ID) const {
1809 static const MCPhysReg ScratchRegs[] = { X86::R11, 0 };
18101810 return ScratchRegs;
18111811 }
18121812
23192319 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0;
23202320
23212321 // FIXME: We should really autogenerate these arrays
2322 static const uint16_t GPR64ArgRegsWin64[] = {
2322 static const MCPhysReg GPR64ArgRegsWin64[] = {
23232323 X86::RCX, X86::RDX, X86::R8, X86::R9
23242324 };
2325 static const uint16_t GPR64ArgRegs64Bit[] = {
2325 static const MCPhysReg GPR64ArgRegs64Bit[] = {
23262326 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9
23272327 };
2328 static const uint16_t XMMArgRegs64Bit[] = {
2328 static const MCPhysReg XMMArgRegs64Bit[] = {
23292329 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
23302330 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
23312331 };
2332 const uint16_t *GPR64ArgRegs;
2332 const MCPhysReg *GPR64ArgRegs;
23332333 unsigned NumXMMRegs = 0;
23342334
23352335 if (IsWin64) {
27292729 // registers used and is in the range 0 - 8 inclusive.
27302730
27312731 // Count the number of XMM registers allocated.
2732 static const uint16_t XMMArgRegs[] = {
2732 static const MCPhysReg XMMArgRegs[] = {
27332733 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3,
27342734 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7
27352735 };
935935 const SmallVectorImpl &Outs,
936936 LLVMContext &Context) const override;
937937
938 const uint16_t *getScratchRegisters(CallingConv::ID CC) const override;
938 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
939939
940940 /// Utility function to emit atomic-load-arith operations (and, or, xor,
941941 /// nand, max, min, umax, umin). It takes the corresponding instruction to
230230 }
231231 }
232232
233 const uint16_t *
233 const MCPhysReg *
234234 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
235235 bool HasAVX = TM.getSubtarget().hasAVX();
236236 bool HasAVX512 = TM.getSubtarget().hasAVX512();
9999
100100 /// getCalleeSavedRegs - Return a null-terminated list of all of the
101101 /// callee-save registers on this target.
102 const uint16_t *
102 const MCPhysReg *
103103 getCalleeSavedRegs(const MachineFunction* MF) const override;
104104 const uint32_t *getCallPreservedMask(CallingConv::ID) const override;
105105 const uint32_t *getNoPreservedMask() const;
13831383 // 1b. CopyFromReg vararg registers.
13841384 if (isVarArg) {
13851385 // Argument registers
1386 static const uint16_t ArgRegs[] = {
1386 static const MCPhysReg ArgRegs[] = {
13871387 XCore::R0, XCore::R1, XCore::R2, XCore::R3
13881388 };
13891389 XCoreFunctionInfo *XFI = MF.getInfo();
204204 MF.getFunction()->needsUnwindTableEntry();
205205 }
206206
207 const uint16_t* XCoreRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
207 const MCPhysReg* XCoreRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
208208 const {
209209 // The callee saved registers LR & FP are explicitly handled during
210210 // emitPrologue & emitEpilogue and related functions.
211 static const uint16_t CalleeSavedRegs[] = {
211 static const MCPhysReg CalleeSavedRegs[] = {
212212 XCore::R4, XCore::R5, XCore::R6, XCore::R7,
213213 XCore::R8, XCore::R9, XCore::R10,
214214 0
215215 };
216 static const uint16_t CalleeSavedRegsFP[] = {
216 static const MCPhysReg CalleeSavedRegsFP[] = {
217217 XCore::R4, XCore::R5, XCore::R6, XCore::R7,
218218 XCore::R8, XCore::R9,
219219 0
2828
2929 /// Code Generation virtual methods...
3030
31 const uint16_t *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
31 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
3232
3333 BitVector getReservedRegs(const MachineFunction &MF) const;
3434
111111 O << IndentStr << "if (unsigned Reg = State.AllocateReg(";
112112 O << getQualifiedName(RegList->getElementAsRecord(0)) << ")) {\n";
113113 } else {
114 O << IndentStr << "static const uint16_t RegList" << ++Counter
114 O << IndentStr << "static const MCPhysReg RegList" << ++Counter
115115 << "[] = {\n";
116116 O << IndentStr << " ";
117117 for (unsigned i = 0, e = RegList->getSize(); i != e; ++i) {
142142 unsigned RegListNumber = ++Counter;
143143 unsigned ShadowRegListNumber = ++Counter;
144144
145 O << IndentStr << "static const uint16_t RegList" << RegListNumber
145 O << IndentStr << "static const MCPhysReg RegList" << RegListNumber
146146 << "[] = {\n";
147147 O << IndentStr << " ";
148148 for (unsigned i = 0, e = RegList->getSize(); i != e; ++i) {
151151 }
152152 O << "\n" << IndentStr << "};\n";
153153
154 O << IndentStr << "static const uint16_t RegList"
154 O << IndentStr << "static const MCPhysReg RegList"
155155 << ShadowRegListNumber << "[] = {\n";
156156 O << IndentStr << " ";
157157 for (unsigned i = 0, e = ShadowRegList->getSize(); i != e; ++i) {
195195
196196 unsigned ShadowRegListNumber = ++Counter;
197197
198 O << IndentStr << "static const uint16_t ShadowRegList"
198 O << IndentStr << "static const MCPhysReg ShadowRegList"
199199 << ShadowRegListNumber << "[] = {\n";
200200 O << IndentStr << " ";
201201 for (unsigned i = 0, e = ShadowRegList->getSize(); i != e; ++i) {
830830
831831 // Emit the table of register unit roots. Each regunit has one or two root
832832 // registers.
833 OS << "extern const uint16_t " << TargetName << "RegUnitRoots[][2] = {\n";
833 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2] = {\n";
834834 for (unsigned i = 0, e = RegBank.getNumNativeRegUnits(); i != e; ++i) {
835835 ArrayRef Roots = RegBank.getRegUnit(i).getRoots();
836836 assert(!Roots.empty() && "All regunits must have a root register.");
857857
858858 // Emit the register list now.
859859 OS << " // " << Name << " Register Class...\n"
860 << " const uint16_t " << Name
860 << " const MCPhysReg " << Name
861861 << "[] = {\n ";
862862 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
863863 Record *Reg = Order[i];
12661266 OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n";
12671267 OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[];\n";
12681268 OS << "extern const char " << TargetName << "RegStrings[];\n";
1269 OS << "extern const uint16_t " << TargetName << "RegUnitRoots[][2];\n";
1269 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2];\n";
12701270 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[];\n";
12711271 OS << "extern const MCRegisterInfo::SubRegCoveredBits "
12721272 << TargetName << "SubRegIdxRanges[];\n";