llvm.org GIT mirror llvm / 84f47c5
InlineAsm asm support for integer registers added git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41225 91177308-0d34-0410-b5e6-96231b3b80d8 Bruno Cardoso Lopes 13 years ago
2 changed file(s) with 81 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
1919 #include "llvm/Function.h"
2020 #include "llvm/Intrinsics.h"
2121 #include "llvm/CallingConv.h"
22 #include "llvm/ADT/VectorExtras.h"
2223 #include "llvm/CodeGen/CallingConvLower.h"
2324 #include "llvm/CodeGen/MachineFrameInfo.h"
2425 #include "llvm/CodeGen/MachineFunction.h"
550551 return DAG.getNode(MipsISD::Ret, MVT::Other,
551552 Chain, DAG.getRegister(Mips::RA, MVT::i32));
552553 }
554
555 //===----------------------------------------------------------------------===//
556 // Mips Inline Assembly Support
557 //===----------------------------------------------------------------------===//
558
559 /// getConstraintType - Given a constraint letter, return the type of
560 /// constraint it is for this target.
561 MipsTargetLowering::ConstraintType MipsTargetLowering::
562 getConstraintType(const std::string &Constraint) const
563 {
564 if (Constraint.size() == 1) {
565 // Mips specific constrainy
566 // GCC config/mips/constraints.md
567 //
568 // 'd' : An address register. Equivalent to r
569 // unless generating MIPS16 code.
570 // 'y' : Equivalent to r; retained for
571 // backwards compatibility.
572 //
573 switch (Constraint[0]) {
574 default : break;
575 case 'd':
576 case 'y':
577 return C_RegisterClass;
578 break;
579 }
580 }
581 return TargetLowering::getConstraintType(Constraint);
582 }
583
584 std::pair MipsTargetLowering::
585 getRegForInlineAsmConstraint(const std::string &Constraint,
586 MVT::ValueType VT) const
587 {
588 if (Constraint.size() == 1) {
589 switch (Constraint[0]) {
590 case 'r':
591 return std::make_pair(0U, Mips::CPURegsRegisterClass);
592 break;
593 }
594 }
595 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
596 }
597
598 std::vector MipsTargetLowering::
599 getRegClassForInlineAsmConstraint(const std::string &Constraint,
600 MVT::ValueType VT) const
601 {
602 if (Constraint.size() != 1)
603 return std::vector();
604
605 switch (Constraint[0]) {
606 default : break;
607 case 'r':
608 // GCC Mips Constraint Letters
609 case 'd':
610 case 'y':
611 return make_vector(Mips::V0, Mips::V1, Mips::A0,
612 Mips::A1, Mips::A2, Mips::A3,
613 Mips::T0, Mips::T1, Mips::T2,
614 Mips::T3, Mips::T4, Mips::T5,
615 Mips::T6, Mips::T7, Mips::S0,
616 Mips::S1, Mips::S2, Mips::S3,
617 Mips::S4, Mips::S5, Mips::S6,
618 Mips::S7, Mips::T8, Mips::T9, 0);
619 break;
620 }
621 return std::vector();
622 }
3939 // Return
4040 Ret,
4141
42 // Need to support addition with a input flag
4243 Add
4344 };
4445 }
7879 SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG);
7980 SDOperand LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG);
8081
82 // Inline asm support
83 ConstraintType getConstraintType(const std::string &Constraint) const;
84
85 std::pair
86 getRegForInlineAsmConstraint(const std::string &Constraint,
87 MVT::ValueType VT) const;
88
89 std::vector
90 getRegClassForInlineAsmConstraint(const std::string &Constraint,
91 MVT::ValueType VT) const;
8192 };
8293 }
8394