llvm.org GIT mirror llvm / 84bc542
Rename SSARegMap -> MachineRegisterInfo in keeping with the idea that "machine" classes are used to represent the current state of the code being compiled. Given this expanded name, we can start moving other stuff into it. For now, move the UsedPhysRegs and LiveIn/LoveOuts vectors from MachineFunction into it. Update all the clients to match. This also reduces some needless #includes, such as MachineModuleInfo from MachineFunction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45467 91177308-0d34-0410-b5e6-96231b3b80d8 Chris Lattner 12 years ago
53 changed file(s) with 558 addition(s) and 534 deletion(s). Raw diff Collapse all Expand all
2828 class MachineConstantPoolValue;
2929 class Mangler;
3030 class TargetAsmInfo;
31
31 class Type;
3232
3333 /// AsmPrinter - This class is intended to be used as a driving class for all
3434 /// asm writers.
3333 class LiveVariables;
3434 class MachineLoopInfo;
3535 class MRegisterInfo;
36 class SSARegMap;
36 class MachineRegisterInfo;
3737 class TargetInstrInfo;
3838 class TargetRegisterClass;
3939 class VirtRegMap;
307307
308308 bool alsoFoldARestore(int Id, int index, unsigned vr,
309309 BitVector &RestoreMBBs,
310 std::map > &RestoreIdxes);
310 std::map >&RestoreIdxes);
311311 void eraseRestoreInfo(int Id, int index, unsigned vr,
312312 BitVector &RestoreMBBs,
313 std::map > &RestoreIdxes);
314
315 /// rewriteInstructionForSpills, rewriteInstructionsForSpills - Helper functions
316 /// for addIntervalsForSpills to rewrite uses / defs for the given live range.
313 std::map >&RestoreIdxes);
314
315 /// rewriteInstructionForSpills, rewriteInstructionsForSpills - Helper
316 /// functions for addIntervalsForSpills to rewrite uses / defs for the given
317 /// live range.
317318 bool rewriteInstructionForSpills(const LiveInterval &li, bool TrySplit,
318319 unsigned id, unsigned index, unsigned end, MachineInstr *MI,
319320 MachineInstr *OrigDefMI, MachineInstr *DefMI, unsigned Slot, int LdSlot,
320321 bool isLoad, bool isLoadSS, bool DefIsReMat, bool CanDelete,
321 VirtRegMap &vrm, SSARegMap *RegMap, const TargetRegisterClass* rc,
322 VirtRegMap &vrm, MachineRegisterInfo &RegMap,
323 const TargetRegisterClass* rc,
322324 SmallVector &ReMatIds,
323325 unsigned &NewVReg, bool &HasDef, bool &HasUse,
324326 const MachineLoopInfo *loopInfo,
328330 LiveInterval::Ranges::const_iterator &I,
329331 MachineInstr *OrigDefMI, MachineInstr *DefMI, unsigned Slot, int LdSlot,
330332 bool isLoad, bool isLoadSS, bool DefIsReMat, bool CanDelete,
331 VirtRegMap &vrm, SSARegMap *RegMap, const TargetRegisterClass* rc,
333 VirtRegMap &vrm, MachineRegisterInfo &RegMap,
334 const TargetRegisterClass* rc,
332335 SmallVector &ReMatIds, const MachineLoopInfo *loopInfo,
333336 BitVector &SpillMBBs,
334337 std::map > &SpillIdxes,
1717 #ifndef LLVM_CODEGEN_MACHINEFUNCTION_H
1818 #define LLVM_CODEGEN_MACHINEFUNCTION_H
1919
20 #include "llvm/CodeGen/MachineModuleInfo.h"
2120 #include "llvm/CodeGen/MachineBasicBlock.h"
2221 #include "llvm/Support/Annotation.h"
23 #include "llvm/ADT/BitVector.h"
2422
2523 namespace llvm {
2624
2725 class Function;
2826 class TargetMachine;
29 class SSARegMap;
27 class MachineRegisterInfo;
3028 class MachineFrameInfo;
3129 class MachineConstantPool;
3230 class MachineJumpTableInfo;
8280 // List of machine basic blocks in function
8381 ilist BasicBlocks;
8482
85 // Keeping track of mapping from SSA values to registers
86 SSARegMap *SSARegMapping;
83 // RegInfo - Information about each register in use in the function.
84 MachineRegisterInfo *RegInfo;
8785
8886 // Used to keep track of target-specific per-machine function information for
8987 // the target implementation.
103101 // numbered and this vector keeps track of the mapping from ID's to MBB's.
104102 std::vector MBBNumbering;
105103
106 /// UsedPhysRegs - This is a bit vector that is computed and set by the
107 /// register allocator, and must be kept up to date by passes that run after
108 /// register allocation (though most don't modify this). This is used
109 /// so that the code generator knows which callee save registers to save and
110 /// for other target specific uses.
111 BitVector UsedPhysRegs;
112
113 /// LiveIns/LiveOuts - Keep track of the physical registers that are
114 /// livein/liveout of the function. Live in values are typically arguments in
115 /// registers, live out values are typically return values in registers.
116 /// LiveIn values are allowed to have virtual registers associated with them,
117 /// stored in the second element.
118 std::vector > LiveIns;
119 std::vector LiveOuts;
120
121104 public:
122105 MachineFunction(const Function *Fn, const TargetMachine &TM);
123106 ~MachineFunction();
130113 ///
131114 const TargetMachine &getTarget() const { return Target; }
132115
133 /// SSARegMap Interface... Keep track of information about each SSA virtual
134 /// register, such as which register class it belongs to.
135 ///
136 SSARegMap *getSSARegMap() const { return SSARegMapping; }
137 void clearSSARegMap();
116 /// getRegInfo - Return information about the registers currently in use.
117 ///
118 MachineRegisterInfo &getRegInfo() const { return *RegInfo; }
138119
139120 /// getFrameInfo - Return the frame info object for the current function.
140121 /// This object contains information about objects allocated on the stack
169150 const Ty *getInfo() const {
170151 return const_cast(this)->getInfo();
171152 }
172
173 /// isPhysRegUsed - Return true if the specified register is used in this
174 /// function. This only works after register allocation.
175 bool isPhysRegUsed(unsigned Reg) const { return UsedPhysRegs[Reg]; }
176
177 /// setPhysRegUsed - Mark the specified register used in this function.
178 /// This should only be called during and after register allocation.
179 void setPhysRegUsed(unsigned Reg) { UsedPhysRegs[Reg] = true; }
180
181 /// setPhysRegUnused - Mark the specified register unused in this function.
182 /// This should only be called during and after register allocation.
183 void setPhysRegUnused(unsigned Reg) { UsedPhysRegs[Reg] = false; }
184
185 // LiveIn/LiveOut management methods.
186
187 /// addLiveIn/Out - Add the specified register as a live in/out. Note that it
188 /// is an error to add the same register to the same set more than once.
189 void addLiveIn(unsigned Reg, unsigned vreg = 0) {
190 LiveIns.push_back(std::make_pair(Reg, vreg));
191 }
192 void addLiveOut(unsigned Reg) { LiveOuts.push_back(Reg); }
193
194 // Iteration support for live in/out sets. These sets are kept in sorted
195 // order by their register number.
196 typedef std::vector >::const_iterator
197 livein_iterator;
198 typedef std::vector::const_iterator liveout_iterator;
199 livein_iterator livein_begin() const { return LiveIns.begin(); }
200 livein_iterator livein_end() const { return LiveIns.end(); }
201 bool livein_empty() const { return LiveIns.empty(); }
202 liveout_iterator liveout_begin() const { return LiveOuts.begin(); }
203 liveout_iterator liveout_end() const { return LiveOuts.end(); }
204 bool liveout_empty() const { return LiveOuts.empty(); }
205153
206154 /// getBlockNumbered - MachineBasicBlocks are automatically numbered when they
207155 /// are inserted into the machine function. The block number for a machine
0 //===-- llvm/CodeGen/MachineRegisterInfo.h ----------------------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the MachineRegisterInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef LLVM_CODEGEN_MACHINEREGISTERINFO_H
14 #define LLVM_CODEGEN_MACHINEREGISTERINFO_H
15
16 #include "llvm/Target/MRegisterInfo.h"
17 #include "llvm/ADT/BitVector.h"
18 #include
19
20 namespace llvm {
21
22 /// MachineRegisterInfo - Keep track of information for each virtual register,
23 /// including its register class.
24 class MachineRegisterInfo {
25 /// VRegInfo - Information we keep for each virtual register. The entries in
26 /// this vector are actually converted to vreg numbers by adding the
27 /// MRegisterInfo::FirstVirtualRegister delta to their index.
28 std::vector VRegInfo;
29
30 /// UsedPhysRegs - This is a bit vector that is computed and set by the
31 /// register allocator, and must be kept up to date by passes that run after
32 /// register allocation (though most don't modify this). This is used
33 /// so that the code generator knows which callee save registers to save and
34 /// for other target specific uses.
35 BitVector UsedPhysRegs;
36
37 /// LiveIns/LiveOuts - Keep track of the physical registers that are
38 /// livein/liveout of the function. Live in values are typically arguments in
39 /// registers, live out values are typically return values in registers.
40 /// LiveIn values are allowed to have virtual registers associated with them,
41 /// stored in the second element.
42 std::vector > LiveIns;
43 std::vector LiveOuts;
44 public:
45 MachineRegisterInfo(const MRegisterInfo &MRI);
46
47
48 //===--------------------------------------------------------------------===//
49 // Virtual Register Info
50 //===--------------------------------------------------------------------===//
51
52 /// getRegClass - Return the register class of the specified virtual register.
53 const TargetRegisterClass *getRegClass(unsigned Reg) {
54 Reg -= MRegisterInfo::FirstVirtualRegister;
55 assert(Reg < VRegInfo.size() && "Invalid vreg!");
56 return VRegInfo[Reg];
57 }
58
59 /// createVirtualRegister - Create and return a new virtual register in the
60 /// function with the specified register class.
61 ///
62 unsigned createVirtualRegister(const TargetRegisterClass *RegClass) {
63 assert(RegClass && "Cannot create register without RegClass!");
64 VRegInfo.push_back(RegClass);
65 return getLastVirtReg();
66 }
67
68 /// getLastVirtReg - Return the highest currently assigned virtual register.
69 ///
70 unsigned getLastVirtReg() const {
71 return VRegInfo.size()+MRegisterInfo::FirstVirtualRegister-1;
72 }
73
74 //===--------------------------------------------------------------------===//
75 // Physical Register Use Info
76 //===--------------------------------------------------------------------===//
77
78 /// isPhysRegUsed - Return true if the specified register is used in this
79 /// function. This only works after register allocation.
80 bool isPhysRegUsed(unsigned Reg) const { return UsedPhysRegs[Reg]; }
81
82 /// setPhysRegUsed - Mark the specified register used in this function.
83 /// This should only be called during and after register allocation.
84 void setPhysRegUsed(unsigned Reg) { UsedPhysRegs[Reg] = true; }
85
86 /// setPhysRegUnused - Mark the specified register unused in this function.
87 /// This should only be called during and after register allocation.
88 void setPhysRegUnused(unsigned Reg) { UsedPhysRegs[Reg] = false; }
89
90
91 //===--------------------------------------------------------------------===//
92 // LiveIn/LiveOut Management
93 //===--------------------------------------------------------------------===//
94
95 /// addLiveIn/Out - Add the specified register as a live in/out. Note that it
96 /// is an error to add the same register to the same set more than once.
97 void addLiveIn(unsigned Reg, unsigned vreg = 0) {
98 LiveIns.push_back(std::make_pair(Reg, vreg));
99 }
100 void addLiveOut(unsigned Reg) { LiveOuts.push_back(Reg); }
101
102 // Iteration support for live in/out sets. These sets are kept in sorted
103 // order by their register number.
104 typedef std::vector >::const_iterator
105 livein_iterator;
106 typedef std::vector::const_iterator liveout_iterator;
107 livein_iterator livein_begin() const { return LiveIns.begin(); }
108 livein_iterator livein_end() const { return LiveIns.end(); }
109 bool livein_empty() const { return LiveIns.empty(); }
110 liveout_iterator liveout_begin() const { return LiveOuts.begin(); }
111 liveout_iterator liveout_end() const { return LiveOuts.end(); }
112 bool liveout_empty() const { return LiveOuts.empty(); }
113 };
114
115 } // End llvm namespace
116
117 #endif
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include/llvm/CodeGen/SSARegMap.h less more
None //===-- llvm/CodeGen/SSARegMap.h --------------------------------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the SSARegMap class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef LLVM_CODEGEN_SSAREGMAP_H
14 #define LLVM_CODEGEN_SSAREGMAP_H
15
16 #include "llvm/Target/MRegisterInfo.h"
17 #include
18
19 namespace llvm {
20
21 /// SSARegMap - Keep track of information for each virtual register, including
22 /// its register class.
23 class SSARegMap {
24 /// VRegInfo - Information we keep for each virtual register. The entries in
25 /// this vector are actually converted to vreg numbers by adding the
26 /// MRegisterInfo::FirstVirtualRegister delta to their index.
27 std::vector VRegInfo;
28
29 public:
30 SSARegMap() {
31 VRegInfo.reserve(256);
32 }
33
34 /// getRegClass - Return the register class of the specified virtual register.
35 const TargetRegisterClass *getRegClass(unsigned Reg) {
36 Reg -= MRegisterInfo::FirstVirtualRegister;
37 assert(Reg < VRegInfo.size() && "Invalid vreg!");
38 return VRegInfo[Reg];
39 }
40
41 /// createVirtualRegister - Create and return a new virtual register in the
42 /// function with the specified register class.
43 ///
44 unsigned createVirtualRegister(const TargetRegisterClass *RegClass) {
45 assert(RegClass && "Cannot create register without RegClass!");
46 VRegInfo.push_back(RegClass);
47 return getLastVirtReg();
48 }
49
50 /// getLastVirtReg - Return the highest currently assigned virtual register.
51 ///
52 unsigned getLastVirtReg() const {
53 return VRegInfo.size()+MRegisterInfo::FirstVirtualRegister-1;
54 }
55 };
56
57 } // End llvm namespace
58
59 #endif
2424 struct SUnit;
2525 class MachineConstantPool;
2626 class MachineModuleInfo;
27 class MachineRegisterInfo;
2728 class MachineInstr;
2829 class MRegisterInfo;
2930 class SelectionDAG;
3031 class SelectionDAGISel;
31 class SSARegMap;
3232 class TargetInstrInfo;
3333 class TargetInstrDescriptor;
3434 class TargetMachine;
242242 const TargetMachine &TM; // Target processor
243243 const TargetInstrInfo *TII; // Target instruction information
244244 const MRegisterInfo *MRI; // Target processor register info
245 SSARegMap *RegMap; // Virtual/real register map
245 MachineRegisterInfo &RegInfo; // Virtual/real register map
246246 MachineConstantPool *ConstPool; // Target constant pool
247247 std::vector Sequence; // The schedule. Null SUnit*'s
248248 // represent noop instructions.
252252 SmallSet CommuteSet; // Nodes the should be commuted.
253253
254254 ScheduleDAG(SelectionDAG &dag, MachineBasicBlock *bb,
255 const TargetMachine &tm)
256 : DAG(dag), BB(bb), TM(tm) {}
255 const TargetMachine &tm);
257256
258257 virtual ~ScheduleDAG() {}
259258
2222 namespace llvm {
2323 class SelectionDAGLowering;
2424 class SDOperand;
25 class SSARegMap;
25 class MachineRegisterInfo;
2626 class MachineBasicBlock;
2727 class MachineFunction;
2828 class MachineInstr;
3535 class SelectionDAGISel : public FunctionPass {
3636 public:
3737 TargetLowering &TLI;
38 SSARegMap *RegMap;
38 MachineRegisterInfo *RegInfo;
3939 SelectionDAG *CurDAG;
4040 MachineBasicBlock *BB;
4141 AliasAnalysis *AA;
3232 class RegScavenger;
3333 class SDNode;
3434 class SelectionDAG;
35 class SSARegMap;
3635 class TargetRegisterClass;
3736 class Type;
3837
1717 #include "llvm/Module.h"
1818 #include "llvm/CodeGen/MachineConstantPool.h"
1919 #include "llvm/CodeGen/MachineJumpTableInfo.h"
20 #include "llvm/CodeGen/MachineModuleInfo.h"
2021 #include "llvm/Support/CommandLine.h"
2122 #include "llvm/Support/Mangler.h"
2223 #include "llvm/Support/MathExtras.h"
2020 #include "llvm/CodeGen/MachineFrameInfo.h"
2121 #include "llvm/CodeGen/MachineFunctionPass.h"
2222 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineModuleInfo.h"
2324 #include "llvm/Target/TargetFrameInfo.h"
2425 #include "llvm/Target/TargetInstrInfo.h"
2526 #include "llvm/Target/TargetMachine.h"
2222 #include "llvm/CodeGen/MachineFrameInfo.h"
2323 #include "llvm/CodeGen/MachineInstr.h"
2424 #include "llvm/CodeGen/MachineLoopInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
2526 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/CodeGen/SSARegMap.h"
2727 #include "llvm/Target/MRegisterInfo.h"
2828 #include "llvm/Target/TargetInstrInfo.h"
2929 #include "llvm/Target/TargetMachine.h"
771771 MachineInstr *ReMatOrigDefMI, MachineInstr *ReMatDefMI,
772772 unsigned Slot, int LdSlot,
773773 bool isLoad, bool isLoadSS, bool DefIsReMat, bool CanDelete,
774 VirtRegMap &vrm, SSARegMap *RegMap,
774 VirtRegMap &vrm, MachineRegisterInfo &RegInfo,
775775 const TargetRegisterClass* rc,
776776 SmallVector &ReMatIds,
777777 unsigned &NewVReg, bool &HasDef, bool &HasUse,
868868 // Create a new virtual register for the spill interval.
869869 bool CreatedNewVReg = false;
870870 if (NewVReg == 0) {
871 NewVReg = RegMap->createVirtualRegister(rc);
871 NewVReg = RegInfo.createVirtualRegister(rc);
872872 vrm.grow();
873873 CreatedNewVReg = true;
874874 }
970970 MachineInstr *ReMatOrigDefMI, MachineInstr *ReMatDefMI,
971971 unsigned Slot, int LdSlot,
972972 bool isLoad, bool isLoadSS, bool DefIsReMat, bool CanDelete,
973 VirtRegMap &vrm, SSARegMap *RegMap,
973 VirtRegMap &vrm, MachineRegisterInfo &RegInfo,
974974 const TargetRegisterClass* rc,
975975 SmallVector &ReMatIds,
976976 const MachineLoopInfo *loopInfo,
10421042 bool CanFold = rewriteInstructionForSpills(li, TrySplit, I->valno->id,
10431043 index, end, MI, ReMatOrigDefMI, ReMatDefMI,
10441044 Slot, LdSlot, isLoad, isLoadSS, DefIsReMat,
1045 CanDelete, vrm, RegMap, rc, ReMatIds, NewVReg,
1045 CanDelete, vrm, RegInfo, rc, ReMatIds, NewVReg,
10461046 HasDef, HasUse, loopInfo, MBBVRegsMap, NewLIs);
10471047 if (!HasDef && !HasUse)
10481048 continue;
11881188 std::map > RestoreIdxes;
11891189 std::map MBBVRegsMap;
11901190 std::vector NewLIs;
1191 SSARegMap *RegMap = mf_->getSSARegMap();
1192 const TargetRegisterClass* rc = RegMap->getRegClass(li.reg);
1191 MachineRegisterInfo &RegInfo = mf_->getRegInfo();
1192 const TargetRegisterClass* rc = RegInfo.getRegClass(li.reg);
11931193
11941194 unsigned NumValNums = li.getNumValNums();
11951195 SmallVector ReMatDefs;
12341234 // Note ReMatOrigDefMI has already been deleted.
12351235 rewriteInstructionsForSpills(li, false, I, NULL, ReMatDefMI,
12361236 Slot, LdSlot, isLoad, isLoadSS, DefIsReMat,
1237 false, vrm, RegMap, rc, ReMatIds, loopInfo,
1237 false, vrm, RegInfo, rc, ReMatIds, loopInfo,
12381238 SpillMBBs, SpillIdxes, RestoreMBBs, RestoreIdxes,
12391239 MBBVRegsMap, NewLIs);
12401240 } else {
12411241 rewriteInstructionsForSpills(li, false, I, NULL, 0,
12421242 Slot, 0, false, false, false,
1243 false, vrm, RegMap, rc, ReMatIds, loopInfo,
1243 false, vrm, RegInfo, rc, ReMatIds, loopInfo,
12441244 SpillMBBs, SpillIdxes, RestoreMBBs, RestoreIdxes,
12451245 MBBVRegsMap, NewLIs);
12461246 }
13081308 (DefIsReMat && (ReMatDefMI->getInstrDescriptor()->Flags & M_LOAD_FLAG));
13091309 rewriteInstructionsForSpills(li, TrySplit, I, ReMatOrigDefMI, ReMatDefMI,
13101310 Slot, LdSlot, isLoad, isLoadSS, DefIsReMat,
1311 CanDelete, vrm, RegMap, rc, ReMatIds, loopInfo,
1311 CanDelete, vrm, RegInfo, rc, ReMatIds, loopInfo,
13121312 SpillMBBs, SpillIdxes, RestoreMBBs, RestoreIdxes,
13131313 MBBVRegsMap, NewLIs);
13141314 }
2727
2828 #include "llvm/CodeGen/LiveVariables.h"
2929 #include "llvm/CodeGen/MachineInstr.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
3031 #include "llvm/Target/MRegisterInfo.h"
3132 #include "llvm/Target/TargetInstrInfo.h"
3233 #include "llvm/Target/TargetMachine.h"
536537 // it as using all of the live-out values in the function.
537538 if (!MBB->empty() && TII.isReturn(MBB->back().getOpcode())) {
538539 MachineInstr *Ret = &MBB->back();
539 for (MachineFunction::liveout_iterator I = MF->liveout_begin(),
540 E = MF->liveout_end(); I != E; ++I) {
540 for (MachineRegisterInfo::liveout_iterator
541 I = MF->getRegInfo().liveout_begin(),
542 E = MF->getRegInfo().liveout_end(); I != E; ++I) {
541543 assert(MRegisterInfo::isPhysicalRegister(*I) &&
542544 "Cannot have a live-in virtual register!");
543545 HandlePhysRegUse(*I, Ret);
1111 #include "llvm/Function.h"
1212 #include "llvm/CodeGen/MachineFunctionPass.h"
1313 #include "llvm/CodeGen/MachineInstr.h"
14 #include "llvm/CodeGen/SSARegMap.h"
14 #include "llvm/CodeGen/MachineRegisterInfo.h"
1515 #include "llvm/Target/MRegisterInfo.h"
1616 #include "llvm/Target/TargetInstrInfo.h"
1717 #include "llvm/Target/TargetMachine.h"
8282 if (MRegisterInfo::isPhysicalRegister(DstReg)) {
8383 TRC = getPhysicalRegisterRegClass(MRI, DstReg);
8484 } else {
85 TRC = MF.getSSARegMap()->getRegClass(DstReg);
85 TRC = MF.getRegInfo().getRegClass(DstReg);
8686 }
8787 assert(TRC == getPhysicalRegisterRegClass(MRI, SrcReg) &&
8888 "Extract subreg and Dst must be of same register class");
154154 if (MRegisterInfo::isPhysicalRegister(InsReg)) {
155155 TRC1 = getPhysicalRegisterRegClass(MRI, InsReg);
156156 } else {
157 TRC1 = MF.getSSARegMap()->getRegClass(InsReg);
157 TRC1 = MF.getRegInfo().getRegClass(InsReg);
158158 }
159159 MRI.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1);
160160
178178 if (MRegisterInfo::isPhysicalRegister(DstReg)) {
179179 TRC0 = getPhysicalRegisterRegClass(MRI, DstReg);
180180 } else {
181 TRC0 = MF.getSSARegMap()->getRegClass(DstReg);
181 TRC0 = MF.getRegInfo().getRegClass(DstReg);
182182 }
183183 assert(TRC0 == getPhysicalRegisterRegClass(MRI, SrcReg) &&
184184 "Insert superreg and Dst must be of same register class");
203203 if (MRegisterInfo::isPhysicalRegister(InsReg)) {
204204 TRC1 = getPhysicalRegisterRegClass(MRI, InsReg);
205205 } else {
206 TRC1 = MF.getSSARegMap()->getRegClass(InsReg);
206 TRC1 = MF.getRegInfo().getRegClass(InsReg);
207207 }
208208 MRI.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1);
209209
1313 //===----------------------------------------------------------------------===//
1414
1515 #include "llvm/DerivedTypes.h"
16 #include "llvm/CodeGen/MachineConstantPool.h"
1617 #include "llvm/CodeGen/MachineFunctionPass.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
1719 #include "llvm/CodeGen/MachineInstr.h"
18 #include "llvm/CodeGen/SSARegMap.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineConstantPool.h"
2120 #include "llvm/CodeGen/MachineJumpTableInfo.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
2222 #include "llvm/CodeGen/Passes.h"
2323 #include "llvm/Target/TargetData.h"
2424 #include "llvm/Target/TargetLowering.h"
121121 MachineFunction::MachineFunction(const Function *F,
122122 const TargetMachine &TM)
123123 : Annotation(MF_AID), Fn(F), Target(TM) {
124 SSARegMapping = new SSARegMap();
124 RegInfo = new MachineRegisterInfo(*TM.getRegisterInfo());
125125 MFInfo = 0;
126126 FrameInfo = new MachineFrameInfo();
127127 ConstantPool = new MachineConstantPool(TM.getTargetData());
128 UsedPhysRegs.resize(TM.getRegisterInfo()->getNumRegs());
129128
130129 // Set up jump table.
131130 const TargetData &TD = *TM.getTargetData();
140139
141140 MachineFunction::~MachineFunction() {
142141 BasicBlocks.clear();
143 delete SSARegMapping;
142 delete RegInfo;
144143 delete MFInfo;
145144 delete FrameInfo;
146145 delete ConstantPool;
207206
208207 const MRegisterInfo *MRI = getTarget().getRegisterInfo();
209208
210 if (!livein_empty()) {
209 if (!RegInfo->livein_empty()) {
211210 OS << "Live Ins:";
212 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I) {
211 for (MachineRegisterInfo::livein_iterator
212 I = RegInfo->livein_begin(), E = RegInfo->livein_end(); I != E; ++I) {
213213 if (MRI)
214214 OS << " " << MRI->getName(I->first);
215215 else
220220 }
221221 OS << "\n";
222222 }
223 if (!liveout_empty()) {
223 if (!RegInfo->liveout_empty()) {
224224 OS << "Live Outs:";
225 for (liveout_iterator I = liveout_begin(), E = liveout_end(); I != E; ++I)
225 for (MachineRegisterInfo::liveout_iterator
226 I = RegInfo->liveout_begin(), E = RegInfo->liveout_end(); I != E; ++I)
226227 if (MRI)
227228 OS << " " << MRI->getName(*I);
228229 else
321322 MachineFunction *mc = (MachineFunction*)F->getAnnotation(MF_AID);
322323 assert(mc && "Call construct() method first to allocate the object");
323324 return *mc;
324 }
325
326 void MachineFunction::clearSSARegMap() {
327 delete SSARegMapping;
328 SSARegMapping = 0;
329325 }
330326
331327 //===----------------------------------------------------------------------===//
1111 //===----------------------------------------------------------------------===//
1212
1313 #include "llvm/CodeGen/MachineInstr.h"
14 #include "llvm/Value.h"
1415 #include "llvm/CodeGen/MachineFunction.h"
1516 #include "llvm/Target/TargetMachine.h"
1617 #include "llvm/Target/TargetInstrInfo.h"
0 //===-- MachineRegisterInfo.cpp -------------------------------------------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Implementation of the MachineRegisterInfo class.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "llvm/CodeGen/MachineRegisterInfo.h"
14 using namespace llvm;
15
16 MachineRegisterInfo::MachineRegisterInfo(const MRegisterInfo &MRI) {
17 VRegInfo.reserve(256);
18 UsedPhysRegs.resize(MRI.getNumRegs());
19 }
1717 #include "llvm/CodeGen/Passes.h"
1818 #include "llvm/CodeGen/MachineFunctionPass.h"
1919 #include "llvm/CodeGen/MachineInstr.h"
20 #include "llvm/CodeGen/SSARegMap.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
2121 #include "llvm/Target/TargetInstrInfo.h"
2222 #include "llvm/Target/TargetMachine.h"
2323 #include "llvm/ADT/STLExtras.h"
126126
127127 // Create a new register for the incoming PHI arguments.
128128 MachineFunction &MF = *MBB.getParent();
129 const TargetRegisterClass *RC = MF.getSSARegMap()->getRegClass(DestReg);
130 unsigned IncomingReg = MF.getSSARegMap()->createVirtualRegister(RC);
129 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
130 unsigned IncomingReg = MF.getRegInfo().createVirtualRegister(RC);
131131
132132 // Insert a register to register copy in the top of the current block (but
133133 // after any remaining phi nodes) which copies the new incoming register
1919 #include "llvm/CodeGen/MachineFunctionPass.h"
2020 #include "llvm/CodeGen/MachineInstr.h"
2121 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineModuleInfo.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
2224 #include "llvm/CodeGen/RegisterScavenging.h"
2325 #include "llvm/Target/TargetMachine.h"
2426 #include "llvm/Target/MRegisterInfo.h"
4749
4850 // Get MachineModuleInfo so that we can track the construction of the
4951 // frame.
50 if (MachineModuleInfo *MMI = getAnalysisToUpdate()) {
52 if (MachineModuleInfo *MMI = getAnalysisToUpdate())
5153 Fn.getFrameInfo()->setMachineModuleInfo(MMI);
52 }
5354
5455 // Allow the target machine to make some adjustments to the function
5556 // e.g. UsedPhysRegs before calculateCalleeSavedRegisters.
173174 std::vector CSI;
174175 for (unsigned i = 0; CSRegs[i]; ++i) {
175176 unsigned Reg = CSRegs[i];
176 if (Fn.isPhysRegUsed(Reg)) {
177 if (Fn.getRegInfo().isPhysRegUsed(Reg)) {
177178 // If the reg is modified, save it!
178179 CSI.push_back(CalleeSavedInfo(Reg, CSRegClasses[i]));
179180 } else {
180181 for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
181182 *AliasSet; ++AliasSet) { // Check alias registers too.
182 if (Fn.isPhysRegUsed(*AliasSet)) {
183 if (Fn.getRegInfo().isPhysRegUsed(*AliasSet)) {
183184 CSI.push_back(CalleeSavedInfo(Reg, CSRegClasses[i]));
184185 break;
185186 }
3131 #include "llvm/CodeGen/Passes.h"
3232 #include "llvm/CodeGen/MachineFunctionPass.h"
3333 #include "llvm/CodeGen/MachineInstr.h"
34 #include "llvm/CodeGen/SSARegMap.h"
3534 #include "llvm/CodeGen/MachineFrameInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
3636 #include "llvm/CodeGen/LiveVariables.h"
3737 #include "llvm/CodeGen/RegAllocRegistry.h"
3838 #include "llvm/Target/TargetInstrInfo.h"
325325 // register. We only need to spill it into its stack slot if it has been
326326 // modified.
327327 if (isVirtRegModified(VirtReg)) {
328 const TargetRegisterClass *RC = MF->getSSARegMap()->getRegClass(VirtReg);
328 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
329329 int FrameIndex = getStackSpaceFor(VirtReg, RC);
330330 DOUT << " to stack slot #" << FrameIndex;
331331 RegInfo->storeRegToStackSlot(MBB, I, PhysReg, true, FrameIndex, RC);
417417 ///
418418 unsigned RABigBlock::chooseReg(MachineBasicBlock &MBB, MachineInstr *I,
419419 unsigned VirtReg) {
420 const TargetRegisterClass *RC = MF->getSSARegMap()->getRegClass(VirtReg);
420 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
421421 // First check to see if we have a free register of the requested type...
422422 unsigned PhysReg = getFreeReg(RC);
423423
511511
512512 // Otherwise, if we have free physical registers available to hold the
513513 // value, use them.
514 const TargetRegisterClass *RC = MF->getSSARegMap()->getRegClass(VirtReg);
514 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
515515 unsigned PhysReg = getFreeReg(RC);
516516 int FrameIndex = getStackSpaceFor(VirtReg, RC);
517517
544544 RegInfo->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC);
545545 ++NumLoads; // Update statistics
546546
547 MF->setPhysRegUsed(PhysReg);
547 MF->getRegInfo().setPhysRegUsed(PhysReg);
548548 MI->getOperand(OpNum).setReg(PhysReg); // Assign the input register
549549 return MI;
550550 }
623623 // If this is the first basic block in the machine function, add live-in
624624 // registers as active.
625625 if (&MBB == &*MF->begin()) {
626 for (MachineFunction::livein_iterator I = MF->livein_begin(),
627 E = MF->livein_end(); I != E; ++I) {
626 for (MachineRegisterInfo::livein_iterator
627 I = MF->getRegInfo().livein_begin(),
628 E = MF->getRegInfo().livein_end(); I != E; ++I) {
628629 unsigned Reg = I->first;
629 MF->setPhysRegUsed(Reg);
630 MF->getRegInfo().setPhysRegUsed(Reg);
630631 PhysRegsUsed[Reg] = 0; // It is free and reserved now
631632 for (const unsigned *AliasSet = RegInfo->getSubRegisters(Reg);
632633 *AliasSet; ++AliasSet) {
633634 if (PhysRegsUsed[*AliasSet] != -2) {
634635 PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
635 MF->setPhysRegUsed(*AliasSet);
636 MF->getRegInfo().setPhysRegUsed(*AliasSet);
636637 }
637638 }
638639 }
730731 // larger registers). Ignore.
731732 if (isReadModWriteImplicitDef(MI, MO.getReg())) continue;
732733
733 MF->setPhysRegUsed(Reg);
734 MF->getRegInfo().setPhysRegUsed(Reg);
734735 spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in reg
735736 PhysRegsUsed[Reg] = 0; // It is free and reserved now
736737 for (const unsigned *AliasSet = RegInfo->getSubRegisters(Reg);
737738 *AliasSet; ++AliasSet) {
738739 if (PhysRegsUsed[*AliasSet] != -2) {
739740 PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
740 MF->setPhysRegUsed(*AliasSet);
741 MF->getRegInfo().setPhysRegUsed(*AliasSet);
741742 }
742743 }
743744 }
752753 spillPhysReg(MBB, MI, Reg, true);
753754 PhysRegsUsed[Reg] = 0; // It is free and reserved now
754755 }
755 MF->setPhysRegUsed(Reg);
756 MF->getRegInfo().setPhysRegUsed(Reg);
756757 for (const unsigned *AliasSet = RegInfo->getSubRegisters(Reg);
757758 *AliasSet; ++AliasSet) {
758759 if (PhysRegsUsed[*AliasSet] != -2) {
759760 PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
760 MF->setPhysRegUsed(*AliasSet);
761 MF->getRegInfo().setPhysRegUsed(*AliasSet);
761762 }
762763 }
763764 }
785786 // If DestVirtReg already has a value, use it.
786787 if (!(DestPhysReg = getVirt2PhysRegMapSlot(DestVirtReg)))
787788 DestPhysReg = chooseReg(MBB, MI, DestVirtReg);
788 MF->setPhysRegUsed(DestPhysReg);
789 MF->getRegInfo().setPhysRegUsed(DestPhysReg);
789790 markVirtRegModified(DestVirtReg);
790791 MI->getOperand(i).setReg(DestPhysReg); // Assign the output register
791792 }
867868
868869 // initialize the virtual->physical register map to have a 'null'
869870 // mapping for all virtual registers
870 Virt2PhysRegMap.grow(MF->getSSARegMap()->getLastVirtReg());
871 StackSlotForVirtReg.grow(MF->getSSARegMap()->getLastVirtReg());
872 VirtRegModified.resize(MF->getSSARegMap()->getLastVirtReg() - MRegisterInfo::FirstVirtualRegister + 1,0);
871 Virt2PhysRegMap.grow(MF->getRegInfo().getLastVirtReg());
872 StackSlotForVirtReg.grow(MF->getRegInfo().getLastVirtReg());
873 VirtRegModified.resize(MF->getRegInfo().getLastVirtReg() -
874 MRegisterInfo::FirstVirtualRegister + 1, 0);
873875
874876 // Loop over all of the basic blocks, eliminating virtual register references
875877 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
1818 #include "llvm/CodeGen/MachineFunctionPass.h"
1919 #include "llvm/CodeGen/MachineInstr.h"
2020 #include "llvm/CodeGen/MachineLoopInfo.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
2122 #include "llvm/CodeGen/Passes.h"
2223 #include "llvm/CodeGen/RegAllocRegistry.h"
2324 #include "llvm/CodeGen/RegisterCoalescer.h"
24 #include "llvm/CodeGen/SSARegMap.h"
2525 #include "llvm/Target/MRegisterInfo.h"
2626 #include "llvm/Target/TargetMachine.h"
2727 #include "llvm/Target/TargetInstrInfo.h"
6363 const TargetMachine* tm_;
6464 const MRegisterInfo* mri_;
6565 const TargetInstrInfo* tii_;
66 SSARegMap *regmap_;
66 MachineRegisterInfo *reginfo_;
6767 BitVector allocatableRegs_;
6868 LiveIntervals* li_;
6969 const MachineLoopInfo *loopInfo;
229229 if (Reg == SrcReg)
230230 return Reg;
231231
232 const TargetRegisterClass *RC = regmap_->getRegClass(cur.reg);
232 const TargetRegisterClass *RC = reginfo_->getRegClass(cur.reg);
233233 if (!RC->contains(SrcReg))
234234 return Reg;
235235
250250 tm_ = &fn.getTarget();
251251 mri_ = tm_->getRegisterInfo();
252252 tii_ = tm_->getInstrInfo();
253 regmap_ = mf_->getSSARegMap();
253 reginfo_ = &mf_->getRegInfo();
254254 allocatableRegs_ = mri_->getAllocatableSet(fn);
255255 li_ = &getAnalysis();
256256 loopInfo = &getAnalysis();
295295
296296 for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
297297 if (MRegisterInfo::isPhysicalRegister(i->second.reg)) {
298 mf_->setPhysRegUsed(i->second.reg);
298 reginfo_->setPhysRegUsed(i->second.reg);
299299 fixed_.push_back(std::make_pair(&i->second, i->second.begin()));
300300 } else
301301 unhandled_.push(&i->second);
507507
508508 std::vector > SpillWeightsToAdd;
509509 unsigned StartPosition = cur->beginNumber();
510 const TargetRegisterClass *RC = regmap_->getRegClass(cur->reg);
510 const TargetRegisterClass *RC = reginfo_->getRegClass(cur->reg);
511511 const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
512512
513513 // If this live interval is defined by a move instruction and its source is
539539 unsigned Reg = i->first->reg;
540540 assert(MRegisterInfo::isVirtualRegister(Reg) &&
541541 "Can only allocate virtual registers!");
542 const TargetRegisterClass *RegRC = regmap_->getRegClass(Reg);
542 const TargetRegisterClass *RegRC = reginfo_->getRegClass(Reg);
543543 // If this is not in a related reg class to the register we're allocating,
544544 // don't check it.
545545 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader &&
837837 std::vector inactiveCounts(mri_->getNumRegs(), 0);
838838 unsigned MaxInactiveCount = 0;
839839
840 const TargetRegisterClass *RC = regmap_->getRegClass(cur->reg);
840 const TargetRegisterClass *RC = reginfo_->getRegClass(cur->reg);
841841 const TargetRegisterClass *RCLeader = RelatedRegClasses.getLeaderValue(RC);
842842
843843 for (IntervalPtrs::iterator i = inactive_.begin(), e = inactive_.end();
848848
849849 // If this is not in a related reg class to the register we're allocating,
850850 // don't check it.
851 const TargetRegisterClass *RegRC = regmap_->getRegClass(reg);
851 const TargetRegisterClass *RegRC = reginfo_->getRegClass(reg);
852852 if (RelatedRegClasses.getLeaderValue(RegRC) == RCLeader) {
853853 reg = vrm_->getPhys(reg);
854854 ++inactiveCounts[reg];
1616 #include "llvm/CodeGen/Passes.h"
1717 #include "llvm/CodeGen/MachineFunctionPass.h"
1818 #include "llvm/CodeGen/MachineInstr.h"
19 #include "llvm/CodeGen/SSARegMap.h"
2019 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
2121 #include "llvm/CodeGen/LiveVariables.h"
2222 #include "llvm/CodeGen/RegAllocRegistry.h"
2323 #include "llvm/Target/TargetInstrInfo.h"
4848 private:
4949 const TargetMachine *TM;
5050 MachineFunction *MF;
51 const MRegisterInfo *RegInfo;
51 const MRegisterInfo *MRI;
5252 LiveVariables *LV;
5353
5454 // StackSlotForVirtReg - Maps virtual regs to the frame index where these
154154 ///
155155 bool areRegsEqual(unsigned R1, unsigned R2) const {
156156 if (R1 == R2) return true;
157 for (const unsigned *AliasSet = RegInfo->getAliasSet(R2);
157 for (const unsigned *AliasSet = MRI->getAliasSet(R2);
158158 *AliasSet; ++AliasSet) {
159159 if (*AliasSet == R1) return true;
160160 }
273273 assert(VirtReg && "Spilling a physical register is illegal!"
274274 " Must not have appropriate kill for the register or use exists beyond"
275275 " the intended one.");
276 DOUT << " Spilling register " << RegInfo->getName(PhysReg)
276 DOUT << " Spilling register " << MRI->getName(PhysReg)
277277 << " containing %reg" << VirtReg;
278278 if (!isVirtRegModified(VirtReg))
279279 DOUT << " which has not been modified, so no store necessary!";
282282 // register. We only need to spill it into its stack slot if it has been
283283 // modified.
284284 if (isVirtRegModified(VirtReg)) {
285 const TargetRegisterClass *RC = MF->getSSARegMap()->getRegClass(VirtReg);
285 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
286286 int FrameIndex = getStackSpaceFor(VirtReg, RC);
287287 DOUT << " to stack slot #" << FrameIndex;
288 RegInfo->storeRegToStackSlot(MBB, I, PhysReg, true, FrameIndex, RC);
288 MRI->storeRegToStackSlot(MBB, I, PhysReg, true, FrameIndex, RC);
289289 ++NumStores; // Update statistics
290290 }
291291
310310 } else {
311311 // If the selected register aliases any other registers, we must make
312312 // sure that one of the aliases isn't alive.
313 for (const unsigned *AliasSet = RegInfo->getAliasSet(PhysReg);
313 for (const unsigned *AliasSet = MRI->getAliasSet(PhysReg);
314314 *AliasSet; ++AliasSet)
315315 if (PhysRegsUsed[*AliasSet] != -1 && // Spill aliased register.
316316 PhysRegsUsed[*AliasSet] != -2) // If allocatable.
343343
344344 // If the selected register aliases any other allocated registers, it is
345345 // not free!
346 for (const unsigned *AliasSet = RegInfo->getAliasSet(PhysReg);
346 for (const unsigned *AliasSet = MRI->getAliasSet(PhysReg);
347347 *AliasSet; ++AliasSet)
348348 if (PhysRegsUsed[*AliasSet] != -1) // Aliased register in use?
349349 return false; // Can't use this reg then.
375375 ///
376376 unsigned RALocal::getReg(MachineBasicBlock &MBB, MachineInstr *I,
377377 unsigned VirtReg) {
378 const TargetRegisterClass *RC = MF->getSSARegMap()->getRegClass(VirtReg);
378 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
379379
380380 // First check to see if we have a free register of the requested type...
381381 unsigned PhysReg = getFreeReg(RC);
406406 } else {
407407 // If one of the registers aliased to the current register is
408408 // compatible, use it.
409 for (const unsigned *AliasIt = RegInfo->getAliasSet(R);
409 for (const unsigned *AliasIt = MRI->getAliasSet(R);
410410 *AliasIt; ++AliasIt) {
411411 if (RC->contains(*AliasIt) &&
412412 // If this is pinned down for some reason, don't use it. For
464464
465465 // Otherwise, we need to fold it into the current instruction, or reload it.
466466 // If we have registers available to hold the value, use them.
467 const TargetRegisterClass *RC = MF->getSSARegMap()->getRegClass(VirtReg);
467 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
468468 unsigned PhysReg = getFreeReg(RC);
469469 int FrameIndex = getStackSpaceFor(VirtReg, RC);
470470
474474 // If we can fold this spill into this instruction, do so now.
475475 SmallVector Ops;
476476 Ops.push_back(OpNum);
477 if (MachineInstr* FMI = RegInfo->foldMemoryOperand(MI, Ops, FrameIndex)) {
477 if (MachineInstr* FMI = MRI->foldMemoryOperand(MI, Ops, FrameIndex)) {
478478 ++NumFolded;
479479 // Since we changed the address of MI, make sure to update live variables
480480 // to know that the new instruction has the properties of the old one.
491491 markVirtRegModified(VirtReg, false); // Note that this reg was just reloaded
492492
493493 DOUT << " Reloading %reg" << VirtReg << " into "
494 << RegInfo->getName(PhysReg) << "\n";
494 << MRI->getName(PhysReg) << "\n";
495495
496496 // Add move instruction(s)
497 RegInfo->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC);
497 MRI->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC);
498498 ++NumLoads; // Update statistics
499499
500 MF->setPhysRegUsed(PhysReg);
500 MF->getRegInfo().setPhysRegUsed(PhysReg);
501501 MI->getOperand(OpNum).setReg(PhysReg); // Assign the input register
502502 return MI;
503503 }
537537 // If this is the first basic block in the machine function, add live-in
538538 // registers as active.
539539 if (&MBB == &*MF->begin()) {
540 for (MachineFunction::livein_iterator I = MF->livein_begin(),
541 E = MF->livein_end(); I != E; ++I) {
540 for (MachineRegisterInfo::livein_iterator I=MF->getRegInfo().livein_begin(),
541 E = MF->getRegInfo().livein_end(); I != E; ++I) {
542542 unsigned Reg = I->first;
543 MF->setPhysRegUsed(Reg);
543 MF->getRegInfo().setPhysRegUsed(Reg);
544544 PhysRegsUsed[Reg] = 0; // It is free and reserved now
545545 AddToPhysRegsUseOrder(Reg);
546 for (const unsigned *AliasSet = RegInfo->getSubRegisters(Reg);
546 for (const unsigned *AliasSet = MRI->getSubRegisters(Reg);
547547 *AliasSet; ++AliasSet) {
548548 if (PhysRegsUsed[*AliasSet] != -2) {
549549 AddToPhysRegsUseOrder(*AliasSet);
550550 PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
551 MF->setPhysRegUsed(*AliasSet);
551 MF->getRegInfo().setPhysRegUsed(*AliasSet);
552552 }
553553 }
554554 }
560560 const TargetInstrDescriptor &TID = TII.get(MI->getOpcode());
561561 DEBUG(DOUT << "\nStarting RegAlloc of: " << *MI;
562562 DOUT << " Regs have values: ";
563 for (unsigned i = 0; i != RegInfo->getNumRegs(); ++i)
563 for (unsigned i = 0; i != MRI->getNumRegs(); ++i)
564564 if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2)
565 DOUT << "[" << RegInfo->getName(i)
565 DOUT << "[" << MRI->getName(i)
566566 << ",%reg" << PhysRegsUsed[i] << "] ";
567567 DOUT << "\n");
568568
624624 }
625625
626626 if (PhysReg) {
627 DOUT << " Last use of " << RegInfo->getName(PhysReg)
627 DOUT << " Last use of " << MRI->getName(PhysReg)
628628 << "[%reg" << VirtReg <<"], removing it from live set\n";
629629 removePhysReg(PhysReg);
630 for (const unsigned *AliasSet = RegInfo->getSubRegisters(PhysReg);
630 for (const unsigned *AliasSet = MRI->getSubRegisters(PhysReg);
631631 *AliasSet; ++AliasSet) {
632632 if (PhysRegsUsed[*AliasSet] != -2) {
633633 DOUT << " Last use of "
634 << RegInfo->getName(*AliasSet)
634 << MRI->getName(*AliasSet)
635635 << "[%reg" << VirtReg <<"], removing it from live set\n";
636636 removePhysReg(*AliasSet);
637637 }
652652 // larger registers). Ignore.
653653 if (isReadModWriteImplicitDef(MI, MO.getReg())) continue;
654654
655 MF->setPhysRegUsed(Reg);
655 MF->getRegInfo().setPhysRegUsed(Reg);
656656 spillPhysReg(MBB, MI, Reg, true); // Spill any existing value in reg
657657 PhysRegsUsed[Reg] = 0; // It is free and reserved now
658658 AddToPhysRegsUseOrder(Reg);
659659
660 for (const unsigned *AliasSet = RegInfo->getSubRegisters(Reg);
660 for (const unsigned *AliasSet = MRI->getSubRegisters(Reg);
661661 *AliasSet; ++AliasSet) {
662662 if (PhysRegsUsed[*AliasSet] != -2) {
663 MF->setPhysRegUsed(*AliasSet);
663 MF->getRegInfo().setPhysRegUsed(*AliasSet);
664664 PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
665665 AddToPhysRegsUseOrder(*AliasSet);
666666 }
678678 AddToPhysRegsUseOrder(Reg);
679679 PhysRegsUsed[Reg] = 0; // It is free and reserved now
680680 }
681 MF->setPhysRegUsed(Reg);
682 for (const unsigned *AliasSet = RegInfo->getSubRegisters(Reg);
681 MF->getRegInfo().setPhysRegUsed(Reg);
682 for (const unsigned *AliasSet = MRI->getSubRegisters(Reg);
683683 *AliasSet; ++AliasSet) {
684684 if (PhysRegsUsed[*AliasSet] != -2) {
685685 AddToPhysRegsUseOrder(*AliasSet);
686686 PhysRegsUsed[*AliasSet] = 0; // It is free and reserved now
687 MF->setPhysRegUsed(*AliasSet);
687 MF->getRegInfo().setPhysRegUsed(*AliasSet);
688688 }
689689 }
690690 }
712712 // If DestVirtReg already has a value, use it.
713713 if (!(DestPhysReg = getVirt2PhysRegMapSlot(DestVirtReg)))
714714 DestPhysReg = getReg(MBB, MI, DestVirtReg);
715 MF->setPhysRegUsed(DestPhysReg);
715 MF->getRegInfo().setPhysRegUsed(DestPhysReg);
716716 markVirtRegModified(DestVirtReg);
717717 MI->getOperand(i).setReg(DestPhysReg); // Assign the output register
718718 }
735735 }
736736
737737 if (PhysReg) {
738 DOUT << " Register " << RegInfo->getName(PhysReg)
738 DOUT << " Register " << MRI->getName(PhysReg)
739739 << " [%reg" << VirtReg
740740 << "] is never used, removing it frame live list\n";
741741 removePhysReg(PhysReg);
742 for (const unsigned *AliasSet = RegInfo->getAliasSet(PhysReg);
742 for (const unsigned *AliasSet = MRI->getAliasSet(PhysReg);
743743 *AliasSet; ++AliasSet) {
744744 if (PhysRegsUsed[*AliasSet] != -2) {
745 DOUT << " Register " << RegInfo->getName(*AliasSet)
745 DOUT << " Register " << MRI->getName(*AliasSet)
746746 << " [%reg" << *AliasSet
747747 << "] is never used, removing it frame live list\n";
748748 removePhysReg(*AliasSet);
763763 MachineBasicBlock::iterator MI = MBB.getFirstTerminator();
764764
765765 // Spill all physical registers holding virtual registers now.
766 for (unsigned i = 0, e = RegInfo->getNumRegs(); i != e; ++i)
766 for (unsigned i = 0, e = MRI->getNumRegs(); i != e; ++i)
767767 if (PhysRegsUsed[i] != -1 && PhysRegsUsed[i] != -2)
768768 if (unsigned VirtReg = PhysRegsUsed[i])
769769 spillVirtReg(MBB, MI, VirtReg, i);
774774 // This checking code is very expensive.
775775 bool AllOk = true;
776776 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
777 e = MF->getSSARegMap()->getLastVirtReg(); i <= e; ++i)
777 e = MF->getRegInfo().getLastVirtReg(); i <= e; ++i)
778778 if (unsigned PR = Virt2PhysRegMap[i]) {
779779 cerr << "Register still mapped: " << i << " -> " << PR << "\n";
780780 AllOk = false;
795795 DOUT << "Machine Function " << "\n";
796796 MF = &Fn;
797797 TM = &Fn.getTarget();
798 RegInfo = TM->getRegisterInfo();
798 MRI = TM->getRegisterInfo();
799799 LV = &getAnalysis();
800800
801 PhysRegsUsed.assign(RegInfo->getNumRegs(), -1);
801 PhysRegsUsed.assign(MRI->getNumRegs(), -1);
802802
803803 // At various places we want to efficiently check to see whether a register
804804 // is allocatable. To handle this, we mark all unallocatable registers as
805805 // being pinned down, permanently.
806806 {
807 BitVector Allocable = RegInfo->getAllocatableSet(Fn);
807 BitVector Allocable = MRI->getAllocatableSet(Fn);
808808 for (unsigned i = 0, e = Allocable.size(); i != e; ++i)
809809 if (!Allocable[i])
810810 PhysRegsUsed[i] = -2; // Mark the reg unallocable.
812812
813813 // initialize the virtual->physical register map to have a 'null'
814814 // mapping for all virtual registers
815 Virt2PhysRegMap.grow(MF->getSSARegMap()->getLastVirtReg());
815 Virt2PhysRegMap.grow(MF->getRegInfo().getLastVirtReg());
816816
817817 // Loop over all of the basic blocks, eliminating virtual register references
818818 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
1717 #include "llvm/CodeGen/Passes.h"
1818 #include "llvm/CodeGen/MachineFunctionPass.h"
1919 #include "llvm/CodeGen/MachineInstr.h"
20 #include "llvm/CodeGen/SSARegMap.h"
2120 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
2222 #include "llvm/CodeGen/RegAllocRegistry.h"
2323 #include "llvm/Target/TargetInstrInfo.h"
2424 #include "llvm/Target/TargetMachine.h"
4343 private:
4444 MachineFunction *MF;
4545 const TargetMachine *TM;
46 const MRegisterInfo *RegInfo;
46 const MRegisterInfo *MRI;
4747
4848 // StackSlotForVirtReg - Maps SSA Regs => frame index on the stack where
4949 // these values are spilled
118118 }
119119
120120 unsigned RegAllocSimple::getFreeReg(unsigned virtualReg) {
121 const TargetRegisterClass* RC = MF->getSSARegMap()->getRegClass(virtualReg);
121 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtualReg);
122122 TargetRegisterClass::iterator RI = RC->allocation_order_begin(*MF);
123123 TargetRegisterClass::iterator RE = RC->allocation_order_end(*MF);
124124
128128 unsigned PhysReg = *(RI+regIdx);
129129
130130 if (!RegsUsed[PhysReg]) {
131 MF->setPhysRegUsed(PhysReg);
131 MF->getRegInfo().setPhysRegUsed(PhysReg);
132132 return PhysReg;
133133 }
134134 }
137137 unsigned RegAllocSimple::reloadVirtReg(MachineBasicBlock &MBB,
138138 MachineBasicBlock::iterator I,
139139 unsigned VirtReg) {
140 const TargetRegisterClass* RC = MF->getSSARegMap()->getRegClass(VirtReg);
140 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(VirtReg);
141141 int FrameIdx = getStackSpaceFor(VirtReg, RC);
142142 unsigned PhysReg = getFreeReg(VirtReg);
143143
144144 // Add move instruction(s)
145145 ++NumLoads;
146 RegInfo->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx, RC);
146 MRI->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx, RC);
147147 return PhysReg;
148148 }
149149
150150 void RegAllocSimple::spillVirtReg(MachineBasicBlock &MBB,
151151 MachineBasicBlock::iterator I,
152152 unsigned VirtReg, unsigned PhysReg) {
153 const TargetRegisterClass* RC = MF->getSSARegMap()->getRegClass(VirtReg);
153 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(VirtReg);
154154 int FrameIdx = getStackSpaceFor(VirtReg, RC);
155155
156156 // Add move instruction(s)
157157 ++NumStores;
158 RegInfo->storeRegToStackSlot(MBB, I, PhysReg, true, FrameIdx, RC);
158 MRI->storeRegToStackSlot(MBB, I, PhysReg, true, FrameIdx, RC);
159159 }
160160
161161
165165 // Made to combat the incorrect allocation of r2 = add r1, r1
166166 std::map Virt2PhysRegMap;
167167
168 RegsUsed.resize(RegInfo->getNumRegs());
168 RegsUsed.resize(MRI->getNumRegs());
169169
170170 // This is a preliminary pass that will invalidate any registers that are
171171 // used by the instruction (including implicit uses).
180180 if (Desc.ImplicitDefs) {
181181 for (Regs = Desc.ImplicitDefs; *Regs; ++Regs) {
182182 RegsUsed[*Regs] = true;
183 MF->setPhysRegUsed(*Regs);
183 MF->getRegInfo().setPhysRegUsed(*Regs);
184184 }
185185 }
186186
236236 DOUT << "Machine Function\n";
237237 MF = &Fn;
238238 TM = &MF->getTarget();
239 RegInfo = TM->getRegisterInfo();
239 MRI = TM->getRegisterInfo();
240240
241241 // Loop over all of the basic blocks, eliminating virtual register references
242242 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
1414 #include "llvm/CodeGen/MachineFunction.h"
1515 #include "llvm/CodeGen/MachineFrameInfo.h"
1616 #include "llvm/CodeGen/MachineJumpTableInfo.h"
17 #include "llvm/CodeGen/MachineModuleInfo.h"
1718 #include "llvm/Target/TargetFrameInfo.h"
1819 #include "llvm/Target/TargetLowering.h"
1920 #include "llvm/Target/TargetData.h"
1717 #include "llvm/CodeGen/ScheduleDAG.h"
1818 #include "llvm/CodeGen/MachineConstantPool.h"
1919 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/SSARegMap.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
2121 #include "llvm/Target/TargetData.h"
2222 #include "llvm/Target/TargetMachine.h"
2323 #include "llvm/Target/TargetInstrInfo.h"
2626 #include "llvm/Support/MathExtras.h"
2727 using namespace llvm;
2828
29 ScheduleDAG::ScheduleDAG(SelectionDAG &dag, MachineBasicBlock *bb,
30 const TargetMachine &tm)
31 : DAG(dag), BB(bb), TM(tm), RegInfo(BB->getParent()->getRegInfo()) {
32 TII = TM.getInstrInfo();
33 MRI = TM.getRegisterInfo();
34 ConstPool = BB->getParent()->getConstantPool();
35 }
2936
3037 /// CheckForPhysRegDependency - Check if the dependency between def and use of
3138 /// a specified operand is a physical register dependency. If so, returns the
340347 const TargetRegisterClass *TRC = 0;
341348 // Figure out the register class to create for the destreg.
342349 if (VRBase)
343 TRC = RegMap->getRegClass(VRBase);
350 TRC = RegInfo.getRegClass(VRBase);
344351 else
345352 TRC = MRI->getPhysicalRegisterRegClass(Node->getValueType(ResNo), SrcReg);
346353
350357 VRBase = SrcReg;
351358 } else {
352359 // Create the reg, emit the copy.
353 VRBase = RegMap->createVirtualRegister(TRC);
360 VRBase = RegInfo.createVirtualRegister(TRC);
354361 MRI->copyRegToReg(*BB, BB->end(), VRBase, SrcReg, TRC, TRC);
355362 }
356363
389396 if (VRBase == 0) {
390397 const TargetRegisterClass *RC = getInstrOperandRegClass(MRI, TII, &II, i);
391398 assert(RC && "Isn't a register operand!");
392 VRBase = RegMap->createVirtualRegister(RC);
399 VRBase = RegInfo.createVirtualRegister(RC);
393400 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
394401 }
395402
436443 const TargetRegisterClass *RC =
437444 getInstrOperandRegClass(MRI, TII, II, IIOpNum);
438445 assert(RC && "Don't have operand info for this instruction!");
439 const TargetRegisterClass *VRC = RegMap->getRegClass(VReg);
446 const TargetRegisterClass *VRC = RegInfo.getRegClass(VReg);
440447 if (VRC != RC) {
441448 cerr << "Register class of operand and regclass of use don't agree!\n";
442449 #ifndef NDEBUG
500507 const TargetRegisterClass *RC =
501508 getInstrOperandRegClass(MRI, TII, II, IIOpNum);
502509 assert(RC && "Don't have operand info for this instruction!");
503 assert(RegMap->getRegClass(VReg) == RC &&
510 assert(RegInfo.getRegClass(VReg) == RC &&
504511 "Register class of operand and regclass of use don't agree!");
505512 }
506513 }
564571
565572 // Figure out the register class to create for the destreg.
566573 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
567 const TargetRegisterClass *TRC = RegMap->getRegClass(VReg);
574 const TargetRegisterClass *TRC = RegInfo.getRegClass(VReg);
568575 const TargetRegisterClass *SRC = getSubRegisterRegClass(TRC, SubIdx);
569576
570577 if (VRBase) {
571578 // Grab the destination register
572579 const TargetRegisterClass *DRC = 0;
573 DRC = RegMap->getRegClass(VRBase);
580 DRC = RegInfo.getRegClass(VRBase);
574581 assert(SRC == DRC &&
575582 "Source subregister and destination must have the same class");
576583 } else {
577584 // Create the reg
578 VRBase = RegMap->createVirtualRegister(SRC);
585 VRBase = RegInfo.createVirtualRegister(SRC);
579586 }
580587
581588 // Add def, source, and subreg index
625632 // Figure out the register class to create for the destreg.
626633 const TargetRegisterClass *TRC = 0;
627634 if (VRBase) {
628 TRC = RegMap->getRegClass(VRBase);
635 TRC = RegInfo.getRegClass(VRBase);
629636 } else {
630 TRC = getSuperregRegisterClass(RegMap->getRegClass(SubReg),
631 SubIdx,
637 TRC = getSuperregRegisterClass(RegInfo.getRegClass(SubReg), SubIdx,
632638 Node->getValueType(0));
633639 assert(TRC && "Couldn't determine register class for insert_subreg");
634 VRBase = RegMap->createVirtualRegister(TRC); // Create the reg
640 VRBase = RegInfo.createVirtualRegister(TRC); // Create the reg
635641 }
636642
637643 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
739745 const TargetRegisterClass *TRC = 0;
740746 // Get the target register class
741747 if (MRegisterInfo::isVirtualRegister(InReg))
742 TRC = RegMap->getRegClass(InReg);
748 TRC = RegInfo.getRegClass(InReg);
743749 else
744750 TRC =
745751 MRI->getPhysicalRegisterRegClass(Node->getOperand(2).getValueType(),
846852 } else {
847853 // Copy from physical register.
848854 assert(I->Reg && "Unknown physical register!");
849 unsigned VRBase = RegMap->createVirtualRegister(SU->CopyDstRC);
855 unsigned VRBase = RegInfo.createVirtualRegister(SU->CopyDstRC);
850856 bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase));
851857 assert(isNew && "Node emitted out of order - early");
852858 MRI->copyRegToReg(*BB, BB->end(), VRBase, I->Reg,
863869 // block before emitting the code for the block.
864870 MachineFunction &MF = DAG.getMachineFunction();
865871 if (&MF.front() == BB) {
866 for (MachineFunction::livein_iterator LI = MF.livein_begin(),
867 E = MF.livein_end(); LI != E; ++LI)
872 for (MachineRegisterInfo::livein_iterator LI = RegInfo.livein_begin(),
873 E = RegInfo.livein_end(); LI != E; ++LI)
868874 if (LI->second) {
869 const TargetRegisterClass *RC = RegMap->getRegClass(LI->second);
875 const TargetRegisterClass *RC = RegInfo.getRegClass(LI->second);
870876 MRI->copyRegToReg(*MF.begin(), MF.begin()->end(), LI->second,
871877 LI->first, RC, RC);
872878 }
905911 /// Run - perform scheduling.
906912 ///
907913 MachineBasicBlock *ScheduleDAG::Run() {
908 TII = TM.getInstrInfo();
909 MRI = TM.getRegisterInfo();
910 RegMap = BB->getParent()->getSSARegMap();
911 ConstPool = BB->getParent()->getConstantPool();
912
913914 Schedule();
914915 return BB;
915916 }
2121 #include "llvm/CodeGen/ScheduleDAG.h"
2222 #include "llvm/CodeGen/SchedulerRegistry.h"
2323 #include "llvm/CodeGen/SelectionDAGISel.h"
24 #include "llvm/CodeGen/SSARegMap.h"
2524 #include "llvm/Target/MRegisterInfo.h"
2625 #include "llvm/Target/TargetData.h"
2726 #include "llvm/Target/TargetMachine.h"
1717 #define DEBUG_TYPE "pre-RA-sched"
1818 #include "llvm/CodeGen/ScheduleDAG.h"
1919 #include "llvm/CodeGen/SchedulerRegistry.h"
20 #include "llvm/CodeGen/SSARegMap.h"
2120 #include "llvm/Target/MRegisterInfo.h"
2221 #include "llvm/Target/TargetData.h"
2322 #include "llvm/Target/TargetMachine.h"
2525 #include "llvm/Intrinsics.h"
2626 #include "llvm/IntrinsicInst.h"
2727 #include "llvm/ParameterAttributes.h"
28 #include "llvm/CodeGen/MachineModuleInfo.h"
2928 #include "llvm/CodeGen/MachineFunction.h"
3029 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
3131 #include "llvm/CodeGen/MachineJumpTableInfo.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineModuleInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
3334 #include "llvm/CodeGen/SchedulerRegistry.h"
3435 #include "llvm/CodeGen/SelectionDAG.h"
35 #include "llvm/CodeGen/SSARegMap.h"
3636 #include "llvm/Target/MRegisterInfo.h"
3737 #include "llvm/Target/TargetData.h"
3838 #include "llvm/Target/TargetFrameInfo.h"
165165 TargetLowering &TLI;
166166 Function &Fn;
167167 MachineFunction &MF;
168 SSARegMap *RegMap;
168 MachineRegisterInfo &RegInfo;
169169
170170 FunctionLoweringInfo(TargetLowering &TLI, Function &Fn,MachineFunction &MF);
171171
188188 #endif
189189
190190 unsigned MakeReg(MVT::ValueType VT) {
191 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
191 return RegInfo.createVirtualRegister(TLI.getRegClassFor(VT));
192192 }
193193
194194 /// isExportedInst - Return true if the specified value is an instruction
243243
244244 FunctionLoweringInfo::FunctionLoweringInfo(TargetLowering &tli,
245245 Function &fn, MachineFunction &mf)
246 : TLI(tli), Fn(fn), MF(mf), RegMap(MF.getSSARegMap()) {
246 : TLI(tli), Fn(fn), MF(mf), RegInfo(MF.getRegInfo()) {
247247
248248 // Create a vreg for each argument register that is not dead and is used
249249 // outside of the entry block for the function.
33473347 ValueVT = RegVT;
33483348
33493349 // Create the appropriate number of virtual registers.
3350 SSARegMap *RegMap = MF.getSSARegMap();
3350 MachineRegisterInfo &RegInfo = MF.getRegInfo();
33513351 for (; NumRegs; --NumRegs)
3352 Regs.push_back(RegMap->createVirtualRegister(PhysReg.second));
3352 Regs.push_back(RegInfo.createVirtualRegister(PhysReg.second));
33533353
33543354 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);
33553355 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs);
43624362 //===----------------------------------------------------------------------===//
43634363
43644364 unsigned SelectionDAGISel::MakeReg(MVT::ValueType VT) {
4365 return RegMap->createVirtualRegister(TLI.getRegClassFor(VT));
4365 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
43664366 }
43674367
43684368 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
43774377 AA = &getAnalysis();
43784378
43794379 MachineFunction &MF = MachineFunction::construct(&Fn, TLI.getTargetMachine());
4380 RegMap = MF.getSSARegMap();
4380 RegInfo = &MF.getRegInfo();
43814381 DOUT << "\n\n\n=== " << Fn.getName() << "\n";
43824382
43834383 FunctionLoweringInfo FuncInfo(TLI, Fn, MF);
43944394 // Add function live-ins to entry block live-in set.
43954395 BasicBlock *EntryBB = &Fn.getEntryBlock();
43964396 BB = FuncInfo.MBBMap[EntryBB];
4397 if (!MF.livein_empty())
4398 for (MachineFunction::livein_iterator I = MF.livein_begin(),
4399 E = MF.livein_end(); I != E; ++I)
4397 if (!RegInfo->livein_empty())
4398 for (MachineRegisterInfo::livein_iterator I = RegInfo->livein_begin(),
4399 E = RegInfo->livein_end(); I != E; ++I)
44004400 BB->addLiveIn(I->first);
44014401
44024402 #ifndef NDEBUG
2020 #include "llvm/CodeGen/MachineFrameInfo.h"
2121 #include "llvm/CodeGen/MachineInstr.h"
2222 #include "llvm/CodeGen/MachineLoopInfo.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
2324 #include "llvm/CodeGen/Passes.h"
24 #include "llvm/CodeGen/SSARegMap.h"
2525 #include "llvm/CodeGen/RegisterCoalescer.h"
26 #include "llvm/Target/MRegisterInfo.h"
2726 #include "llvm/Target/TargetInstrInfo.h"
2827 #include "llvm/Target/TargetMachine.h"
2928 #include "llvm/Support/CommandLine.h"
282281 // If this is a extract_subreg where dst is a physical register, e.g.
283282 // cl = EXTRACT_SUBREG reg1024, 1
284283 // then create and update the actual physical register allocated to RHS.
285 const TargetRegisterClass *RC=mf_->getSSARegMap()->getRegClass(repSrcReg);
284 const TargetRegisterClass *RC=mf_->getRegInfo().getRegClass(repSrcReg);
286285 for (const unsigned *SRs = mri_->getSuperRegisters(repDstReg);
287286 unsigned SR = *SRs; ++SRs) {
288287 if (repDstReg == mri_->getSubReg(SR, SubIdx) &&
312311 } else {
313312 unsigned SrcSize= li_->getInterval(repSrcReg).getSize() / InstrSlots::NUM;
314313 unsigned DstSize= li_->getInterval(repDstReg).getSize() / InstrSlots::NUM;
315 const TargetRegisterClass *RC=mf_->getSSARegMap()->getRegClass(repDstReg);
314 const TargetRegisterClass *RC=mf_->getRegInfo().getRegClass(repDstReg);
316315 unsigned Threshold = allocatableRCRegs_[RC].count();
317316 // Be conservative. If both sides are virtual registers, do not coalesce
318317 // if this will cause a high use density interval to target a smaller set
394393 LiveInterval &JoinVInt = SrcIsPhys ? DstInt : SrcInt;
395394 unsigned JoinVReg = SrcIsPhys ? repDstReg : repSrcReg;
396395 unsigned JoinPReg = SrcIsPhys ? repSrcReg : repDstReg;
397 const TargetRegisterClass *RC = mf_->getSSARegMap()->getRegClass(JoinVReg);
396 const TargetRegisterClass *RC = mf_->getRegInfo().getRegClass(JoinVReg);
398397 unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
399398 if (TheCopy.isBackEdge)
400399 Threshold *= 2; // Favors back edge copies.
12381237 if (MRegisterInfo::isPhysicalRegister(RegA)) {
12391238 assert(MRegisterInfo::isVirtualRegister(RegB) &&
12401239 "Shouldn't consider two physregs!");
1241 return !mf_->getSSARegMap()->getRegClass(RegB)->contains(RegA);
1240 return !mf_->getRegInfo().getRegClass(RegB)->contains(RegA);
12421241 }
12431242
12441243 // Compare against the regclass for the second reg.
1245 const TargetRegisterClass *RegClass = mf_->getSSARegMap()->getRegClass(RegA);
1244 const TargetRegisterClass *RegClass = mf_->getRegInfo().getRegClass(RegA);
12461245 if (MRegisterInfo::isVirtualRegister(RegB))
1247 return RegClass != mf_->getSSARegMap()->getRegClass(RegB);
1246 return RegClass != mf_->getRegInfo().getRegClass(RegB);
12481247 else
12491248 return !RegClass->contains(RegB);
12501249 }
12531252 /// cycles Start and End. It also returns the use operand by reference. It
12541253 /// returns NULL if there are no uses.
12551254 MachineInstr *
1256 SimpleRegisterCoalescing::lastRegisterUse(unsigned Start, unsigned End, unsigned Reg,
1257 MachineOperand *&MOU) {
1255 SimpleRegisterCoalescing::lastRegisterUse(unsigned Start, unsigned End,
1256 unsigned Reg, MachineOperand *&MOU) {
12581257 int e = (End-1) / InstrSlots::NUM * InstrSlots::NUM;
12591258 int s = Start;
12601259 while (e >= s) {
13891388 E = mri_->regclass_end(); I != E; ++I)
13901389 allocatableRCRegs_.insert(std::make_pair(*I,mri_->getAllocatableSet(fn, *I)));
13911390
1392 SSARegMap *RegMap = mf_->getSSARegMap();
1393 r2rMap_.grow(RegMap->getLastVirtReg());
1394 r2rRevMap_.grow(RegMap->getLastVirtReg());
1391 MachineRegisterInfo &RegInfo = mf_->getRegInfo();
1392 r2rMap_.grow(RegInfo.getLastVirtReg());
1393 r2rRevMap_.grow(RegInfo.getLastVirtReg());
13951394
13961395 // Join (coalesce) intervals if requested.
13971396 IndexedMap RegSubIdxMap;
14121411
14131412 // Transfer sub-registers info to SSARegMap now that coalescing information
14141413 // is complete.
1415 RegSubIdxMap.grow(mf_->getSSARegMap()->getLastVirtReg()+1);
1414 RegSubIdxMap.grow(RegInfo.getLastVirtReg()+1);
14161415 while (!SubRegIdxes.empty()) {
14171416 std::pair RI = SubRegIdxes.back();
14181417 SubRegIdxes.pop_back();
2424 #include "llvm/CodeGen/MachineDominators.h"
2525 #include "llvm/CodeGen/MachineFunctionPass.h"
2626 #include "llvm/CodeGen/MachineInstr.h"
27 #include "llvm/CodeGen/SSARegMap.h"
2827 #include "llvm/Target/TargetInstrInfo.h"
2928 #include "llvm/Target/TargetMachine.h"
3029 #include "llvm/ADT/DepthFirstIterator.h"
3232 #include "llvm/CodeGen/LiveVariables.h"
3333 #include "llvm/CodeGen/MachineFunctionPass.h"
3434 #include "llvm/CodeGen/MachineInstr.h"
35 #include "llvm/CodeGen/SSARegMap.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
3636 #include "llvm/Target/MRegisterInfo.h"
3737 #include "llvm/Target/TargetInstrInfo.h"
3838 #include "llvm/Target/TargetMachine.h"
191191 }
192192
193193 InstructionRearranged:
194 const TargetRegisterClass* rc = MF.getSSARegMap()->getRegClass(regA);
194 const TargetRegisterClass* rc = MF.getRegInfo().getRegClass(regA);
195195 MRI.copyRegToReg(*mbbi, mi, regA, regB, rc, rc);
196196
197197 MachineBasicBlock::iterator prevMi = prior(mi);
2020 #include "llvm/Function.h"
2121 #include "llvm/CodeGen/MachineFrameInfo.h"
2222 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/SSARegMap.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
2424 #include "llvm/Target/TargetMachine.h"
2525 #include "llvm/Target/TargetInstrInfo.h"
2626 #include "llvm/Support/CommandLine.h"
6868 }
6969
7070 void VirtRegMap::grow() {
71 unsigned LastVirtReg = MF.getSSARegMap()->getLastVirtReg();
71 unsigned LastVirtReg = MF.getRegInfo().getLastVirtReg();
7272 Virt2PhysMap.grow(LastVirtReg);
7373 Virt2StackSlotMap.grow(LastVirtReg);
7474 Virt2ReMatIdMap.grow(LastVirtReg);
8181 assert(MRegisterInfo::isVirtualRegister(virtReg));
8282 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
8383 "attempt to assign stack slot to already spilled register");
84 const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(virtReg);
84 const TargetRegisterClass* RC = MF.getRegInfo().getRegClass(virtReg);
8585 int frameIndex = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
8686 RC->getAlignment());
8787 Virt2StackSlotMap[virtReg] = frameIndex;
138138
139139 OS << "********** REGISTER MAP **********\n";
140140 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
141 e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i) {
141 e = MF.getRegInfo().getLastVirtReg(); i <= e; ++i) {
142142 if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG)
143143 OS << "[reg" << i << " -> " << MRI->getName(Virt2PhysMap[i]) << "]\n";
144144
145145 }
146146
147147 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
148 e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i)
148 e = MF.getRegInfo().getLastVirtReg(); i <= e; ++i)
149149 if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT)
150150 OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i] << "]\n";
151151 OS << '\n';
196196 if (!VRM.isAssignedReg(VirtReg)) {
197197 int StackSlot = VRM.getStackSlot(VirtReg);
198198 const TargetRegisterClass* RC =
199 MF.getSSARegMap()->getRegClass(VirtReg);
199 MF.getRegInfo().getRegClass(VirtReg);
200200
201201 if (MO.isUse() &&
202202 std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg)
213213 ++NumStores;
214214 }
215215 }
216 MF.setPhysRegUsed(PhysReg);
216 MF.getRegInfo().setPhysRegUsed(PhysReg);
217217 MI.getOperand(i).setReg(PhysReg);
218218 } else {
219 MF.setPhysRegUsed(MO.getReg());
219 MF.getRegInfo().setPhysRegUsed(MO.getReg());
220220 }
221221 }
222222
239239 /// blocks that have low register pressure (the vreg may be spilled due to
240240 /// register pressure in other blocks).
241241 class VISIBILITY_HIDDEN LocalSpiller : public Spiller {
242 SSARegMap *RegMap;
242 MachineRegisterInfo *RegInfo;
243243 const MRegisterInfo *MRI;
244244 const TargetInstrInfo *TII;
245245 public:
246246 bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
247 RegMap = MF.getSSARegMap();
247 RegInfo = &MF.getRegInfo();
248248 MRI = MF.getTarget().getRegisterInfo();
249249 TII = MF.getTarget().getInstrInfo();
250250 DOUT << "\n**** Local spiller rewriting function '"
251251 << MF.getFunction()->getName() << "':\n";
252 DOUT << "**** Machine Instrs (NOTE! Does not include spills and reloads!) ****\n";
252 DOUT << "**** Machine Instrs (NOTE! Does not include spills and reloads!)"
253 " ****\n";
253254 DEBUG(MF.dump());
254255
255256 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
671672 // to undo a previous reuse.
672673 MachineBasicBlock *MBB = MI->getParent();
673674 const TargetRegisterClass *AliasRC =
674 MBB->getParent()->getSSARegMap()->getRegClass(Op.VirtReg);
675 MBB->getParent()->getRegInfo().getRegClass(Op.VirtReg);
675676
676677 // Copy Op out of the vector and remove it, we're going to insert an
677678 // explicit load for it.
970971 if (!VRM.getPreSplitReg(VirtReg))
971972 continue; // Split interval spilled again.
972973 unsigned Phys = VRM.getPhys(VirtReg);
973 MF.setPhysRegUsed(Phys);
974 RegInfo->setPhysRegUsed(Phys);
974975 if (VRM.isReMaterialized(VirtReg)) {
975976 MRI->reMaterialize(MBB, &MI, Phys,
976977 VRM.getReMaterializedMI(VirtReg));
977978 ++NumReMats;
978979 } else {
979 const TargetRegisterClass* RC = RegMap->getRegClass(VirtReg);
980 MRI->loadRegFromStackSlot(MBB, &MI, Phys, VRM.getStackSlot(VirtReg), RC);
980 const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
981 MRI->loadRegFromStackSlot(MBB, &MI, Phys, VRM.getStackSlot(VirtReg),
982 RC);
981983 ++NumLoads;
982984 }
983985 // This invalidates Phys.
996998 bool isKill = SpillRegs[i].second;
997999 if (!VRM.getPreSplitReg(VirtReg))
9981000 continue; // Split interval spilled again.
999 const TargetRegisterClass *RC = RegMap->getRegClass(VirtReg);
1001 const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg);
10001002 unsigned Phys = VRM.getPhys(VirtReg);
10011003 int StackSlot = VRM.getStackSlot(VirtReg);
10021004 MRI->storeRegToStackSlot(MBB, next(MII), Phys, isKill, StackSlot, RC);
10201022 if (MRegisterInfo::isPhysicalRegister(VirtReg)) {
10211023 // Ignore physregs for spilling, but remember that it is used by this
10221024 // function.
1023 MF.setPhysRegUsed(VirtReg);
1025 RegInfo->setPhysRegUsed(VirtReg);
10241026 continue;
10251027 }
10261028
10311033 if (VRM.isAssignedReg(VirtReg)) {
10321034 // This virtual register was assigned a physreg!
10331035 unsigned Phys = VRM.getPhys(VirtReg);
1034 MF.setPhysRegUsed(Phys);
1036 RegInfo->setPhysRegUsed(Phys);
10351037 if (MO.isDef())
10361038 ReusedOperands.markClobbered(Phys);
10371039 unsigned RReg = SubIdx ? MRI->getSubReg(Phys, SubIdx) : Phys;
10631065 // the right register file.
10641066 if (PhysReg &&
10651067 (SubIdx || MI.getOpcode() == TargetInstrInfo::EXTRACT_SUBREG)) {
1066 const TargetRegisterClass* RC = RegMap->getRegClass(VirtReg);
1068 const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
10671069 if (!RC->contains(PhysReg))
10681070 PhysReg = 0;
10691071 }
11761178 continue;
11771179 }
11781180
1179 const TargetRegisterClass* RC = RegMap->getRegClass(VirtReg);
1180 MF.setPhysRegUsed(DesignatedReg);
1181 const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
1182 RegInfo->setPhysRegUsed(DesignatedReg);
11811183 ReusedOperands.markClobbered(DesignatedReg);
11821184 MRI->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC, RC);
11831185
12081210 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI,
12091211 Spills, MaybeDeadStores, RegKills, KillOps, VRM);
12101212
1211 MF.setPhysRegUsed(PhysReg);
1213 RegInfo->setPhysRegUsed(PhysReg);
12121214 ReusedOperands.markClobbered(PhysReg);
12131215 if (DoReMat) {
12141216 MRI->reMaterialize(MBB, &MI, PhysReg, VRM.getReMaterializedMI(VirtReg));
12151217 ++NumReMats;
12161218 } else {
1217 const TargetRegisterClass* RC = RegMap->getRegClass(VirtReg);
1219 const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
12181220 MRI->loadRegFromStackSlot(MBB, &MI, PhysReg, SSorRMId, RC);
12191221 ++NumLoads;
12201222 }
12641266 if (unsigned InReg = Spills.getSpillSlotOrReMatPhysReg(SS)) {
12651267 DOUT << "Promoted Load To Copy: " << MI;
12661268 if (DestReg != InReg) {
1267 const TargetRegisterClass *RC = RegMap->getRegClass(VirtReg);
1269 const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg);
12681270 MRI->copyRegToReg(MBB, &MI, DestReg, InReg, RC, RC);
12691271 // Revisit the copy so we make sure to notice the effects of the
12701272 // operation on the destreg (either needing to RA it if it's
13091311 unsigned PhysReg = Spills.getSpillSlotOrReMatPhysReg(SS);
13101312 SmallVector NewMIs;
13111313 // We can reuse this physreg as long as we are allowed to clobber
1312 // the value and there isn't an earlier def that has already clobbered the
1313 // physreg.
1314 // the value and there isn't an earlier def that has already clobbered
1315 // the physreg.
13141316 if (PhysReg &&
13151317 !TII->isStoreToStackSlot(&MI, SS) && // Not profitable!
13161318 DeadStore->findRegisterUseOperandIdx(PhysReg, true) != -1 &&
14241426
14251427 // The only vregs left are stack slot definitions.
14261428 int StackSlot = VRM.getStackSlot(VirtReg);
1427 const TargetRegisterClass *RC = RegMap->getRegClass(VirtReg);
1429 const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg);
14281430
14291431 // If this def is part of a two-address operand, make sure to execute
14301432 // the store from the correct physical register.
14481450 }
14491451 }
14501452
1451 MF.setPhysRegUsed(PhysReg);
1453 RegInfo->setPhysRegUsed(PhysReg);
14521454 unsigned RReg = SubIdx ? MRI->getSubReg(PhysReg, SubIdx) : PhysReg;
14531455 ReusedOperands.markClobbered(RReg);
14541456 MI.getOperand(i).setReg(RReg);
2424 #include "llvm/CodeGen/MachineInstrBuilder.h"
2525 #include "llvm/CodeGen/SelectionDAG.h"
2626 #include "llvm/CodeGen/SelectionDAGISel.h"
27 #include "llvm/CodeGen/SSARegMap.h"
2827 #include "llvm/Target/TargetLowering.h"
2928 #include "llvm/Target/TargetOptions.h"
3029 #include "llvm/Support/Debug.h"
2323 #include "llvm/Constants.h"
2424 #include "llvm/Instruction.h"
2525 #include "llvm/Intrinsics.h"
26 #include "llvm/GlobalValue.h"
2627 #include "llvm/CodeGen/MachineBasicBlock.h"
2728 #include "llvm/CodeGen/MachineFrameInfo.h"
2829 #include "llvm/CodeGen/MachineFunction.h"
2930 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineRegisterInfo.h"
3032 #include "llvm/CodeGen/SelectionDAG.h"
31 #include "llvm/CodeGen/SSARegMap.h"
3233 #include "llvm/Target/TargetOptions.h"
3334 #include "llvm/ADT/VectorExtras.h"
3435 #include "llvm/Support/MathExtras.h"
684685 Op.getValue(1), Sign);
685686 }
686687 Copy = DAG.getCopyToReg(Chain, ARM::R0, Op, SDOperand());
687 if (DAG.getMachineFunction().liveout_empty())
688 DAG.getMachineFunction().addLiveOut(ARM::R0);
688 if (DAG.getMachineFunction().getRegInfo().liveout_empty())
689 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R0);
689690 break;
690691 case 5:
691692 Copy = DAG.getCopyToReg(Chain, ARM::R1, Op.getOperand(3), SDOperand());
692693 Copy = DAG.getCopyToReg(Copy, ARM::R0, Op.getOperand(1), Copy.getValue(1));
693694 // If we haven't noted the R0+R1 are live out, do so now.
694 if (DAG.getMachineFunction().liveout_empty()) {
695 DAG.getMachineFunction().addLiveOut(ARM::R0);
696 DAG.getMachineFunction().addLiveOut(ARM::R1);
695 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
696 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R0);
697 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R1);
697698 }
698699 break;
699700 }
916917 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
917918 SDOperand Root = Op.getOperand(0);
918919 std::vector ArgValues;
919 SSARegMap *RegMap = MF.getSSARegMap();
920 MachineRegisterInfo &RegInfo = MF.getRegInfo();
920921
921922 static const unsigned GPRArgRegs[] = {
922923 ARM::R0, ARM::R1, ARM::R2, ARM::R3
934935
935936 SDOperand ArgValue;
936937 if (ObjGPRs == 1) {
937 unsigned VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass);
938 MF.addLiveIn(GPRArgRegs[NumGPRs], VReg);
938 unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
939 RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg);
939940 vRegs[NumGPRs] = VReg;
940941 ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32);
941942 if (ObjectVT == MVT::f32)
942943 ArgValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, ArgValue);
943944 } else if (ObjGPRs == 2) {
944 unsigned VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass);
945 MF.addLiveIn(GPRArgRegs[NumGPRs], VReg);
945 unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
946 RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg);
946947 vRegs[NumGPRs] = VReg;
947948 ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32);
948949
949 VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass);
950 MF.addLiveIn(GPRArgRegs[NumGPRs+1], VReg);
950 VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
951 RegInfo.addLiveIn(GPRArgRegs[NumGPRs+1], VReg);
951952 vRegs[NumGPRs+1] = VReg;
952953 SDOperand ArgValue2 = DAG.getCopyFromReg(Root, VReg, MVT::i32);
953954
10011002 };
10021003
10031004 MachineFunction &MF = DAG.getMachineFunction();
1004 SSARegMap *RegMap = MF.getSSARegMap();
1005 MachineRegisterInfo &RegInfo = MF.getRegInfo();
10051006 MachineFrameInfo *MFI = MF.getFrameInfo();
10061007 ARMFunctionInfo *AFI = MF.getInfo();
10071008 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
10181019
10191020 SmallVector MemOps;
10201021 for (; NumGPRs < 4; ++NumGPRs) {
1021 unsigned VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass);
1022 MF.addLiveIn(GPRArgRegs[NumGPRs], VReg);
1022 unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
1023 RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg);
10231024 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i32);
10241025 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
10251026 MemOps.push_back(Store);
2323 #include "llvm/CodeGen/MachineFunction.h"
2424 #include "llvm/CodeGen/MachineInstrBuilder.h"
2525 #include "llvm/CodeGen/MachineLocation.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
2627 #include "llvm/CodeGen/RegisterScavenging.h"
2728 #include "llvm/Target/TargetFrameInfo.h"
2829 #include "llvm/Target/TargetMachine.h"
12051206 for (unsigned i = 0; CSRegs[i]; ++i) {
12061207 unsigned Reg = CSRegs[i];
12071208 bool Spilled = false;
1208 if (MF.isPhysRegUsed(Reg)) {
1209 if (MF.getRegInfo().isPhysRegUsed(Reg)) {
12091210 AFI->setCSRegisterIsSpilled(Reg);
12101211 Spilled = true;
12111212 CanEliminateFrame = false;
12121213 } else {
12131214 // Check alias registers too.
12141215 for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) {
1215 if (MF.isPhysRegUsed(*Aliases)) {
1216 if (MF.getRegInfo().isPhysRegUsed(*Aliases)) {
12161217 Spilled = true;
12171218 CanEliminateFrame = false;
12181219 }
12851286 // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
12861287 // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
12871288 if (!LRSpilled && CS1Spilled) {
1288 MF.setPhysRegUsed(ARM::LR);
1289 MF.getRegInfo().setPhysRegUsed(ARM::LR);
12891290 AFI->setCSRegisterIsSpilled(ARM::LR);
12901291 NumGPRSpills++;
12911292 UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
12971298 // Darwin ABI requires FP to point to the stack slot that contains the
12981299 // previous FP.
12991300 if (STI.isTargetDarwin() || hasFP(MF)) {
1300 MF.setPhysRegUsed(FramePtr);
1301 MF.getRegInfo().setPhysRegUsed(FramePtr);
13011302 NumGPRSpills++;
13021303 }
13031304
13111312 unsigned Reg = UnspilledCS1GPRs[i];
13121313 // Don't spiil high register if the function is thumb
13131314 if (!AFI->isThumbFunction() || isLowRegister(Reg) || Reg == ARM::LR) {
1314 MF.setPhysRegUsed(Reg);
1315 MF.getRegInfo().setPhysRegUsed(Reg);
13151316 AFI->setCSRegisterIsSpilled(Reg);
13161317 if (!isReservedReg(MF, Reg))
13171318 ExtraCSSpill = true;
13211322 } else if (!UnspilledCS2GPRs.empty() &&
13221323 !AFI->isThumbFunction()) {
13231324 unsigned Reg = UnspilledCS2GPRs.front();
1324 MF.setPhysRegUsed(Reg);
1325 MF.getRegInfo().setPhysRegUsed(Reg);
13251326 AFI->setCSRegisterIsSpilled(Reg);
13261327 if (!isReservedReg(MF, Reg))
13271328 ExtraCSSpill = true;
13771378 }
13781379 if (Extras.size() && NumExtras == 0) {
13791380 for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
1380 MF.setPhysRegUsed(Extras[i]);
1381 MF.getRegInfo().setPhysRegUsed(Extras[i]);
13811382 AFI->setCSRegisterIsSpilled(Extras[i]);
13821383 }
13831384 } else {
13911392 }
13921393
13931394 if (ForceLRSpill) {
1394 MF.setPhysRegUsed(ARM::LR);
1395 MF.getRegInfo().setPhysRegUsed(ARM::LR);
13951396 AFI->setCSRegisterIsSpilled(ARM::LR);
13961397 AFI->setLRIsSpilledForFarJump(true);
13971398 }
14451446
14461447 if (isThumb) {
14471448 // Check if R3 is live in. It might have to be used as a scratch register.
1448 for (MachineFunction::livein_iterator I=MF.livein_begin(),E=MF.livein_end();
1449 I != E; ++I) {
1450 if ((*I).first == ARM::R3) {
1449 for (MachineRegisterInfo::livein_iterator I =MF.getRegInfo().livein_begin(),
1450 E = MF.getRegInfo().livein_end(); I != E; ++I) {
1451 if (I->first == ARM::R3) {
14511452 AFI->setR3IsLiveIn(true);
14521453 break;
14531454 }
1717 #include "llvm/CodeGen/MachineInstrBuilder.h"
1818 #include "llvm/CodeGen/MachineFrameInfo.h"
1919 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/SSARegMap.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
2121 #include "llvm/CodeGen/SelectionDAG.h"
2222 #include "llvm/CodeGen/SelectionDAGISel.h"
2323 #include "llvm/Target/TargetOptions.h"
199199 /// GOT address into a register.
200200 ///
201201 SDOperand AlphaDAGToDAGISel::getGlobalBaseReg() {
202 MachineFunction* MF = BB->getParent();
203202 unsigned GP = 0;
204 for(MachineFunction::livein_iterator ii = MF->livein_begin(),
205 ee = MF->livein_end(); ii != ee; ++ii)
203 for(MachineRegisterInfo::livein_iterator ii = RegInfo->livein_begin(),
204 ee = RegInfo->livein_end(); ii != ee; ++ii)
206205 if (ii->first == Alpha::R29) {
207206 GP = ii->second;
208207 break;
215214 /// getRASaveReg - Grab the return address
216215 ///
217216 SDOperand AlphaDAGToDAGISel::getGlobalRetAddr() {
218 MachineFunction* MF = BB->getParent();
219217 unsigned RA = 0;
220 for(MachineFunction::livein_iterator ii = MF->livein_begin(),
221 ee = MF->livein_end(); ii != ee; ++ii)
218 for(MachineRegisterInfo::livein_iterator ii = RegInfo->livein_begin(),
219 ee = RegInfo->livein_end(); ii != ee; ++ii)
222220 if (ii->first == Alpha::R26) {
223221 RA = ii->second;
224222 break;
1515 #include "llvm/CodeGen/MachineFrameInfo.h"
1616 #include "llvm/CodeGen/MachineFunction.h"
1717 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
1819 #include "llvm/CodeGen/SelectionDAG.h"
19 #include "llvm/CodeGen/SSARegMap.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
2021 #include "llvm/Constants.h"
2122 #include "llvm/Function.h"
2223 #include "llvm/Module.h"
2930 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
3031 TargetRegisterClass *RC) {
3132 assert(RC->contains(PReg) && "Not the correct regclass!");
32 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
33 MF.addLiveIn(PReg, VReg);
33 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
34 MF.getRegInfo().addLiveIn(PReg, VReg);
3435 return VReg;
3536 }
3637
311312 ArgReg = Alpha::F0;
312313 }
313314 Copy = DAG.getCopyToReg(Copy, ArgReg, Op.getOperand(1), Copy.getValue(1));
314 if (DAG.getMachineFunction().liveout_empty())
315 DAG.getMachineFunction().addLiveOut(ArgReg);
315 if (DAG.getMachineFunction().getRegInfo().liveout_empty())
316 DAG.getMachineFunction().getRegInfo().addLiveOut(ArgReg);
316317 break;
317318 }
318319 }
1919 #include "llvm/CodeGen/MachineConstantPool.h"
2020 #include "llvm/CodeGen/MachineInstrBuilder.h"
2121 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/SSARegMap.h"
2322 #include "llvm/CodeGen/SelectionDAG.h"
2423 #include "llvm/CodeGen/SelectionDAGISel.h"
2524 #include "llvm/Target/TargetOptions.h"
1919 #include "llvm/CodeGen/MachineFrameInfo.h"
2020 #include "llvm/CodeGen/MachineFunction.h"
2121 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
2223 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SSARegMap.h"
2424 #include "llvm/Constants.h"
2525 #include "llvm/Function.h"
2626 #include "llvm/Intrinsics.h"
901901 {
902902 MachineFunction &MF = DAG.getMachineFunction();
903903 MachineFrameInfo *MFI = MF.getFrameInfo();
904 SSARegMap *RegMap = MF.getSSARegMap();
904 MachineRegisterInfo &RegInfo = MF.getRegInfo();
905905 SmallVector ArgValues;
906906 SDOperand Root = Op.getOperand(0);
907907 bool isVarArg = cast(Op.getOperand(2))->getValue() != 0;
931931 }
932932 case MVT::i8:
933933 if (!isVarArg && ArgRegIdx < NumArgRegs) {
934 unsigned VReg = RegMap->createVirtualRegister(&SPU::R8CRegClass);
935 MF.addLiveIn(ArgRegs[ArgRegIdx], VReg);
934 unsigned VReg = RegInfo.createVirtualRegister(&SPU::R8CRegClass);
935 RegInfo.addLiveIn(ArgRegs[ArgRegIdx], VReg);
936936 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i8);
937937 ++ArgRegIdx;
938938 } else {
941941 break;
942942 case MVT::i16:
943943 if (!isVarArg && ArgRegIdx < NumArgRegs) {
944 unsigned VReg = RegMap->createVirtualRegister(&SPU::R16CRegClass);
945 MF.addLiveIn(ArgRegs[ArgRegIdx], VReg);
944 unsigned VReg = RegInfo.createVirtualRegister(&SPU::R16CRegClass);
945 RegInfo.addLiveIn(ArgRegs[ArgRegIdx], VReg);
946946 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i16);
947947 ++ArgRegIdx;
948948 } else {
951951 break;
952952 case MVT::i32:
953953 if (!isVarArg && ArgRegIdx < NumArgRegs) {
954 unsigned VReg = RegMap->createVirtualRegister(&SPU::R32CRegClass);
955 MF.addLiveIn(ArgRegs[ArgRegIdx], VReg);
954 unsigned VReg = RegInfo.createVirtualRegister(&SPU::R32CRegClass);
955 RegInfo.addLiveIn(ArgRegs[ArgRegIdx], VReg);
956956 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32);
957957 ++ArgRegIdx;
958958 } else {
961961 break;
962962 case MVT::i64:
963963 if (!isVarArg && ArgRegIdx < NumArgRegs) {
964 unsigned VReg = RegMap->createVirtualRegister(&SPU::R64CRegClass);
965 MF.addLiveIn(ArgRegs[ArgRegIdx], VReg);
964 unsigned VReg = RegInfo.createVirtualRegister(&SPU::R64CRegClass);
965 RegInfo.addLiveIn(ArgRegs[ArgRegIdx], VReg);
966966 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i64);
967967 ++ArgRegIdx;
968968 } else {
971971 break;
972972 case MVT::f32:
973973 if (!isVarArg && ArgRegIdx < NumArgRegs) {
974 unsigned VReg = RegMap->createVirtualRegister(&SPU::R32FPRegClass);
975 MF.addLiveIn(ArgRegs[ArgRegIdx], VReg);
974 unsigned VReg = RegInfo.createVirtualRegister(&SPU::R32FPRegClass);
975 RegInfo.addLiveIn(ArgRegs[ArgRegIdx], VReg);
976976 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::f32);
977977 ++ArgRegIdx;
978978 } else {
981981 break;
982982 case MVT::f64:
983983 if (!isVarArg && ArgRegIdx < NumArgRegs) {
984 unsigned VReg = RegMap->createVirtualRegister(&SPU::R64FPRegClass);
985 MF.addLiveIn(ArgRegs[ArgRegIdx], VReg);
984 unsigned VReg = RegInfo.createVirtualRegister(&SPU::R64FPRegClass);
985 RegInfo.addLiveIn(ArgRegs[ArgRegIdx], VReg);
986986 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::f64);
987987 ++ArgRegIdx;
988988 } else {
995995 case MVT::v8i16:
996996 case MVT::v16i8:
997997 if (!isVarArg && ArgRegIdx < NumArgRegs) {
998 unsigned VReg = RegMap->createVirtualRegister(&SPU::VECREGRegClass);
999 MF.addLiveIn(ArgRegs[ArgRegIdx], VReg);
998 unsigned VReg = RegInfo.createVirtualRegister(&SPU::VECREGRegClass);
999 RegInfo.addLiveIn(ArgRegs[ArgRegIdx], VReg);
10001000 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
10011001 ++ArgRegIdx;
10021002 } else {
10361036 // result of va_next.
10371037 SmallVector MemOps;
10381038 for (; ArgRegIdx != NumArgRegs; ++ArgRegIdx) {
1039 unsigned VReg = RegMap->createVirtualRegister(&SPU::GPRCRegClass);
1040 MF.addLiveIn(ArgRegs[ArgRegIdx], VReg);
1039 unsigned VReg = RegInfo.createVirtualRegister(&SPU::GPRCRegClass);
1040 RegInfo.addLiveIn(ArgRegs[ArgRegIdx], VReg);
10411041 SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
10421042 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
10431043 MemOps.push_back(Store);
12931293
12941294 // If this is the first return lowered for this function, add the regs to the
12951295 // liveout set for the function.
1296 if (DAG.getMachineFunction().liveout_empty()) {
1296 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
12971297 for (unsigned i = 0; i != RVLocs.size(); ++i)
1298 DAG.getMachineFunction().addLiveOut(RVLocs[i].getLocReg());
1298 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
12991299 }
13001300
13011301 SDOperand Chain = Op.getOperand(0);
17841784 if (EltsFromV2 == 1 && monotonic) {
17851785 // Compute mask and shuffle
17861786 MachineFunction &MF = DAG.getMachineFunction();
1787 SSARegMap *RegMap = MF.getSSARegMap();
1788 unsigned VReg = RegMap->createVirtualRegister(&SPU::R32CRegClass);
1787 MachineRegisterInfo &RegInfo = MF.getRegInfo();
1788 unsigned VReg = RegInfo.createVirtualRegister(&SPU::R32CRegClass);
17891789 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
17901790 // Initialize temporary register to 0
17911791 SDOperand InitTempReg =
18921892 // the wacky side
18931893 case MVT::v8i16: {
18941894 MachineFunction &MF = DAG.getMachineFunction();
1895 SSARegMap *RegMap = MF.getSSARegMap();
1895 MachineRegisterInfo &RegInfo = MF.getRegInfo();
18961896 SDOperand Chain = Op.getOperand(0);
18971897 SDOperand rA = Op.getOperand(0);
18981898 SDOperand rB = Op.getOperand(1);
1899 unsigned FSMBIreg = RegMap->createVirtualRegister(&SPU::VECREGRegClass);
1900 unsigned HiProdReg = RegMap->createVirtualRegister(&SPU::VECREGRegClass);
1899 unsigned FSMBIreg = RegInfo.createVirtualRegister(&SPU::VECREGRegClass);
1900 unsigned HiProdReg = RegInfo.createVirtualRegister(&SPU::VECREGRegClass);
19011901
19021902 SDOperand FSMBOp =
19031903 DAG.getCopyToReg(Chain, FSMBIreg,
19281928 // intermediate products.
19291929 case MVT::v16i8: {
19301930 MachineFunction &MF = DAG.getMachineFunction();
1931 SSARegMap *RegMap = MF.getSSARegMap();
1931 MachineRegisterInfo &RegInfo = MF.getRegInfo();
19321932 SDOperand Chain = Op.getOperand(0);
19331933 SDOperand rA = Op.getOperand(0);
19341934 SDOperand rB = Op.getOperand(1);
19351935 SDOperand c8 = DAG.getConstant(8, MVT::i8);
19361936 SDOperand c16 = DAG.getConstant(16, MVT::i8);
19371937
1938 unsigned FSMBreg_2222 = RegMap->createVirtualRegister(&SPU::VECREGRegClass);
1939 unsigned LoProd_reg = RegMap->createVirtualRegister(&SPU::VECREGRegClass);
1940 unsigned HiProd_reg = RegMap->createVirtualRegister(&SPU::VECREGRegClass);
1938 unsigned FSMBreg_2222 = RegInfo.createVirtualRegister(&SPU::VECREGRegClass);
1939 unsigned LoProd_reg = RegInfo.createVirtualRegister(&SPU::VECREGRegClass);
1940 unsigned HiProd_reg = RegInfo.createVirtualRegister(&SPU::VECREGRegClass);
19411941
19421942 SDOperand LLProd =
19431943 DAG.getNode(SPUISD::MPY, MVT::v8i16,
20232023
20242024 static SDOperand LowerFDIVf32(SDOperand Op, SelectionDAG &DAG) {
20252025 MachineFunction &MF = DAG.getMachineFunction();
2026 SSARegMap *RegMap = MF.getSSARegMap();
2026 MachineRegisterInfo &RegInfo = MF.getRegInfo();
20272027
20282028 SDOperand A = Op.getOperand(0);
20292029 SDOperand B = Op.getOperand(1);
20322032 unsigned VRegBR, VRegC;
20332033
20342034 if (VT == MVT::f32) {
2035 VRegBR = RegMap->createVirtualRegister(&SPU::R32FPRegClass);
2036 VRegC = RegMap->createVirtualRegister(&SPU::R32FPRegClass);
2035 VRegBR = RegInfo.createVirtualRegister(&SPU::R32FPRegClass);
2036 VRegC = RegInfo.createVirtualRegister(&SPU::R32FPRegClass);
20372037 } else {
2038 VRegBR = RegMap->createVirtualRegister(&SPU::VECREGRegClass);
2039 VRegC = RegMap->createVirtualRegister(&SPU::VECREGRegClass);
2038 VRegBR = RegInfo.createVirtualRegister(&SPU::VECREGRegClass);
2039 VRegC = RegInfo.createVirtualRegister(&SPU::VECREGRegClass);
20402040 }
20412041 // TODO: make sure we're feeding FPInterp the right arguments
20422042 // Right now: fi B, frest(B)
20642064 DAG.getNode(ISD::FMUL, VT, B,
20652065 DAG.getCopyFromReg(AxBRcpl, VRegC, VT)))));
20662066 }
2067
2068 // Expands double-precision FDIV
2069 // Expects two doubles as inputs X and Y, does a floating point
2070 // reciprocal estimate, and three iterations of Newton-Raphson
2071 // to increase accuracy.
2072 //static SDOperand LowerFDIVf64(SDOperand Op, SelectionDAG &DAG) {
2073 // MachineFunction &MF = DAG.getMachineFunction();
2074 // SSARegMap *RegMap = MF.getSSARegMap();
2075 //
2076 // SDOperand X = Op.getOperand(0);
2077 // SDOperand Y = Op.getOperand(1);
2078 //}
20792067
20802068 static SDOperand LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
20812069 unsigned VT = Op.getValueType();
23642352
23652353 case MVT::i16: {
23662354 MachineFunction &MF = DAG.getMachineFunction();
2367 SSARegMap *RegMap = MF.getSSARegMap();
2368
2369 unsigned CNTB_reg = RegMap->createVirtualRegister(&SPU::R16CRegClass);
2355 MachineRegisterInfo &RegInfo = MF.getRegInfo();
2356
2357 unsigned CNTB_reg = RegInfo.createVirtualRegister(&SPU::R16CRegClass);
23702358
23712359 SDOperand N = Op.getOperand(0);
23722360 SDOperand Elt0 = DAG.getConstant(0, MVT::i16);
23962384
23972385 case MVT::i32: {
23982386 MachineFunction &MF = DAG.getMachineFunction();
2399 SSARegMap *RegMap = MF.getSSARegMap();
2400
2401 unsigned CNTB_reg = RegMap->createVirtualRegister(&SPU::R32CRegClass);
2402 unsigned SUM1_reg = RegMap->createVirtualRegister(&SPU::R32CRegClass);
2387 MachineRegisterInfo &RegInfo = MF.getRegInfo();
2388
2389 unsigned CNTB_reg = RegInfo.createVirtualRegister(&SPU::R32CRegClass);
2390 unsigned SUM1_reg = RegInfo.createVirtualRegister(&SPU::R32CRegClass);
24032391
24042392 SDOperand N = Op.getOperand(0);
24052393 SDOperand Elt0 = DAG.getConstant(0, MVT::i32);
2626 #include "llvm/CodeGen/MachineFunction.h"
2727 #include "llvm/CodeGen/MachineFrameInfo.h"
2828 #include "llvm/CodeGen/MachineLocation.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
2930 #include "llvm/CodeGen/SelectionDAGNodes.h"
3031 #include "llvm/CodeGen/ValueTypes.h"
3132 #include "llvm/Target/TargetFrameInfo.h"
669670 #if 0
670671 // Save and clear the LR state.
671672 SPUFunctionInfo *FI = MF.getInfo();
672 FI->setUsesLR(MF.isPhysRegUsed(LR));
673 FI->setUsesLR(MF.getRegInfo().isPhysRegUsed(LR));
673674 #endif
674675 // Mark LR and SP unused, since the prolog spills them to stack and
675676 // we don't want anyone else to spill them for us.
676677 //
677678 // Also, unless R2 is really used someday, don't spill it automatically.
678 MF.setPhysRegUnused(SPU::R0);
679 MF.setPhysRegUnused(SPU::R1);
680 MF.setPhysRegUnused(SPU::R2);
679 MF.getRegInfo().setPhysRegUnused(SPU::R0);
680 MF.getRegInfo().setPhysRegUnused(SPU::R1);
681 MF.getRegInfo().setPhysRegUnused(SPU::R2);
681682 }
682683
683684 void SPURegisterInfo::emitPrologue(MachineFunction &MF) const
1717 #include "IA64ISelLowering.h"
1818 #include "llvm/CodeGen/MachineInstrBuilder.h"
1919 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/SSARegMap.h"
2120 #include "llvm/CodeGen/SelectionDAG.h"
2221 #include "llvm/CodeGen/SelectionDAGISel.h"
2322 #include "llvm/Target/TargetOptions.h"
1717 #include "llvm/CodeGen/MachineFunction.h"
1818 #include "llvm/CodeGen/MachineInstrBuilder.h"
1919 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/CodeGen/SSARegMap.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
2121 #include "llvm/Constants.h"
2222 #include "llvm/Function.h"
2323 using namespace llvm;
147147 MachineFrameInfo *MFI = MF.getFrameInfo();
148148 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
149149
150 GP = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
151 SP = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
152 RP = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
150 GP = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
151 SP = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
152 RP = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
153153
154154 MachineBasicBlock& BB = MF.front();
155155
181181 // see intel ABI docs)
182182 case MVT::f64:
183183 //XXX BuildMI(&BB, IA64::IDEF, 0, args_FP[used_FPArgs]);
184 MF.addLiveIn(args_FP[used_FPArgs]); // mark this reg as liveIn
184 MF.getRegInfo().addLiveIn(args_FP[used_FPArgs]);
185 // mark this reg as liveIn
185186 // floating point args go into f8..f15 as-needed, the increment
186187 argVreg[count] = // is below..:
187 MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::f64));
188 MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::f64));
188189 // FP args go into f8..f15 as needed: (hence the ++)
189190 argPreg[count] = args_FP[used_FPArgs++];
190191 argOpc[count] = IA64::FMOV;
200201 case MVT::i32:
201202 case MVT::i64:
202203 //XXX BuildMI(&BB, IA64::IDEF, 0, args_int[count]);
203 MF.addLiveIn(args_int[count]); // mark this register as liveIn
204 MF.getRegInfo().addLiveIn(args_int[count]);
205 // mark this register as liveIn
204206 argVreg[count] =
205 MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
207 MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
206208 argPreg[count] = args_int[count];
207209 argOpc[count] = IA64::MOV;
208210 argt = newroot =
231233
232234 // Create a vreg to hold the output of (what will become)
233235 // the "alloc" instruction
234 VirtGPR = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64));
236 VirtGPR = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64));
235237 BuildMI(&BB, TII->get(IA64::PSEUDO_ALLOC), VirtGPR);
236238 // we create a PSEUDO_ALLOC (pseudo)instruction for now
237239 /*
283285 case MVT::i16:
284286 case MVT::i32:
285287 case MVT::i64:
286 MF.addLiveOut(IA64::r8);
288 MF.getRegInfo().addLiveOut(IA64::r8);
287289 break;
288290 case MVT::f32:
289291 case MVT::f64:
290 MF.addLiveOut(IA64::F8);
292 MF.getRegInfo().addLiveOut(IA64::F8);
291293 break;
292294 }
293295
2222 #include "llvm/CodeGen/MachineFunction.h"
2323 #include "llvm/CodeGen/MachineFrameInfo.h"
2424 #include "llvm/CodeGen/MachineLocation.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
2526 #include "llvm/Target/TargetFrameInfo.h"
2627 #include "llvm/Target/TargetMachine.h"
2728 #include "llvm/Target/TargetOptions.h"
2829 #include "llvm/Target/TargetInstrInfo.h"
29 #include "llvm/Support/CommandLine.h"
3030 #include "llvm/ADT/BitVector.h"
3131 #include "llvm/ADT/STLExtras.h"
3232 using namespace llvm;
327327 IA64::r126, IA64::r127 };
328328
329329 unsigned numStackedGPRsUsed=0;
330 for(int i=0; i<96; i++) {
331 if(MF.isPhysRegUsed(RegsInOrder[i]))
330 for (int i=0; i != 96; i++) {
331 if (MF.getRegInfo().isPhysRegUsed(RegsInOrder[i]))
332332 numStackedGPRsUsed=i+1; // (i+1 and not ++ - consider fn(fp, fp, int)
333333 }
334334
1111 //===----------------------------------------------------------------------===//
1212
1313 #define DEBUG_TYPE "mips-isel"
14
1514 #include "Mips.h"
1615 #include "MipsISelLowering.h"
1716 #include "MipsMachineFunction.h"
2726 #include "llvm/CodeGen/MachineFunction.h"
2827 #include "llvm/CodeGen/MachineFrameInfo.h"
2928 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
3030 #include "llvm/CodeGen/SelectionDAGISel.h"
3131 #include "llvm/Target/TargetMachine.h"
3232 #include "llvm/Support/Compiler.h"
126126
127127 /// getGlobalBaseReg - Output the instructions required to put the
128128 /// GOT address into a register.
129 SDOperand MipsDAGToDAGISel::getGlobalBaseReg()
130 {
129 SDOperand MipsDAGToDAGISel::getGlobalBaseReg() {
131130 MachineFunction* MF = BB->getParent();
132131 unsigned GP = 0;
133 for(MachineFunction::livein_iterator ii = MF->livein_begin(),
134 ee = MF->livein_end(); ii != ee; ++ii)
132 for(MachineRegisterInfo::livein_iterator ii = MF->getRegInfo().livein_begin(),
133 ee = MF->getRegInfo().livein_end(); ii != ee; ++ii)
135134 if (ii->first == Mips::GP) {
136135 GP = ii->second;
137136 break;
2424 #include "llvm/CodeGen/MachineFrameInfo.h"
2525 #include "llvm/CodeGen/MachineFunction.h"
2626 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
2728 #include "llvm/CodeGen/SelectionDAGISel.h"
28 #include "llvm/CodeGen/SSARegMap.h"
2929 #include "llvm/CodeGen/ValueTypes.h"
3030 #include "llvm/Support/Debug.h"
3131 #include
138138 AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
139139 {
140140 assert(RC->contains(PReg) && "Not the correct regclass!");
141 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
142 MF.addLiveIn(PReg, VReg);
141 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
142 MF.getRegInfo().addLiveIn(PReg, VReg);
143143 return VReg;
144144 }
145145
595595
596596 // If this is the first return lowered for this function, add
597597 // the regs to the liveout set for the function.
598 if (DAG.getMachineFunction().liveout_empty()) {
598 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
599599 for (unsigned i = 0; i != RVLocs.size(); ++i)
600600 if (RVLocs[i].isRegLoc())
601 DAG.getMachineFunction().addLiveOut(RVLocs[i].getLocReg());
601 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
602602 }
603603
604604 // The chain is always operand #0
1919 #include "PPCHazardRecognizers.h"
2020 #include "llvm/CodeGen/MachineInstrBuilder.h"
2121 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/SSARegMap.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
2323 #include "llvm/CodeGen/SelectionDAG.h"
2424 #include "llvm/CodeGen/SelectionDAGISel.h"
2525 #include "llvm/Target/TargetOptions.h"
223223 // In this case, there will be virtual registers of vector type type created
224224 // by the scheduler. Detect them now.
225225 MachineFunction &Fn = MachineFunction::get(&F);
226 SSARegMap *RegMap = Fn.getSSARegMap();
227226 bool HasVectorVReg = false;
228227 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
229 e = RegMap->getLastVirtReg()+1; i != e; ++i)
230 if (RegMap->getRegClass(i) == &PPC::VRRCRegClass) {
228 e = RegInfo->getLastVirtReg()+1; i != e; ++i)
229 if (RegInfo->getRegClass(i) == &PPC::VRRCRegClass) {
231230 HasVectorVReg = true;
232231 break;
233232 }
245244
246245 // Create two vregs - one to hold the VRSAVE register that is live-in to the
247246 // function and one for the value after having bits or'd into it.
248 unsigned InVRSAVE = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
249 unsigned UpdatedVRSAVE = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
247 unsigned InVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
248 unsigned UpdatedVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
250249
251250 const TargetInstrInfo &TII = *TM.getInstrInfo();
252251 MachineBasicBlock &EntryBB = *Fn.begin();
286285 // Insert the set of GlobalBaseReg into the first MBB of the function
287286 MachineBasicBlock &FirstMBB = BB->getParent()->front();
288287 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
289 SSARegMap *RegMap = BB->getParent()->getSSARegMap();
290288
291289 if (PPCLowering.getPointerTy() == MVT::i32) {
292 GlobalBaseReg = RegMap->createVirtualRegister(PPC::GPRCRegisterClass);
290 GlobalBaseReg = RegInfo->createVirtualRegister(PPC::GPRCRegisterClass);
293291 BuildMI(FirstMBB, MBBI, TII.get(PPC::MovePCtoLR), PPC::LR);
294292 BuildMI(FirstMBB, MBBI, TII.get(PPC::MFLR), GlobalBaseReg);
295293 } else {
296 GlobalBaseReg = RegMap->createVirtualRegister(PPC::G8RCRegisterClass);
294 GlobalBaseReg = RegInfo->createVirtualRegister(PPC::G8RCRegisterClass);
297295 BuildMI(FirstMBB, MBBI, TII.get(PPC::MovePCtoLR8), PPC::LR8);
298296 BuildMI(FirstMBB, MBBI, TII.get(PPC::MFLR8), GlobalBaseReg);
299297 }
2222 #include "llvm/CodeGen/MachineFrameInfo.h"
2323 #include "llvm/CodeGen/MachineFunction.h"
2424 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
2526 #include "llvm/CodeGen/SelectionDAG.h"
26 #include "llvm/CodeGen/SSARegMap.h"
2727 #include "llvm/Constants.h"
2828 #include "llvm/Function.h"
2929 #include "llvm/Intrinsics.h"
12641264 //
12651265 MachineFunction &MF = DAG.getMachineFunction();
12661266 MachineFrameInfo *MFI = MF.getFrameInfo();
1267 SSARegMap *RegMap = MF.getSSARegMap();
1267 MachineRegisterInfo &RegInfo = MF.getRegInfo();
12681268 SmallVector ArgValues;
12691269 SDOperand Root = Op.getOperand(0);
12701270
13281328 // Double word align in ELF
13291329 if (Expand && isELF32_ABI) GPR_idx += (GPR_idx % 2);
13301330 if (GPR_idx != Num_GPR_Regs) {
1331 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
1332 MF.addLiveIn(GPR[GPR_idx], VReg);
1331 unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
1332 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
13331333 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32);
13341334 ++GPR_idx;
13351335 } else {
13451345
13461346 case MVT::i64: // PPC64
13471347 if (GPR_idx != Num_GPR_Regs) {
1348 unsigned VReg = RegMap->createVirtualRegister(&PPC::G8RCRegClass);
1349 MF.addLiveIn(GPR[GPR_idx], VReg);
1348 unsigned VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass);
1349 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
13501350 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i64);
13511351 ++GPR_idx;
13521352 } else {
13681368 if (FPR_idx != Num_FPR_Regs) {
13691369 unsigned VReg;
13701370 if (ObjectVT == MVT::f32)
1371 VReg = RegMap->createVirtualRegister(&PPC::F4RCRegClass);
1371 VReg = RegInfo.createVirtualRegister(&PPC::F4RCRegClass);
13721372 else
1373 VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass);
1374 MF.addLiveIn(FPR[FPR_idx], VReg);
1373 VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
1374 RegInfo.addLiveIn(FPR[FPR_idx], VReg);
13751375 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
13761376 ++FPR_idx;
13771377 } else {
13901390 case MVT::v16i8:
13911391 // Note that vector arguments in registers don't reserve stack space.
13921392 if (VR_idx != Num_VR_Regs) {
1393 unsigned VReg = RegMap->createVirtualRegister(&PPC::VRRCRegClass);
1394 MF.addLiveIn(VR[VR_idx], VReg);
1393 unsigned VReg = RegInfo.createVirtualRegister(&PPC::VRRCRegClass);
1394 RegInfo.addLiveIn(VR[VR_idx], VReg);
13951395 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
13961396 ++VR_idx;
13971397 } else {
14701470 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
14711471 unsigned VReg;
14721472 if (isPPC64)
1473 VReg = RegMap->createVirtualRegister(&PPC::G8RCRegClass);
1473 VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass);
14741474 else
1475 VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
1476
1477 MF.addLiveIn(GPR[GPR_idx], VReg);
1475 VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
1476
1477 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
14781478 SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
14791479 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
14801480 MemOps.push_back(Store);
14981498
14991499 for (; FPR_idx != Num_FPR_Regs; ++FPR_idx) {
15001500 unsigned VReg;
1501 VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass);
1502
1503 MF.addLiveIn(FPR[FPR_idx], VReg);
1501 VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
1502
1503 RegInfo.addLiveIn(FPR[FPR_idx], VReg);
15041504 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::f64);
15051505 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
15061506 MemOps.push_back(Store);
19041904
19051905 // If this is the first return lowered for this function, add the regs to the
19061906 // liveout set for the function.
1907 if (DAG.getMachineFunction().liveout_empty()) {
1907 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
19081908 for (unsigned i = 0; i != RVLocs.size(); ++i)
1909 DAG.getMachineFunction().addLiveOut(RVLocs[i].getLocReg());
1909 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
19101910 }
19111911
19121912 SDOperand Chain = Op.getOperand(0);
2525 #include "llvm/CodeGen/MachineFunction.h"
2626 #include "llvm/CodeGen/MachineFrameInfo.h"
2727 #include "llvm/CodeGen/MachineLocation.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
2829 #include "llvm/CodeGen/SelectionDAGNodes.h"
2930 #include "llvm/Target/TargetFrameInfo.h"
3031 #include "llvm/Target/TargetInstrInfo.h"
910911
911912 unsigned UsedRegMask = 0;
912913 for (unsigned i = 0; i != 32; ++i)
913 if (MF->isPhysRegUsed(VRRegNo[i]))
914 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i]))
914915 UsedRegMask |= 1 << (31-i);
915916
916917 // Live in and live out values already must be in the mask, so don't bother
917918 // marking them.
918 for (MachineFunction::livein_iterator I =
919 MF->livein_begin(), E = MF->livein_end(); I != E; ++I) {
919 for (MachineRegisterInfo::livein_iterator
920 I = MF->getRegInfo().livein_begin(),
921 E = MF->getRegInfo().livein_end(); I != E; ++I) {
920922 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first);
921923 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
922924 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
923925 }
924 for (MachineFunction::liveout_iterator I =
925 MF->liveout_begin(), E = MF->liveout_end(); I != E; ++I) {
926 for (MachineRegisterInfo::liveout_iterator
927 I = MF->getRegInfo().liveout_begin(),
928 E = MF->getRegInfo().liveout_end(); I != E; ++I) {
926929 unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I);
927930 if (VRRegNo[RegNo] == *I) // If this really is a vector reg.
928931 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
10111014 // Save and clear the LR state.
10121015 PPCFunctionInfo *FI = MF.getInfo();
10131016 unsigned LR = getRARegister();
1014 FI->setUsesLR(MF.isPhysRegUsed(LR));
1015 MF.setPhysRegUnused(LR);
1017 FI->setUsesLR(MF.getRegInfo().isPhysRegUsed(LR));
1018 MF.getRegInfo().setPhysRegUnused(LR);
10161019
10171020 // Save R31 if necessary
10181021 int FPSI = FI->getFramePointerSaveIndex();
10221025 const MachineFrameInfo *MFI = MF.getFrameInfo();
10231026
10241027 // If the frame pointer save index hasn't been defined yet.
1025 if (!FPSI && (NoFramePointerElim || MFI->hasVarSizedObjects())
1026 && IsELF32_ABI) {
1028 if (!FPSI && (NoFramePointerElim || MFI->hasVarSizedObjects()) &&
1029 IsELF32_ABI) {
10271030 // Find out what the fix offset of the frame pointer save area.
10281031 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64,
10291032 IsMachoABI);
1818 #include "llvm/CodeGen/MachineFrameInfo.h"
1919 #include "llvm/CodeGen/MachineFunction.h"
2020 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
2122 #include "llvm/CodeGen/SelectionDAG.h"
2223 #include "llvm/CodeGen/SelectionDAGISel.h"
23 #include "llvm/CodeGen/SSARegMap.h"
2424 #include "llvm/Target/TargetLowering.h"
2525 #include "llvm/Support/Debug.h"
2626 #include
297297 std::vector
298298 SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
299299 MachineFunction &MF = DAG.getMachineFunction();
300 SSARegMap *RegMap = MF.getSSARegMap();
300 MachineRegisterInfo &RegInfo = MF.getRegInfo();
301301 std::vector ArgValues;
302302
303303 static const unsigned ArgRegs[] = {
323323 if (CurArgReg < ArgRegEnd) ++CurArgReg;
324324 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
325325 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
326 unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
327 MF.addLiveIn(*CurArgReg++, VReg);
326 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
327 MF.getRegInfo().addLiveIn(*CurArgReg++, VReg);
328328 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
329329 if (ObjectVT != MVT::i32) {
330330 unsigned AssertOp = ISD::AssertSext;
361361 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
362362 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
363363 // FP value is passed in an integer register.
364 unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
365 MF.addLiveIn(*CurArgReg++, VReg);
364 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
365 MF.getRegInfo().addLiveIn(*CurArgReg++, VReg);
366366 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
367367
368368 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg);
395395 } else {
396396 SDOperand HiVal;
397397 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
398 unsigned VRegHi = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
399 MF.addLiveIn(*CurArgReg++, VRegHi);
398 unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
399 MF.getRegInfo().addLiveIn(*CurArgReg++, VRegHi);
400400 HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32);
401401 } else {
402402 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
406406
407407 SDOperand LoVal;
408408 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
409 unsigned VRegLo = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
410 MF.addLiveIn(*CurArgReg++, VRegLo);
409 unsigned VRegLo = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
410 MF.getRegInfo().addLiveIn(*CurArgReg++, VRegLo);
411411 LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32);
412412 } else {
413413 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4);
436436 VarArgsFrameOffset = ArgOffset;
437437
438438 for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
439 unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
440 MF.addLiveIn(*CurArgReg, VReg);
439 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
440 MF.getRegInfo().addLiveIn(*CurArgReg, VReg);
441441 SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
442442
443443 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
460460 case MVT::i8:
461461 case MVT::i16:
462462 case MVT::i32:
463 MF.addLiveOut(SP::I0);
463 MF.getRegInfo().addLiveOut(SP::I0);
464464 break;
465465 case MVT::i64:
466 MF.addLiveOut(SP::I0);
467 MF.addLiveOut(SP::I1);
466 MF.getRegInfo().addLiveOut(SP::I0);
467 MF.getRegInfo().addLiveOut(SP::I1);
468468 break;
469469 case MVT::f32:
470 MF.addLiveOut(SP::F0);
470 MF.getRegInfo().addLiveOut(SP::F0);
471471 break;
472472 case MVT::f64:
473 MF.addLiveOut(SP::D0);
473 MF.getRegInfo().addLiveOut(SP::D0);
474474 break;
475475 }
476476
3232 #include "X86InstrInfo.h"
3333 #include "llvm/CodeGen/MachineFunctionPass.h"
3434 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
3536 #include "llvm/CodeGen/LiveVariables.h"
3637 #include "llvm/CodeGen/Passes.h"
3738 #include "llvm/Target/TargetInstrInfo.h"
168169
169170 assert(X86::FP6 == X86::FP0+6 && "Register enums aren't sorted right!");
170171 for (unsigned i = 0; i <= 6; ++i)
171 if (MF.isPhysRegUsed(X86::FP0+i)) {
172 if (MF.getRegInfo().isPhysRegUsed(X86::FP0+i)) {
172173 FPIsUsed = true;
173174 break;
174175 }
2727 #include "llvm/CodeGen/MachineFunction.h"
2828 #include "llvm/CodeGen/MachineFrameInfo.h"
2929 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/SSARegMap.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
3131 #include "llvm/CodeGen/SelectionDAGISel.h"
3232 #include "llvm/Target/TargetMachine.h"
3333 #include "llvm/Support/Compiler.h"
503503 for (unsigned op = 0, e = I->getNumOperands(); op != e; ++op) {
504504 if (I->getOperand(op).isRegister() && I->getOperand(op).isDef() &&
505505 MRegisterInfo::isVirtualRegister(I->getOperand(op).getReg()) &&
506 ((clas = RegMap->getRegClass(I->getOperand(0).getReg())) ==
506 ((clas = RegInfo->getRegClass(I->getOperand(0).getReg())) ==
507507 X86::RFP32RegisterClass ||
508508 clas == X86::RFP64RegisterClass ||
509509 clas == X86::RFP80RegisterClass)) {
989989 // Insert the set of GlobalBaseReg into the first MBB of the function
990990 MachineBasicBlock &FirstMBB = BB->getParent()->front();
991991 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
992 SSARegMap *RegMap = BB->getParent()->getSSARegMap();
993 unsigned PC = RegMap->createVirtualRegister(X86::GR32RegisterClass);
992 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
993 unsigned PC = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
994994
995995 const TargetInstrInfo *TII = TM.getInstrInfo();
996996 // Operand of MovePCtoStack is completely ignored by asm printer. It's
10021002 // not to pc, but to _GLOBAL_ADDRESS_TABLE_ external
10031003 if (TM.getRelocationModel() == Reloc::PIC_ &&
10041004 Subtarget->isPICStyleGOT()) {
1005 GlobalBaseReg = RegMap->createVirtualRegister(X86::GR32RegisterClass);
1005 GlobalBaseReg = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
10061006 BuildMI(FirstMBB, MBBI, TII->get(X86::ADD32ri), GlobalBaseReg).
10071007 addReg(PC).
10081008 addExternalSymbol("_GLOBAL_OFFSET_TABLE_");
2929 #include "llvm/CodeGen/MachineFrameInfo.h"
3030 #include "llvm/CodeGen/MachineFunction.h"
3131 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
3233 #include "llvm/CodeGen/SelectionDAG.h"
33 #include "llvm/CodeGen/SSARegMap.h"
3434 #include "llvm/Support/MathExtras.h"
3535 #include "llvm/Support/Debug.h"
3636 #include "llvm/Target/TargetOptions.h"
702702
703703 // If this is the first return lowered for this function, add the regs to the
704704 // liveout set for the function.
705 if (DAG.getMachineFunction().liveout_empty()) {
705 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
706706 for (unsigned i = 0; i != RVLocs.size(); ++i)
707707 if (RVLocs[i].isRegLoc())
708 DAG.getMachineFunction().addLiveOut(RVLocs[i].getLocReg());
708 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
709709 }
710710 SDOperand Chain = Op.getOperand(0);
711711
932932 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
933933 const TargetRegisterClass *RC) {
934934 assert(RC->contains(PReg) && "Not the correct regclass!");
935 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
936 MF.addLiveIn(PReg, VReg);
935 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
936 MF.getRegInfo().addLiveIn(PReg, VReg);
937937 return VReg;
938938 }
939939
17531753 Callee,InFlag);
17541754 Callee = DAG.getRegister(Opc, getPointerTy());
17551755 // Add register as live out.
1756 DAG.getMachineFunction().addLiveOut(Opc);
1756 DAG.getMachineFunction().getRegInfo().addLiveOut(Opc);
17571757 }
17581758
17591759 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
52875287 StoreAddr = DAG.getNode(ISD::ADD, getPointerTy(), StoreAddr, Offset);
52885288 Chain = DAG.getStore(Chain, Handler, StoreAddr, NULL, 0);
52895289 Chain = DAG.getCopyToReg(Chain, X86::ECX, StoreAddr);
5290 MF.addLiveOut(X86::ECX);
5290 MF.getRegInfo().addLiveOut(X86::ECX);
52915291
52925292 return DAG.getNode(X86ISD::EH_RETURN, MVT::Other,
52935293 Chain, DAG.getRegister(X86::ECX, getPointerTy()));
58015801
58025802 // Load the old value of the high byte of the control word...
58035803 unsigned OldCW =
5804 F->getSSARegMap()->createVirtualRegister(X86::GR16RegisterClass);
5804 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass);
58055805 addFrameReference(BuildMI(BB, TII->get(X86::MOV16rm), OldCW), CWFrameIdx);
58065806
58075807 // Set the high part to be round to zero...
1818 #include "X86TargetMachine.h"
1919 #include "llvm/ADT/STLExtras.h"
2020 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
2122 #include "llvm/CodeGen/LiveVariables.h"
22 #include "llvm/CodeGen/SSARegMap.h"
2323 #include "llvm/Target/TargetOptions.h"
2424 using namespace llvm;
2525
315315
316316 if (DisableLEA16) {
317317 // If 16-bit LEA is disabled, use 32-bit LEA via subregisters.
318 SSARegMap *RegMap = MFI->getParent()->getSSARegMap();
318 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
319319 unsigned Opc = TM.getSubtarget().is64Bit()
320320 ? X86::LEA64_32r : X86::LEA32r;
321 unsigned leaInReg = RegMap->createVirtualRegister(&X86::GR32RegClass);
322 unsigned leaOutReg = RegMap->createVirtualRegister(&X86::GR32RegClass);
321 unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
322 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
323323
324324 MachineInstr *Ins =
325325 BuildMI(get(X86::INSERT_SUBREG), leaInReg).addReg(Src).addImm(2);
2525 #include "llvm/CodeGen/MachineFunction.h"
2626 #include "llvm/CodeGen/MachineFrameInfo.h"
2727 #include "llvm/CodeGen/MachineLocation.h"
28 #include "llvm/CodeGen/SSARegMap.h"
28 #include "llvm/CodeGen/MachineModuleInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
2930 #include "llvm/Target/TargetAsmInfo.h"
3031 #include "llvm/Target/TargetFrameInfo.h"
3132 #include "llvm/Target/TargetInstrInfo.h"
18421843 if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
18431844 // Check, whether EAX is livein for this function
18441845 bool isEAXAlive = false;
1845 for (MachineFunction::livein_iterator II = MF.livein_begin(),
1846 EE = MF.livein_end(); (II != EE) && !isEAXAlive; ++II) {
1846 for (MachineRegisterInfo::livein_iterator
1847 II = MF.getRegInfo().livein_begin(),
1848 EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) {
18471849 unsigned Reg = II->first;
18481850 isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
18491851 Reg == X86::AH || Reg == X86::AL);
19031905 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
19041906 } else {
19051907 MachineLocation SPDst(MachineLocation::VirtualFP);
1906 MachineLocation SPSrc(MachineLocation::VirtualFP, -StackSize+stackGrowth);
1908 MachineLocation SPSrc(MachineLocation::VirtualFP,
1909 -StackSize+stackGrowth);
19071910 Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
19081911 }
19091912 } else {