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Merging r325653 with test fixups: ------------------------------------------------------------------------ r325653 | sdardis | 2018-02-21 00:06:53 +0000 (Wed, 21 Feb 2018) | 31 lines [mips] Spectre variant two mitigation for MIPSR2 This patch provides mitigation for CVE-2017-5715, Spectre variant two, which affects the P5600 and P6600. It implements the LLVM part of -mindirect-jump=hazard. It is _not_ enabled by default for the P5600. The migitation strategy suggested by MIPS for these processors is to use hazard barrier instructions. 'jalr.hb' and 'jr.hb' are hazard barrier variants of the 'jalr' and 'jr' instructions respectively. These instructions impede the execution of instruction stream until architecturally defined hazards (changes to the instruction stream, privileged registers which may affect execution) are cleared. These instructions in MIPS' designs are not speculated past. These instructions are used with the attribute +use-indirect-jump-hazard when branching indirectly and for indirect function calls. These instructions are defined by the MIPS32R2 ISA, so this mitigation method is not compatible with processors which implement an earlier revision of the MIPS ISA. Performance benchmarking of this option with -fpic and lld using -z hazardplt shows a difference of overall 10%~ time increase for the LLVM testsuite. Certain benchmarks such as methcall show a substantially larger increase in time due to their nature. Reviewers: atanasyan, zoran.jovanovic Differential Revision: https://reviews.llvm.org/D43486 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@329798 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Dardis 2 years ago
22 changed file(s) with 1425 addition(s) and 42 deletion(s). Raw diff Collapse all Expand all
51355135 // It also applies for registers Rt and Rs of microMIPSr6 jalrc.hb instruction
51365136 // and registers Rd and Base for microMIPS lwp instruction
51375137 case Mips::JALR_HB:
5138 case Mips::JALR_HB64:
51385139 case Mips::JALRC_HB_MMR6:
51395140 case Mips::JALRC_MMR6:
51405141 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg())
18851885
18861886 def TAILCALL_MMR6 : TailCall, ISA_MICROMIPS32R6;
18871887
1888 def TAILCALLREG_MMR6 : TailCallReg, ISA_MICROMIPS32R6;
1889
1890 def PseudoIndirectBranch_MMR6 : PseudoIndirectBranchBase
1891 GPR32Opnd>,
1892 ISA_MICROMIPS32R6;
1893
18881894 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
18891895 (TAILCALL_MMR6 tglobaladdr:$dst)>, ISA_MICROMIPS32R6;
18901896
10011001 }
10021002
10031003 def TAILCALL_MM : TailCall, ISA_MIPS1_NOT_32R6_64R6;
1004
1005 def TAILCALLREG_MM : TailCallReg,
1006 ISA_MICROMIPS32_NOT_MIPS32R6;
1007
1008 def PseudoIndirectBranch_MM : PseudoIndirectBranchBase,
1009 ISA_MICROMIPS32_NOT_MIPS32R6;
10041010
10051011 let DecoderNamespace = "MicroMips" in {
10061012 def RDHWR_MM : MMRel, R6MMR6Rel, ReadHardware,
192192 def FeatureLongCalls : SubtargetFeature<"long-calls", "UseLongCalls", "true",
193193 "Disable use of the jal instruction">;
194194
195 def FeatureUseIndirectJumpsHazard : SubtargetFeature<"use-indirect-jump-hazard",
196 "UseIndirectJumpsHazard",
197 "true", "Use indirect jump"
198 " guards to prevent certain speculation based attacks">;
195199 //===----------------------------------------------------------------------===//
196200 // Mips processors supported.
197201 //===----------------------------------------------------------------------===//
10351035 (SELEQZ i32:$f, i32:$cond)>,
10361036 ISA_MIPS32R6;
10371037 }
1038
1039 // Pseudo instructions
1040 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
1041 hasExtraSrcRegAllocReq = 1, isCTI = 1, Defs = [AT] in {
1042 class TailCallRegR6 :
1043 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], II_JR>,
1044 PseudoInstExpansion<(JumpInst RT:$rt, RO:$rs)>;
1045 }
1046
1047 class PseudoIndirectBranchBaseR6
1048 RegisterOperand RO> :
1049 MipsPseudo<(outs), (ins RO:$rs), [(brind RO:$rs)],
1050 II_IndirectBranchPseudo>,
1051 PseudoInstExpansion<(JumpInst RT:$rt, RO:$rs)> {
1052 let isTerminator=1;
1053 let isBarrier=1;
1054 let hasDelaySlot = 1;
1055 let isBranch = 1;
1056 let isIndirectBranch = 1;
1057 bit isCTI = 1;
1058 }
1059
1060
1061 let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips,
1062 NoIndirectJumpGuards] in {
1063 def TAILCALLR6REG : TailCallRegR6, ISA_MIPS32R6;
1064 def PseudoIndirectBranchR6 : PseudoIndirectBranchBaseR6
1065 GPR32Opnd>,
1066 ISA_MIPS32R6;
1067 }
1068
1069 let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips,
1070 UseIndirectJumpsHazard] in {
1071 def TAILCALLHBR6REG : TailCallReg, ISA_MIPS32R6;
1072 def PseudoIndrectHazardBranchR6 : PseudoIndirectBranchBase
1073 GPR32Opnd>,
1074 ISA_MIPS32R6;
1075 }
1076
239239 def BGTZ64 : CBranchZero<"bgtz", brtarget, setgt, GPR64Opnd>, BGEZ_FM<7, 0>;
240240 def BLEZ64 : CBranchZero<"blez", brtarget, setle, GPR64Opnd>, BGEZ_FM<6, 0>;
241241 def BLTZ64 : CBranchZero<"bltz", brtarget, setlt, GPR64Opnd>, BGEZ_FM<1, 0>;
242 def JALR64Pseudo : JumpLinkRegPseudo;
243 }
244
245 def TAILCALLREG64 : TailCallReg;
246
242 let AdditionalPredicates = [NoIndirectJumpGuards] in
243 def JALR64Pseudo : JumpLinkRegPseudo;
244 }
245 let AdditionalPredicates = [NotInMicroMips],
246 DecoderNamespace = "Mips64" in {
247 def JR_HB64 : JR_HB_DESC, JR_HB_ENC, ISA_MIPS32_NOT_32R6_64R6;
248 def JALR_HB64 : JALR_HB_DESC, JALR_HB_ENC, ISA_MIPS32R2;
249 }
247250 def PseudoReturn64 : PseudoReturnBase;
248 def PseudoIndirectBranch64 : PseudoIndirectBranchBase;
251
252 let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips,
253 NoIndirectJumpGuards] in {
254 def TAILCALLREG64 : TailCallReg, ISA_MIPS3_NOT_32R6_64R6,
255 PTR_64;
256 def PseudoIndirectBranch64 : PseudoIndirectBranchBase,
257 ISA_MIPS3_NOT_32R6_64R6;
258 }
259
260 let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips,
261 UseIndirectJumpsHazard] in {
262 def TAILCALLREGHB64 : TailCallReg,
263 ISA_MIPS32R2_NOT_32R6_64R6, PTR_64;
264 def PseudoIndirectHazardBranch64 : PseudoIndirectBranchBase
265 GPR64Opnd>,
266 ISA_MIPS32R2_NOT_32R6_64R6;
267 }
249268
250269 /// Multiply and Divide Instructions.
251270 let AdditionalPredicates = [NotInMicroMips] in {
535554 ISA_MIPS3;
536555 }
537556
557
558 let AdditionalPredicates = [UseIndirectJumpsHazard] in
559 def JALRHB64Pseudo : JumpLinkRegPseudo;
560
538561 //===----------------------------------------------------------------------===//
539562 // Arbitrary patterns that map to one or more instructions
540563 //===----------------------------------------------------------------------===//
842865 def : MipsInstAlias<"dext $rt, $rs, $pos, $size",
843866 (DEXTU GPR64Opnd:$rt, GPR64Opnd:$rs, uimm5_plus32:$pos,
844867 uimm5_plus1:$size), 0>, ISA_MIPS64R2;
845
868 def : MipsInstAlias<"jalr.hb $rs", (JALR_HB64 RA_64, GPR64Opnd:$rs), 1>,
869 ISA_MIPS64;
846870 // Two operand (implicit 0 selector) versions:
847871 def : MipsInstAlias<"dmtc0 $rt, $rd",
848872 (DMTC0 COP0Opnd:$rd, GPR64Opnd:$rt, 0), 0>;
103103
104104 class LL64_R6_DESC : LL_R6_DESC_BASE<"ll", GPR32Opnd, mem_simm9, II_LL>;
105105 class SC64_R6_DESC : SC_R6_DESC_BASE<"sc", GPR32Opnd, II_SC>;
106
107 class JR_HB64_R6_DESC : JR_HB_DESC_BASE<"jr.hb", GPR64Opnd> {
108 bit isBranch = 1;
109 bit isIndirectBranch = 1;
110 bit hasDelaySlot = 1;
111 bit isTerminator=1;
112 bit isBarrier=1;
113 bit isCTI = 1;
114 InstrItinClass Itinerary = II_JR_HB;
115 }
106116 //===----------------------------------------------------------------------===//
107117 //
108118 // Instruction Definitions
135145 let DecoderNamespace = "Mips32r6_64r6_GP64" in {
136146 def SELEQZ64 : SELEQZ_ENC, SELEQZ64_DESC, ISA_MIPS32R6, GPR_64;
137147 def SELNEZ64 : SELNEZ_ENC, SELNEZ64_DESC, ISA_MIPS32R6, GPR_64;
148 def JR_HB64_R6 : JR_HB_R6_ENC, JR_HB64_R6_DESC, ISA_MIPS32R6;
138149 }
139150 let AdditionalPredicates = [NotInMicroMips],
140151 DecoderNamespace = "Mips32r6_64r6_PTR64" in {
276287 def : MipsPat<(select (i32 (seteq i32:$cond, immz)), immz, i64:$f),
277288 (SELNEZ64 i64:$f, (SLL64_32 i32:$cond))>,
278289 ISA_MIPS64R6;
290
291 // Pseudo instructions
292
293 let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips,
294 NoIndirectJumpGuards] in {
295 def TAILCALL64R6REG : TailCallRegR6, ISA_MIPS64R6;
296 def PseudoIndirectBranch64R6 : PseudoIndirectBranchBaseR6
297 GPR64Opnd>,
298 ISA_MIPS64R6;
299 }
300
301 let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips,
302 UseIndirectJumpsHazard] in {
303 def TAILCALLHB64R6REG : TailCallReg,
304 ISA_MIPS64R6;
305 def PseudoIndrectHazardBranch64R6 : PseudoIndirectBranchBase
306 GPR64Opnd>,
307 ISA_MIPS64R6;
308 }
5252
5353 class PseudoDSP pattern,
5454 InstrItinClass itin = IIPseudo>
55 : MipsPseudo, PredicateControl {
55 : MipsPseudo {
5656 let InsnPredicates = [HasDSP];
5757 }
5858
127127 // Mips Pseudo Instructions Format
128128 class MipsPseudo pattern,
129129 InstrItinClass itin = IIPseudo> :
130 MipsInst {
130 MipsInst, PredicateControl {
131131 let isCodeGenOnly = 1;
132132 let isPseudo = 1;
133133 }
135135 // Mips32/64 Pseudo Instruction Format
136136 class PseudoSE pattern,
137137 InstrItinClass itin = IIPseudo> :
138 MipsPseudo, PredicateControl {
138 MipsPseudo {
139139 let EncodingPredicates = [HasStdEnc];
140140 }
141141
297297 case Mips::JR:
298298 case Mips::PseudoReturn:
299299 case Mips::PseudoIndirectBranch:
300 case Mips::TAILCALLREG:
301300 canUseShortMicroMipsCTI = true;
302301 break;
303302 }
376375 // For MIPSR6, the instruction 'jic' can be used for these cases. Some
377376 // tools will accept 'jrc reg' as an alias for 'jic 0, $reg'.
378377 case Mips::JR:
378 case Mips::PseudoIndirectBranchR6:
379379 case Mips::PseudoReturn:
380 case Mips::PseudoIndirectBranch:
381 case Mips::TAILCALLREG:
380 case Mips::TAILCALLR6REG:
382381 if (canUseShortMicroMipsCTI)
383382 return Mips::JRC16_MM;
384383 return Mips::JIC;
385384 case Mips::JALRPseudo:
386385 return Mips::JIALC;
387386 case Mips::JR64:
387 case Mips::PseudoIndirectBranch64R6:
388388 case Mips::PseudoReturn64:
389 case Mips::PseudoIndirectBranch64:
390 case Mips::TAILCALLREG64:
389 case Mips::TAILCALL64R6REG:
391390 return Mips::JIC64;
392391 case Mips::JALR64Pseudo:
393392 return Mips::JIALC64;
616615 return verifyInsExtInstruction(MI, ErrInfo, 0, 32, 32, 64, 32, 64);
617616 case Mips::DEXTU:
618617 return verifyInsExtInstruction(MI, ErrInfo, 32, 64, 0, 32, 32, 64);
618 case Mips::TAILCALLREG:
619 case Mips::PseudoIndirectBranch:
620 case Mips::JR:
621 case Mips::JR64:
622 case Mips::JALR:
623 case Mips::JALR64:
624 case Mips::JALRPseudo:
625 if (!Subtarget.useIndirectJumpsHazard())
626 return true;
627
628 ErrInfo = "invalid instruction when using jump guards!";
629 return false;
619630 default:
620631 return true;
621632 }
243243 AssemblerPredicate<"!FeatureMadd4">;
244244 def HasMT : Predicate<"Subtarget->hasMT()">,
245245 AssemblerPredicate<"FeatureMT">;
246
246 def UseIndirectJumpsHazard : Predicate<"Subtarget->useIndirectJumpsHazard()">,
247 AssemblerPredicate<"FeatureUseIndirectJumpsHazard">;
248 def NoIndirectJumpGuards : Predicate<"!Subtarget->useIndirectJumpsHazard()">,
249 AssemblerPredicate<"!FeatureUseIndirectJumpsHazard">;
247250 //===----------------------------------------------------------------------===//
248251 // Mips GPR size adjectives.
249252 // They are mutually exclusive.
15391542 PseudoSE<(outs), (ins calltarget:$target), [], II_J>,
15401543 PseudoInstExpansion<(JumpInst Opnd:$target)>;
15411544
1542 class TailCallReg :
1543 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], II_JR>;
1545 class TailCallReg :
1546 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], II_JR>,
1547 PseudoInstExpansion<(JumpInst RO:$rs)>;
15441548 }
15451549
15461550 class BAL_BR_Pseudo :
20672071 AdditionalRequires<[NotInMicroMips]>;
20682072
20692073 def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>;
2070 let AdditionalPredicates = [NotInMicroMips] in {
2074 let AdditionalPredicates = [NotInMicroMips, NoIndirectJumpGuards] in {
20712075 def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
20722076 def JALRPseudo : JumpLinkRegPseudo;
20732077 }
20872091 let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips] in {
20882092 def TAILCALL : TailCall;
20892093 }
2090
2091 def TAILCALLREG : TailCallReg;
2094 let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips,
2095 NoIndirectJumpGuards] in
2096 def TAILCALLREG : TailCallReg, ISA_MIPS1_NOT_32R6_64R6;
20922097
20932098 // Indirect branches are matched as PseudoIndirectBranch/PseudoIndirectBranch64
20942099 // then are expanded to JR, JR64, JALR, or JALR64 depending on the ISA.
2095 class PseudoIndirectBranchBase<RegisterOperand RO> :
2100 class PseudoIndirectBranchBase<Instruction JumpInst, RegisterOperand RO> :
20962101 MipsPseudo<(outs), (ins RO:$rs), [(brind RO:$rs)],
2097 II_IndirectBranchPseudo> {
2102 II_IndirectBranchPseudo>,
2103 PseudoInstExpansion<(JumpInst RO:$rs)> {
20982104 let isTerminator=1;
20992105 let isBarrier=1;
21002106 let hasDelaySlot = 1;
21012107 let isBranch = 1;
21022108 let isIndirectBranch = 1;
21032109 bit isCTI = 1;
2104 let Predicates = [NotInMips16Mode];
2105 }
2106
2107 def PseudoIndirectBranch : PseudoIndirectBranchBase;
2110 }
2111
2112 let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips,
2113 NoIndirectJumpGuards] in
2114 def PseudoIndirectBranch : PseudoIndirectBranchBase,
2115 ISA_MIPS1_NOT_32R6_64R6;
21082116
21092117 // Return instructions are matched as a RetRA instruction, then are expanded
21102118 // into PseudoReturn/PseudoReturn64 after register allocation. Finally,
22772285 list Pattern = [];
22782286 }
22792287
2280 class JR_HB_DESC : InstSE<(outs), (ins), "", [], II_JR_HB, FrmJ>,
2281 JR_HB_DESC_BASE<"jr.hb", GPR32Opnd> {
2288 class JR_HB_DESC :
2289 InstSE<(outs), (ins), "", [], II_JR_HB, FrmJ>, JR_HB_DESC_BASE<"jr.hb", RO> {
22822290 let isBranch=1;
22832291 let isIndirectBranch=1;
22842292 let hasDelaySlot=1;
22872295 bit isCTI = 1;
22882296 }
22892297
2290 class JALR_HB_DESC : InstSE<(outs), (ins), "", [], II_JALR_HB, FrmJ>,
2291 JALR_HB_DESC_BASE<"jalr.hb", GPR32Opnd> {
2298 class JALR_HB_DESC :
2299 InstSE<(outs), (ins), "", [], II_JALR_HB, FrmJ>, JALR_HB_DESC_BASE<"jalr.hb",
2300 RO> {
22922301 let isIndirectBranch=1;
22932302 let hasDelaySlot=1;
22942303 bit isCTI = 1;
22972306 class JR_HB_ENC : JR_HB_FM<8>;
22982307 class JALR_HB_ENC : JALR_HB_FM<9>;
22992308
2300 def JR_HB : JR_HB_DESC, JR_HB_ENC, ISA_MIPS32_NOT_32R6_64R6;
2301 def JALR_HB : JALR_HB_DESC, JALR_HB_ENC, ISA_MIPS32;
2309 def JR_HB : JR_HB_DESC, JR_HB_ENC, ISA_MIPS32R2_NOT_32R6_64R6;
2310 def JALR_HB : JALR_HB_DESC, JALR_HB_ENC, ISA_MIPS32;
2311
2312 let AdditionalPredicates = [NotInMicroMips, UseIndirectJumpsHazard] in
2313 def JALRHBPseudo : JumpLinkRegPseudo;
2314
2315
2316 let AdditionalPredicates = [NotInMips16Mode, NotInMicroMips,
2317 UseIndirectJumpsHazard] in {
2318 def TAILCALLREGHB : TailCallReg, ISA_MIPS32_NOT_32R6_64R6;
2319 def PseudoIndirectHazardBranch : PseudoIndirectBranchBase,
2320 ISA_MIPS32R2_NOT_32R6_64R6;
2321 }
23022322
23032323 class TLB :
23042324 InstSE<(outs), (ins), asmstr, [], itin, FrmOther, asmstr>;
24322452 let Predicates = [NotInMicroMips] in {
24332453 def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
24342454 }
2435 def : MipsInstAlias<"jalr.hb $rs", (JALR_HB RA, GPR32Opnd:$rs), 1>, ISA_MIPS32;
2455 def : MipsInstAlias<"jalr.hb $rs", (JALR_HB RA, GPR32Opnd:$rs), 1>,
2456 ISA_MIPS32;
24362457 def : MipsInstAlias<"neg $rt, $rs",
24372458 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
24382459 def : MipsInstAlias<"neg $rt",
370370
371371 // In NaCl, modifying the sp is not allowed in branch delay slot.
372372 // For MIPS32R6, we can skip using a delay slot branch.
373 if (Subtarget.isTargetNaCl() || Subtarget.hasMips32r6())
373 if (Subtarget.isTargetNaCl() ||
374 (Subtarget.hasMips32r6() && !Subtarget.useIndirectJumpsHazard()))
374375 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
375376 .addReg(Mips::SP).addImm(8);
376377
377 if (Subtarget.hasMips32r6()) {
378 if (Subtarget.hasMips32r6() && !Subtarget.useIndirectJumpsHazard()) {
378379 const unsigned JICOp =
379380 Subtarget.inMicroMipsMode() ? Mips::JIC_MMR6 : Mips::JIC;
380381 BuildMI(*BalTgtMBB, Pos, DL, TII->get(JICOp))
382383 .addImm(0);
383384
384385 } else {
385 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::JR)).addReg(Mips::AT);
386 unsigned JROp =
387 Subtarget.useIndirectJumpsHazard()
388 ? (Subtarget.hasMips32r6() ? Mips::JR_HB_R6 : Mips::JR_HB)
389 : Mips::JR;
390 BuildMI(*BalTgtMBB, Pos, DL, TII->get(JROp)).addReg(Mips::AT);
386391
387392 if (Subtarget.isTargetNaCl()) {
388393 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::NOP));
474479 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LD), Mips::RA_64)
475480 .addReg(Mips::SP_64).addImm(0);
476481
477 if (Subtarget.hasMips64r6()) {
482 if (Subtarget.hasMips64r6() && !Subtarget.useIndirectJumpsHazard()) {
478483 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::DADDiu), Mips::SP_64)
479484 .addReg(Mips::SP_64)
480485 .addImm(16);
482487 .addReg(Mips::AT_64)
483488 .addImm(0);
484489 } else {
485 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::JR64)).addReg(Mips::AT_64);
490 unsigned JROp =
491 Subtarget.useIndirectJumpsHazard()
492 ? (Subtarget.hasMips32r6() ? Mips::JR_HB64_R6 : Mips::JR_HB64)
493 : Mips::JR64;
494 BuildMI(*BalTgtMBB, Pos, DL, TII->get(JROp)).addReg(Mips::AT_64);
486495 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::DADDiu), Mips::SP_64)
487496 .addReg(Mips::SP_64)
488497 .addImm(16);
7171 HasDSPR2(false), HasDSPR3(false), AllowMixed16_32(Mixed16_32 | Mips_Os16),
7272 Os16(Mips_Os16), HasMSA(false), UseTCCInDIV(false), HasSym32(false),
7373 HasEVA(false), DisableMadd4(false), HasMT(false),
74 StackAlignOverride(StackAlignOverride), TM(TM), TargetTriple(TT),
75 TSInfo(), InstrInfo(MipsInstrInfo::create(
76 initializeSubtargetDependencies(CPU, FS, TM))),
74 UseIndirectJumpsHazard(false), StackAlignOverride(StackAlignOverride),
75 TM(TM), TargetTriple(TT), TSInfo(),
76 InstrInfo(
77 MipsInstrInfo::create(initializeSubtargetDependencies(CPU, FS, TM))),
7778 FrameLowering(MipsFrameLowering::create(*this)),
7879 TLInfo(MipsTargetLowering::create(TM, *this)) {
7980
106107 if (hasMips64r6() && InMicroMipsMode)
107108 report_fatal_error("microMIPS64R6 is not supported", false);
108109
110
111 if (UseIndirectJumpsHazard) {
112 if (InMicroMipsMode)
113 report_fatal_error(
114 "cannot combine indirect jumps with hazard barriers and microMIPS");
115 if (!hasMips32r2())
116 report_fatal_error(
117 "indirect jumps with hazard barriers requires MIPS32R2 or later");
118 }
109119 if (hasMips32r6()) {
110120 StringRef ISA = hasMips64r6() ? "MIPS64r6" : "MIPS32r6";
111121
150150
151151 // HasMT -- support MT ASE.
152152 bool HasMT;
153
154 // Use hazard variants of the jump register instructions for indirect
155 // function calls and jump tables.
156 bool UseIndirectJumpsHazard;
153157
154158 // Disable use of the `jal` instruction.
155159 bool UseLongCalls = false;
271275 bool disableMadd4() const { return DisableMadd4; }
272276 bool hasEVA() const { return HasEVA; }
273277 bool hasMT() const { return HasMT; }
278 bool useIndirectJumpsHazard() const {
279 return UseIndirectJumpsHazard && hasMips32r2();
280 }
274281 bool useSmallSection() const { return UseSmallSection; }
275282
276283 bool hasStandardEncoding() const { return !inMips16Mode(); }
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc < %s -mtriple=mips-mti-linux-gnu -relocation-model=static \
2 ; RUN: -mips-tail-calls=1 -mcpu=mips32r2 -mattr=+use-indirect-jump-hazard \
3 ; RUN: -verify-machineinstrs | FileCheck %s --check-prefix=MIPS32R2
4 ; RUN: llc < %s -mtriple=mips-img-linux-gnu -relocation-model=static \
5 ; RUN: -mips-tail-calls=1 -mcpu=mips32r6 -mattr=+use-indirect-jump-hazard \
6 ; RUN: -verify-machineinstrs | FileCheck %s --check-prefix=MIPS32R6
7 ; RUN: llc < %s -mtriple=mips64-mti-linux-gnu -relocation-model=static \
8 ; RUN: -mips-tail-calls=1 -mcpu=mips64r2 -mattr=+use-indirect-jump-hazard \
9 ; RUN: -verify-machineinstrs | FileCheck %s --check-prefix=MIPS64R2
10 ; RUN: llc < %s -mtriple=mips64-img-linux-gnu -relocation-model=static \
11 ; RUN: -mips-tail-calls=1 -mcpu=mips64r6 -mattr=+use-indirect-jump-hazard \
12 ; RUN: -verify-machineinstrs | FileCheck %s --check-prefix=MIPS64R6
13
14 ; RUN: llc < %s -mtriple=mips-mti-linux-gnu -relocation-model=pic \
15 ; RUN: -mips-tail-calls=1 -mcpu=mips32r2 -mattr=+use-indirect-jump-hazard \
16 ; RUN: -verify-machineinstrs | FileCheck %s --check-prefix=PIC-MIPS32R2
17 ; RUN: llc < %s -mtriple=mips-img-linux-gnu -relocation-model=pic \
18 ; RUN: -mips-tail-calls=1 -mcpu=mips32r6 -mattr=+use-indirect-jump-hazard \
19 ; RUN: -verify-machineinstrs | FileCheck %s --check-prefix=PIC-MIPS32R6
20 ; RUN: llc < %s -mtriple=mips64-mti-linux-gnu -relocation-model=pic \
21 ; RUN: -mips-tail-calls=1 -mcpu=mips64r2 -mattr=+use-indirect-jump-hazard \
22 ; RUN: -verify-machineinstrs | FileCheck %s --check-prefix=PIC-MIPS64R2
23 ; RUN: llc < %s -mtriple=mips64-img-linux-gnu -relocation-model=pic \
24 ; RUN: -mips-tail-calls=1 -mcpu=mips64r6 -mattr=+use-indirect-jump-hazard \
25 ; RUN: -verify-machineinstrs | FileCheck %s --check-prefix=PIC-MIPS64R6
26
27 define void @fooNonTail(void (i32)* nocapture %f1) nounwind {
28 ; MIPS32R2-LABEL: fooNonTail:
29 ; MIPS32R2: # %bb.0: # %entry
30 ; MIPS32R2-NEXT: addiu $sp, $sp, -24
31 ; MIPS32R2-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
32 ; MIPS32R2-NEXT: move $1, $4
33 ; MIPS32R2-NEXT: move $25, $1
34 ; MIPS32R2-NEXT: jalr.hb $25
35 ; MIPS32R2-NEXT: addiu $4, $zero, 13
36 ; MIPS32R2-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
37 ; MIPS32R2-NEXT: jr $ra
38 ; MIPS32R2-NEXT: addiu $sp, $sp, 24
39 ;
40 ; MIPS32R6-LABEL: fooNonTail:
41 ; MIPS32R6: # %bb.0: # %entry
42 ; MIPS32R6-NEXT: addiu $sp, $sp, -24
43 ; MIPS32R6-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
44 ; MIPS32R6-NEXT: move $1, $4
45 ; MIPS32R6-NEXT: move $25, $1
46 ; MIPS32R6-NEXT: jalr.hb $25
47 ; MIPS32R6-NEXT: addiu $4, $zero, 13
48 ; MIPS32R6-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
49 ; MIPS32R6-NEXT: jr $ra
50 ; MIPS32R6-NEXT: addiu $sp, $sp, 24
51 ;
52 ; MIPS64R2-LABEL: fooNonTail:
53 ; MIPS64R2: # %bb.0: # %entry
54 ; MIPS64R2-NEXT: daddiu $sp, $sp, -16
55 ; MIPS64R2-NEXT: sd $ra, 8($sp) # 8-byte Folded Spill
56 ; MIPS64R2-NEXT: move $1, $4
57 ; MIPS64R2-NEXT: move $25, $1
58 ; MIPS64R2-NEXT: jalr.hb $25
59 ; MIPS64R2-NEXT: daddiu $4, $zero, 13
60 ; MIPS64R2-NEXT: ld $ra, 8($sp) # 8-byte Folded Reload
61 ; MIPS64R2-NEXT: jr $ra
62 ; MIPS64R2-NEXT: daddiu $sp, $sp, 16
63 ;
64 ; MIPS64R6-LABEL: fooNonTail:
65 ; MIPS64R6: # %bb.0: # %entry
66 ; MIPS64R6-NEXT: daddiu $sp, $sp, -16
67 ; MIPS64R6-NEXT: sd $ra, 8($sp) # 8-byte Folded Spill
68 ; MIPS64R6-NEXT: move $1, $4
69 ; MIPS64R6-NEXT: move $25, $1
70 ; MIPS64R6-NEXT: jalr.hb $25
71 ; MIPS64R6-NEXT: daddiu $4, $zero, 13
72 ; MIPS64R6-NEXT: ld $ra, 8($sp) # 8-byte Folded Reload
73 ; MIPS64R6-NEXT: jr $ra
74 ; MIPS64R6-NEXT: daddiu $sp, $sp, 16
75 ;
76 ; PIC-MIPS32R2-LABEL: fooNonTail:
77 ; PIC-MIPS32R2: # %bb.0: # %entry
78 ; PIC-MIPS32R2-NEXT: addiu $sp, $sp, -24
79 ; PIC-MIPS32R2-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
80 ; PIC-MIPS32R2-NEXT: move $1, $4
81 ; PIC-MIPS32R2-NEXT: move $25, $1
82 ; PIC-MIPS32R2-NEXT: jalr.hb $25
83 ; PIC-MIPS32R2-NEXT: addiu $4, $zero, 13
84 ; PIC-MIPS32R2-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
85 ; PIC-MIPS32R2-NEXT: jr $ra
86 ; PIC-MIPS32R2-NEXT: addiu $sp, $sp, 24
87 ;
88 ; PIC-MIPS32R6-LABEL: fooNonTail:
89 ; PIC-MIPS32R6: # %bb.0: # %entry
90 ; PIC-MIPS32R6-NEXT: addiu $sp, $sp, -24
91 ; PIC-MIPS32R6-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
92 ; PIC-MIPS32R6-NEXT: move $1, $4
93 ; PIC-MIPS32R6-NEXT: move $25, $1
94 ; PIC-MIPS32R6-NEXT: jalr.hb $25
95 ; PIC-MIPS32R6-NEXT: addiu $4, $zero, 13
96 ; PIC-MIPS32R6-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
97 ; PIC-MIPS32R6-NEXT: jr $ra
98 ; PIC-MIPS32R6-NEXT: addiu $sp, $sp, 24
99 ;
100 ; PIC-MIPS64R2-LABEL: fooNonTail:
101 ; PIC-MIPS64R2: # %bb.0: # %entry
102 ; PIC-MIPS64R2-NEXT: daddiu $sp, $sp, -16
103 ; PIC-MIPS64R2-NEXT: sd $ra, 8($sp) # 8-byte Folded Spill
104 ; PIC-MIPS64R2-NEXT: move $1, $4
105 ; PIC-MIPS64R2-NEXT: move $25, $1
106 ; PIC-MIPS64R2-NEXT: jalr.hb $25
107 ; PIC-MIPS64R2-NEXT: daddiu $4, $zero, 13
108 ; PIC-MIPS64R2-NEXT: ld $ra, 8($sp) # 8-byte Folded Reload
109 ; PIC-MIPS64R2-NEXT: jr $ra
110 ; PIC-MIPS64R2-NEXT: daddiu $sp, $sp, 16
111 ;
112 ; PIC-MIPS64R6-LABEL: fooNonTail:
113 ; PIC-MIPS64R6: # %bb.0: # %entry
114 ; PIC-MIPS64R6-NEXT: daddiu $sp, $sp, -16
115 ; PIC-MIPS64R6-NEXT: sd $ra, 8($sp) # 8-byte Folded Spill
116 ; PIC-MIPS64R6-NEXT: move $1, $4
117 ; PIC-MIPS64R6-NEXT: move $25, $1
118 ; PIC-MIPS64R6-NEXT: jalr.hb $25
119 ; PIC-MIPS64R6-NEXT: daddiu $4, $zero, 13
120 ; PIC-MIPS64R6-NEXT: ld $ra, 8($sp) # 8-byte Folded Reload
121 ; PIC-MIPS64R6-NEXT: jr $ra
122 ; PIC-MIPS64R6-NEXT: daddiu $sp, $sp, 16
123 entry:
124 call void %f1(i32 13) nounwind
125 ret void
126 }
127
128 define i32 @fooTail(i32 (i32)* nocapture %f1) nounwind {
129 ; MIPS32R2-LABEL: fooTail:
130 ; MIPS32R2: # %bb.0: # %entry
131 ; MIPS32R2-NEXT: move $1, $4
132 ; MIPS32R2-NEXT: move $25, $1
133 ; MIPS32R2-NEXT: jr.hb $25
134 ; MIPS32R2-NEXT: addiu $4, $zero, 14
135 ;
136 ; MIPS32R6-LABEL: fooTail:
137 ; MIPS32R6: # %bb.0: # %entry
138 ; MIPS32R6-NEXT: move $1, $4
139 ; MIPS32R6-NEXT: move $25, $1
140 ; MIPS32R6-NEXT: jr.hb $25
141 ; MIPS32R6-NEXT: addiu $4, $zero, 14
142 ;
143 ; MIPS64R2-LABEL: fooTail:
144 ; MIPS64R2: # %bb.0: # %entry
145 ; MIPS64R2-NEXT: move $1, $4
146 ; MIPS64R2-NEXT: move $25, $1
147 ; MIPS64R2-NEXT: jr.hb $25
148 ; MIPS64R2-NEXT: daddiu $4, $zero, 14
149 ;
150 ; MIPS64R6-LABEL: fooTail:
151 ; MIPS64R6: # %bb.0: # %entry
152 ; MIPS64R6-NEXT: move $1, $4
153 ; MIPS64R6-NEXT: move $25, $1
154 ; MIPS64R6-NEXT: jr.hb $25
155 ; MIPS64R6-NEXT: daddiu $4, $zero, 14
156 ;
157 ; PIC-MIPS32R2-LABEL: fooTail:
158 ; PIC-MIPS32R2: # %bb.0: # %entry
159 ; PIC-MIPS32R2-NEXT: move $1, $4
160 ; PIC-MIPS32R2-NEXT: move $25, $1
161 ; PIC-MIPS32R2-NEXT: jr.hb $25
162 ; PIC-MIPS32R2-NEXT: addiu $4, $zero, 14
163 ;
164 ; PIC-MIPS32R6-LABEL: fooTail:
165 ; PIC-MIPS32R6: # %bb.0: # %entry
166 ; PIC-MIPS32R6-NEXT: move $1, $4
167 ; PIC-MIPS32R6-NEXT: move $25, $1
168 ; PIC-MIPS32R6-NEXT: jr.hb $25
169 ; PIC-MIPS32R6-NEXT: addiu $4, $zero, 14
170 ;
171 ; PIC-MIPS64R2-LABEL: fooTail:
172 ; PIC-MIPS64R2: # %bb.0: # %entry
173 ; PIC-MIPS64R2-NEXT: move $1, $4
174 ; PIC-MIPS64R2-NEXT: move $25, $1
175 ; PIC-MIPS64R2-NEXT: jr.hb $25
176 ; PIC-MIPS64R2-NEXT: daddiu $4, $zero, 14
177 ;
178 ; PIC-MIPS64R6-LABEL: fooTail:
179 ; PIC-MIPS64R6: # %bb.0: # %entry
180 ; PIC-MIPS64R6-NEXT: move $1, $4
181 ; PIC-MIPS64R6-NEXT: move $25, $1
182 ; PIC-MIPS64R6-NEXT: jr.hb $25
183 ; PIC-MIPS64R6-NEXT: daddiu $4, $zero, 14
184 entry:
185 %0 = tail call i32 %f1(i32 14) nounwind
186 ret i32 %0
187 }
0 # RUN: not llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 %s \
1 # RUN: -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
2 # RUN: -verify-machineinstrs -mattr=+use-indirect-jump-hazard -o - 2>&1 \
3 # RUN: | FileCheck %s
4
5 # Test that calls are checked when using indirect jumps guards (hazard variant).
6
7 # CHECK: Bad machine code: invalid instruction when using jump guards!
8 --- |
9 define i32 @fooTail(i32 (i32)* nocapture %f1) {
10 entry:
11 %0 = tail call i32 %f1(i32 14)
12 ret i32 %0
13 }
14 ...
15 ---
16 name: fooTail
17 alignment: 2
18 exposesReturnsTwice: false
19 legalized: false
20 regBankSelected: false
21 selected: false
22 tracksRegLiveness: true
23 registers:
24 - { id: 0, class: gpr32, preferred-register: '' }
25 - { id: 1, class: gpr32, preferred-register: '' }
26 liveins:
27 - { reg: '%a0', virtual-reg: '%0' }
28 frameInfo:
29 isFrameAddressTaken: false
30 isReturnAddressTaken: false
31 hasStackMap: false
32 hasPatchPoint: false
33 stackSize: 0
34 offsetAdjustment: 0
35 maxAlignment: 1
36 adjustsStack: false
37 hasCalls: false
38 stackProtector: ''
39 maxCallFrameSize: 4294967295
40 hasOpaqueSPAdjustment: false
41 hasVAStart: false
42 hasMustTailInVarArgFunc: false
43 savePoint: ''
44 restorePoint: ''
45 fixedStack:
46 stack:
47 constants:
48 body: |
49 bb.0.entry:
50 liveins: %a0
51
52 %0:gpr32 = COPY %a0
53 %1:gpr32 = ADDiu $zero, 14
54 %a0 = COPY %1
55 TAILCALLREG %0, csr_o32, implicit-def dead %at, implicit %a0
56
57 ...
0 # RUN: not llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 %s \
1 # RUN: -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
2 # RUN: -verify-machineinstrs -mattr=+use-indirect-jump-hazard -o - 2>&1 \
3 # RUN: | FileCheck %s
4
5 # That that tail calls are checked when using indirect jump guards (hazard variant).
6
7 # CHECK: Bad machine code: invalid instruction when using jump guards!
8 --- |
9 define i32 @fooTail(i32 (i32)* nocapture %f1) {
10 entry:
11 %0 = tail call i32 %f1(i32 14)
12 ret i32 %0
13 }
14
15 ...
16 ---
17 name: fooTail
18 alignment: 2
19 exposesReturnsTwice: false
20 legalized: false
21 regBankSelected: false
22 selected: false
23 tracksRegLiveness: true
24 registers:
25 - { id: 0, class: gpr32, preferred-register: '' }
26 - { id: 1, class: gpr32, preferred-register: '' }
27 liveins:
28 - { reg: '%a0', virtual-reg: '%0' }
29 frameInfo:
30 isFrameAddressTaken: false
31 isReturnAddressTaken: false
32 hasStackMap: false
33 hasPatchPoint: false
34 stackSize: 0
35 offsetAdjustment: 0
36 maxAlignment: 1
37 adjustsStack: false
38 hasCalls: false
39 stackProtector: ''
40 maxCallFrameSize: 4294967295
41 hasOpaqueSPAdjustment: false
42 hasVAStart: false
43 hasMustTailInVarArgFunc: false
44 savePoint: ''
45 restorePoint: ''
46 fixedStack:
47 stack:
48 constants:
49 body: |
50 bb.0.entry:
51 liveins: %a0
52
53 %0:gpr32 = COPY %a0
54 %1:gpr32 = ADDiu $zero, 14
55 %a0 = COPY %1
56 TAILCALLREG %0, csr_o32, implicit-def dead %at, implicit %a0
57
58 ...
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc < %s -mtriple=mips-mti-linux-gnu -relocation-model=static \
2 ; RUN: -mips-tail-calls=1 -mcpu=mips32r2 -mattr=+use-indirect-jump-hazard \
3 ; RUN: -verify-machineinstrs | FileCheck %s --check-prefix=MIPS32R2
4 ; RUN: llc < %s -mtriple=mips-img-linux-gnu -relocation-model=static \
5 ; RUN: -mips-tail-calls=1 -mcpu=mips32r6 -mattr=+use-indirect-jump-hazard \
6 ; RUN: -verify-machineinstrs | FileCheck %s --check-prefix=MIPS32R6
7 ; RUN: llc < %s -mtriple=mips64-mti-linux-gnu -relocation-model=static \
8 ; RUN: -mips-tail-calls=1 -mcpu=mips64r2 -mattr=+use-indirect-jump-hazard \
9 ; RUN: -verify-machineinstrs | FileCheck %s --check-prefix=MIPS64R2
10 ; RUN: llc < %s -mtriple=mips64-img-linux-gnu -relocation-model=static \
11 ; RUN: -mips-tail-calls=1 -mcpu=mips64r6 -mattr=+use-indirect-jump-hazard \
12 ; RUN: -verify-machineinstrs | FileCheck %s --check-prefix=MIPS64R6
13
14 ; RUN: llc < %s -mtriple=mips-mti-linux-gnu -relocation-model=pic \
15 ; RUN: -mips-tail-calls=1 -mcpu=mips32r2 -mattr=+use-indirect-jump-hazard \
16 ; RUN: -verify-machineinstrs | FileCheck %s --check-prefix=PIC-MIPS32R2
17 ; RUN: llc < %s -mtriple=mips-img-linux-gnu -relocation-model=pic \
18 ; RUN: -mips-tail-calls=1 -mcpu=mips32r6 -mattr=+use-indirect-jump-hazard \
19 ; RUN: -verify-machineinstrs | FileCheck %s --check-prefix=PIC-MIPS32R6
20 ; RUN: llc < %s -mtriple=mips64-mti-linux-gnu -relocation-model=pic \
21 ; RUN: -mips-tail-calls=1 -mcpu=mips64r2 -mattr=+use-indirect-jump-hazard \
22 ; RUN: -verify-machineinstrs | FileCheck %s --check-prefix=PIC-MIPS64R2
23 ; RUN: llc < %s -mtriple=mips64-img-linux-gnu -relocation-model=pic \
24 ; RUN: -mips-tail-calls=1 -mcpu=mips64r6 -mattr=+use-indirect-jump-hazard \
25 ; RUN: -verify-machineinstrs | FileCheck %s --check-prefix=PIC-MIPS64R6
26
27 @.str = private unnamed_addr constant [2 x i8] c"A\00", align 1
28 @.str.1 = private unnamed_addr constant [2 x i8] c"B\00", align 1
29 @.str.2 = private unnamed_addr constant [2 x i8] c"C\00", align 1
30 @.str.3 = private unnamed_addr constant [2 x i8] c"D\00", align 1
31 @.str.4 = private unnamed_addr constant [2 x i8] c"E\00", align 1
32 @.str.5 = private unnamed_addr constant [2 x i8] c"F\00", align 1
33 @.str.6 = private unnamed_addr constant [2 x i8] c"G\00", align 1
34 @.str.7 = private unnamed_addr constant [1 x i8] zeroinitializer, align 1
35
36 define i8* @_Z3fooi(i32 signext %Letter) {
37 ; MIPS32R2-LABEL: _Z3fooi:
38 ; MIPS32R2: # %bb.0: # %entry
39 ; MIPS32R2-NEXT: addiu $sp, $sp, -16
40 ; MIPS32R2-NEXT: .cfi_def_cfa_offset 16
41 ; MIPS32R2-NEXT: sltiu $1, $4, 7
42 ; MIPS32R2-NEXT: beqz $1, $BB0_3
43 ; MIPS32R2-NEXT: sw $4, 4($sp)
44 ; MIPS32R2-NEXT: $BB0_1: # %entry
45 ; MIPS32R2-NEXT: sll $1, $4, 2
46 ; MIPS32R2-NEXT: lui $2, %hi($JTI0_0)
47 ; MIPS32R2-NEXT: addu $1, $1, $2
48 ; MIPS32R2-NEXT: lw $1, %lo($JTI0_0)($1)
49 ; MIPS32R2-NEXT: jr.hb $1
50 ; MIPS32R2-NEXT: nop
51 ; MIPS32R2-NEXT: $BB0_2: # %sw.bb
52 ; MIPS32R2-NEXT: lui $1, %hi($.str)
53 ; MIPS32R2-NEXT: addiu $1, $1, %lo($.str)
54 ; MIPS32R2-NEXT: j $BB0_10
55 ; MIPS32R2-NEXT: sw $1, 8($sp)
56 ; MIPS32R2-NEXT: $BB0_3: # %sw.epilog
57 ; MIPS32R2-NEXT: lui $1, %hi($.str.7)
58 ; MIPS32R2-NEXT: addiu $1, $1, %lo($.str.7)
59 ; MIPS32R2-NEXT: j $BB0_10
60 ; MIPS32R2-NEXT: sw $1, 8($sp)
61 ; MIPS32R2-NEXT: $BB0_4: # %sw.bb1
62 ; MIPS32R2-NEXT: lui $1, %hi($.str.1)
63 ; MIPS32R2-NEXT: addiu $1, $1, %lo($.str.1)
64 ; MIPS32R2-NEXT: j $BB0_10
65 ; MIPS32R2-NEXT: sw $1, 8($sp)
66 ; MIPS32R2-NEXT: $BB0_5: # %sw.bb2
67 ; MIPS32R2-NEXT: lui $1, %hi($.str.2)
68 ; MIPS32R2-NEXT: addiu $1, $1, %lo($.str.2)
69 ; MIPS32R2-NEXT: j $BB0_10
70 ; MIPS32R2-NEXT: sw $1, 8($sp)
71 ; MIPS32R2-NEXT: $BB0_6: # %sw.bb3
72 ; MIPS32R2-NEXT: lui $1, %hi($.str.3)
73 ; MIPS32R2-NEXT: addiu $1, $1, %lo($.str.3)
74 ; MIPS32R2-NEXT: j $BB0_10
75 ; MIPS32R2-NEXT: sw $1, 8($sp)
76 ; MIPS32R2-NEXT: $BB0_7: # %sw.bb4
77 ; MIPS32R2-NEXT: lui $1, %hi($.str.4)
78 ; MIPS32R2-NEXT: addiu $1, $1, %lo($.str.4)
79 ; MIPS32R2-NEXT: j $BB0_10
80 ; MIPS32R2-NEXT: sw $1, 8($sp)
81 ; MIPS32R2-NEXT: $BB0_8: # %sw.bb5
82 ; MIPS32R2-NEXT: lui $1, %hi($.str.5)
83 ; MIPS32R2-NEXT: addiu $1, $1, %lo($.str.5)
84 ; MIPS32R2-NEXT: j $BB0_10
85 ; MIPS32R2-NEXT: sw $1, 8($sp)
86 ; MIPS32R2-NEXT: $BB0_9: # %sw.bb6
87 ; MIPS32R2-NEXT: lui $1, %hi($.str.6)
88 ; MIPS32R2-NEXT: addiu $1, $1, %lo($.str.6)
89 ; MIPS32R2-NEXT: sw $1, 8($sp)
90 ; MIPS32R2-NEXT: $BB0_10: # %return
91 ; MIPS32R2-NEXT: lw $2, 8($sp)
92 ; MIPS32R2-NEXT: jr $ra
93 ; MIPS32R2-NEXT: addiu $sp, $sp, 16
94 ;
95 ; MIPS32R6-LABEL: _Z3fooi:
96 ; MIPS32R6: # %bb.0: # %entry
97 ; MIPS32R6-NEXT: addiu $sp, $sp, -16
98 ; MIPS32R6-NEXT: .cfi_def_cfa_offset 16
99 ; MIPS32R6-NEXT: sltiu $1, $4, 7
100 ; MIPS32R6-NEXT: beqz $1, $BB0_3
101 ; MIPS32R6-NEXT: sw $4, 4($sp)
102 ; MIPS32R6-NEXT: $BB0_1: # %entry
103 ; MIPS32R6-NEXT: sll $1, $4, 2
104 ; MIPS32R6-NEXT: lui $2, %hi($JTI0_0)
105 ; MIPS32R6-NEXT: addu $1, $1, $2
106 ; MIPS32R6-NEXT: lw $1, %lo($JTI0_0)($1)
107 ; MIPS32R6-NEXT: jr.hb $1
108 ; MIPS32R6-NEXT: nop
109 ; MIPS32R6-NEXT: $BB0_2: # %sw.bb
110 ; MIPS32R6-NEXT: lui $1, %hi($.str)
111 ; MIPS32R6-NEXT: addiu $1, $1, %lo($.str)
112 ; MIPS32R6-NEXT: j $BB0_10
113 ; MIPS32R6-NEXT: sw $1, 8($sp)
114 ; MIPS32R6-NEXT: $BB0_3: # %sw.epilog
115 ; MIPS32R6-NEXT: lui $1, %hi($.str.7)
116 ; MIPS32R6-NEXT: addiu $1, $1, %lo($.str.7)
117 ; MIPS32R6-NEXT: j $BB0_10
118 ; MIPS32R6-NEXT: sw $1, 8($sp)
119 ; MIPS32R6-NEXT: $BB0_4: # %sw.bb1
120 ; MIPS32R6-NEXT: lui $1, %hi($.str.1)
121 ; MIPS32R6-NEXT: addiu $1, $1, %lo($.str.1)
122 ; MIPS32R6-NEXT: j $BB0_10
123 ; MIPS32R6-NEXT: sw $1, 8($sp)
124 ; MIPS32R6-NEXT: $BB0_5: # %sw.bb2
125 ; MIPS32R6-NEXT: lui $1, %hi($.str.2)
126 ; MIPS32R6-NEXT: addiu $1, $1, %lo($.str.2)
127 ; MIPS32R6-NEXT: j $BB0_10
128 ; MIPS32R6-NEXT: sw $1, 8($sp)
129 ; MIPS32R6-NEXT: $BB0_6: # %sw.bb3
130 ; MIPS32R6-NEXT: lui $1, %hi($.str.3)
131 ; MIPS32R6-NEXT: addiu $1, $1, %lo($.str.3)
132 ; MIPS32R6-NEXT: j $BB0_10
133 ; MIPS32R6-NEXT: sw $1, 8($sp)
134 ; MIPS32R6-NEXT: $BB0_7: # %sw.bb4
135 ; MIPS32R6-NEXT: lui $1, %hi($.str.4)
136 ; MIPS32R6-NEXT: addiu $1, $1, %lo($.str.4)
137 ; MIPS32R6-NEXT: j $BB0_10
138 ; MIPS32R6-NEXT: sw $1, 8($sp)
139 ; MIPS32R6-NEXT: $BB0_8: # %sw.bb5
140 ; MIPS32R6-NEXT: lui $1, %hi($.str.5)
141 ; MIPS32R6-NEXT: addiu $1, $1, %lo($.str.5)
142 ; MIPS32R6-NEXT: j $BB0_10
143 ; MIPS32R6-NEXT: sw $1, 8($sp)
144 ; MIPS32R6-NEXT: $BB0_9: # %sw.bb6
145 ; MIPS32R6-NEXT: lui $1, %hi($.str.6)
146 ; MIPS32R6-NEXT: addiu $1, $1, %lo($.str.6)
147 ; MIPS32R6-NEXT: sw $1, 8($sp)
148 ; MIPS32R6-NEXT: $BB0_10: # %return
149 ; MIPS32R6-NEXT: lw $2, 8($sp)
150 ; MIPS32R6-NEXT: jr $ra
151 ; MIPS32R6-NEXT: addiu $sp, $sp, 16
152 ;
153 ; MIPS64R2-LABEL: _Z3fooi:
154 ; MIPS64R2: # %bb.0: # %entry
155 ; MIPS64R2-NEXT: daddiu $sp, $sp, -16
156 ; MIPS64R2-NEXT: .cfi_def_cfa_offset 16
157 ; MIPS64R2-NEXT: sw $4, 4($sp)
158 ; MIPS64R2-NEXT: lwu $2, 4($sp)
159 ; MIPS64R2-NEXT: sltiu $1, $2, 7
160 ; MIPS64R2-NEXT: beqz $1, .LBB0_3
161 ; MIPS64R2-NEXT: nop
162 ; MIPS64R2-NEXT: .LBB0_1: # %entry
163 ; MIPS64R2-NEXT: daddiu $1, $zero, 8
164 ; MIPS64R2-NEXT: dmult $2, $1
165 ; MIPS64R2-NEXT: mflo $1
166 ; MIPS64R2-NEXT: lui $2, %highest(.LJTI0_0)
167 ; MIPS64R2-NEXT: daddiu $2, $2, %higher(.LJTI0_0)
168 ; MIPS64R2-NEXT: dsll $2, $2, 16
169 ; MIPS64R2-NEXT: daddiu $2, $2, %hi(.LJTI0_0)
170 ; MIPS64R2-NEXT: dsll $2, $2, 16
171 ; MIPS64R2-NEXT: daddu $1, $1, $2
172 ; MIPS64R2-NEXT: ld $1, %lo(.LJTI0_0)($1)
173 ; MIPS64R2-NEXT: jr.hb $1
174 ; MIPS64R2-NEXT: nop
175 ; MIPS64R2-NEXT: .LBB0_2: # %sw.bb
176 ; MIPS64R2-NEXT: lui $1, %highest(.L.str)
177 ; MIPS64R2-NEXT: daddiu $1, $1, %higher(.L.str)
178 ; MIPS64R2-NEXT: dsll $1, $1, 16
179 ; MIPS64R2-NEXT: daddiu $1, $1, %hi(.L.str)
180 ; MIPS64R2-NEXT: dsll $1, $1, 16
181 ; MIPS64R2-NEXT: daddiu $1, $1, %lo(.L.str)
182 ; MIPS64R2-NEXT: j .LBB0_10
183 ; MIPS64R2-NEXT: sd $1, 8($sp)
184 ; MIPS64R2-NEXT: .LBB0_3: # %sw.epilog
185 ; MIPS64R2-NEXT: lui $1, %highest(.L.str.7)
186 ; MIPS64R2-NEXT: daddiu $1, $1, %higher(.L.str.7)
187 ; MIPS64R2-NEXT: dsll $1, $1, 16
188 ; MIPS64R2-NEXT: daddiu $1, $1, %hi(.L.str.7)
189 ; MIPS64R2-NEXT: dsll $1, $1, 16
190 ; MIPS64R2-NEXT: daddiu $1, $1, %lo(.L.str.7)
191 ; MIPS64R2-NEXT: j .LBB0_10
192 ; MIPS64R2-NEXT: sd $1, 8($sp)
193 ; MIPS64R2-NEXT: .LBB0_4: # %sw.bb1
194 ; MIPS64R2-NEXT: lui $1, %highest(.L.str.1)
195 ; MIPS64R2-NEXT: daddiu $1, $1, %higher(.L.str.1)
196 ; MIPS64R2-NEXT: dsll $1, $1, 16
197 ; MIPS64R2-NEXT: daddiu $1, $1, %hi(.L.str.1)
198 ; MIPS64R2-NEXT: dsll $1, $1, 16
199 ; MIPS64R2-NEXT: daddiu $1, $1, %lo(.L.str.1)
200 ; MIPS64R2-NEXT: j .LBB0_10
201 ; MIPS64R2-NEXT: sd $1, 8($sp)
202 ; MIPS64R2-NEXT: .LBB0_5: # %sw.bb2
203 ; MIPS64R2-NEXT: lui $1, %highest(.L.str.2)
204 ; MIPS64R2-NEXT: daddiu $1, $1, %higher(.L.str.2)
205 ; MIPS64R2-NEXT: dsll $1, $1, 16
206 ; MIPS64R2-NEXT: daddiu $1, $1, %hi(.L.str.2)
207 ; MIPS64R2-NEXT: dsll $1, $1, 16
208 ; MIPS64R2-NEXT: daddiu $1, $1, %lo(.L.str.2)
209 ; MIPS64R2-NEXT: j .LBB0_10
210 ; MIPS64R2-NEXT: sd $1, 8($sp)
211 ; MIPS64R2-NEXT: .LBB0_6: # %sw.bb3
212 ; MIPS64R2-NEXT: lui $1, %highest(.L.str.3)
213 ; MIPS64R2-NEXT: daddiu $1, $1, %higher(.L.str.3)
214 ; MIPS64R2-NEXT: dsll $1, $1, 16
215 ; MIPS64R2-NEXT: daddiu $1, $1, %hi(.L.str.3)
216 ; MIPS64R2-NEXT: dsll $1, $1, 16
217 ; MIPS64R2-NEXT: daddiu $1, $1, %lo(.L.str.3)
218 ; MIPS64R2-NEXT: j .LBB0_10
219 ; MIPS64R2-NEXT: sd $1, 8($sp)
220 ; MIPS64R2-NEXT: .LBB0_7: # %sw.bb4
221 ; MIPS64R2-NEXT: lui $1, %highest(.L.str.4)
222 ; MIPS64R2-NEXT: daddiu $1, $1, %higher(.L.str.4)
223 ; MIPS64R2-NEXT: dsll $1, $1, 16
224 ; MIPS64R2-NEXT: daddiu $1, $1, %hi(.L.str.4)
225 ; MIPS64R2-NEXT: dsll $1, $1, 16
226 ; MIPS64R2-NEXT: daddiu $1, $1, %lo(.L.str.4)
227 ; MIPS64R2-NEXT: j .LBB0_10
228 ; MIPS64R2-NEXT: sd $1, 8($sp)
229 ; MIPS64R2-NEXT: .LBB0_8: # %sw.bb5
230 ; MIPS64R2-NEXT: lui $1, %highest(.L.str.5)
231 ; MIPS64R2-NEXT: daddiu $1, $1, %higher(.L.str.5)
232 ; MIPS64R2-NEXT: dsll $1, $1, 16
233 ; MIPS64R2-NEXT: daddiu $1, $1, %hi(.L.str.5)
234 ; MIPS64R2-NEXT: dsll $1, $1, 16
235 ; MIPS64R2-NEXT: daddiu $1, $1, %lo(.L.str.5)
236 ; MIPS64R2-NEXT: j .LBB0_10
237 ; MIPS64R2-NEXT: sd $1, 8($sp)
238 ; MIPS64R2-NEXT: .LBB0_9: # %sw.bb6
239 ; MIPS64R2-NEXT: lui $1, %highest(.L.str.6)
240 ; MIPS64R2-NEXT: daddiu $1, $1, %higher(.L.str.6)
241 ; MIPS64R2-NEXT: dsll $1, $1, 16
242 ; MIPS64R2-NEXT: daddiu $1, $1, %hi(.L.str.6)
243 ; MIPS64R2-NEXT: dsll $1, $1, 16
244 ; MIPS64R2-NEXT: daddiu $1, $1, %lo(.L.str.6)
245 ; MIPS64R2-NEXT: sd $1, 8($sp)
246 ; MIPS64R2-NEXT: .LBB0_10: # %return
247 ; MIPS64R2-NEXT: ld $2, 8($sp)
248 ; MIPS64R2-NEXT: jr $ra
249 ; MIPS64R2-NEXT: daddiu $sp, $sp, 16
250 ;
251 ; MIPS64R6-LABEL: _Z3fooi:
252 ; MIPS64R6: # %bb.0: # %entry
253 ; MIPS64R6-NEXT: daddiu $sp, $sp, -16
254 ; MIPS64R6-NEXT: .cfi_def_cfa_offset 16
255 ; MIPS64R6-NEXT: sw $4, 4($sp)
256 ; MIPS64R6-NEXT: lwu $2, 4($sp)
257 ; MIPS64R6-NEXT: sltiu $1, $2, 7
258 ; MIPS64R6-NEXT: beqzc $1, .LBB0_3
259 ; MIPS64R6-NEXT: .LBB0_1: # %entry
260 ; MIPS64R6-NEXT: dsll $1, $2, 3
261 ; MIPS64R6-NEXT: lui $2, %highest(.LJTI0_0)
262 ; MIPS64R6-NEXT: daddiu $2, $2, %higher(.LJTI0_0)
263 ; MIPS64R6-NEXT: dsll $2, $2, 16
264 ; MIPS64R6-NEXT: daddiu $2, $2, %hi(.LJTI0_0)
265 ; MIPS64R6-NEXT: dsll $2, $2, 16
266 ; MIPS64R6-NEXT: daddu $1, $1, $2
267 ; MIPS64R6-NEXT: ld $1, %lo(.LJTI0_0)($1)
268 ; MIPS64R6-NEXT: jr.hb $1
269 ; MIPS64R6-NEXT: nop
270 ; MIPS64R6-NEXT: .LBB0_2: # %sw.bb
271 ; MIPS64R6-NEXT: lui $1, %highest(.L.str)
272 ; MIPS64R6-NEXT: daddiu $1, $1, %higher(.L.str)
273 ; MIPS64R6-NEXT: dsll $1, $1, 16
274 ; MIPS64R6-NEXT: daddiu $1, $1, %hi(.L.str)
275 ; MIPS64R6-NEXT: dsll $1, $1, 16
276 ; MIPS64R6-NEXT: daddiu $1, $1, %lo(.L.str)
277 ; MIPS64R6-NEXT: j .LBB0_10
278 ; MIPS64R6-NEXT: sd $1, 8($sp)
279 ; MIPS64R6-NEXT: .LBB0_3: # %sw.epilog
280 ; MIPS64R6-NEXT: lui $1, %highest(.L.str.7)
281 ; MIPS64R6-NEXT: daddiu $1, $1, %higher(.L.str.7)
282 ; MIPS64R6-NEXT: dsll $1, $1, 16
283 ; MIPS64R6-NEXT: daddiu $1, $1, %hi(.L.str.7)
284 ; MIPS64R6-NEXT: dsll $1, $1, 16
285 ; MIPS64R6-NEXT: daddiu $1, $1, %lo(.L.str.7)
286 ; MIPS64R6-NEXT: j .LBB0_10
287 ; MIPS64R6-NEXT: sd $1, 8($sp)
288 ; MIPS64R6-NEXT: .LBB0_4: # %sw.bb1
289 ; MIPS64R6-NEXT: lui $1, %highest(.L.str.1)
290 ; MIPS64R6-NEXT: daddiu $1, $1, %higher(.L.str.1)
291 ; MIPS64R6-NEXT: dsll $1, $1, 16
292 ; MIPS64R6-NEXT: daddiu $1, $1, %hi(.L.str.1)
293 ; MIPS64R6-NEXT: dsll $1, $1, 16
294 ; MIPS64R6-NEXT: daddiu $1, $1, %lo(.L.str.1)
295 ; MIPS64R6-NEXT: j .LBB0_10
296 ; MIPS64R6-NEXT: sd $1, 8($sp)
297 ; MIPS64R6-NEXT: .LBB0_5: # %sw.bb2
298 ; MIPS64R6-NEXT: lui $1, %highest(.L.str.2)
299 ; MIPS64R6-NEXT: daddiu $1, $1, %higher(.L.str.2)
300 ; MIPS64R6-NEXT: dsll $1, $1, 16
301 ; MIPS64R6-NEXT: daddiu $1, $1, %hi(.L.str.2)
302 ; MIPS64R6-NEXT: dsll $1, $1, 16
303 ; MIPS64R6-NEXT: daddiu $1, $1, %lo(.L.str.2)
304 ; MIPS64R6-NEXT: j .LBB0_10
305 ; MIPS64R6-NEXT: sd $1, 8($sp)
306 ; MIPS64R6-NEXT: .LBB0_6: # %sw.bb3
307 ; MIPS64R6-NEXT: lui $1, %highest(.L.str.3)
308 ; MIPS64R6-NEXT: daddiu $1, $1, %higher(.L.str.3)
309 ; MIPS64R6-NEXT: dsll $1, $1, 16
310 ; MIPS64R6-NEXT: daddiu $1, $1, %hi(.L.str.3)
311 ; MIPS64R6-NEXT: dsll $1, $1, 16
312 ; MIPS64R6-NEXT: daddiu $1, $1, %lo(.L.str.3)
313 ; MIPS64R6-NEXT: j .LBB0_10
314 ; MIPS64R6-NEXT: sd $1, 8($sp)
315 ; MIPS64R6-NEXT: .LBB0_7: # %sw.bb4
316 ; MIPS64R6-NEXT: lui $1, %highest(.L.str.4)
317 ; MIPS64R6-NEXT: daddiu $1, $1, %higher(.L.str.4)
318 ; MIPS64R6-NEXT: dsll $1, $1, 16
319 ; MIPS64R6-NEXT: daddiu $1, $1, %hi(.L.str.4)
320 ; MIPS64R6-NEXT: dsll $1, $1, 16
321 ; MIPS64R6-NEXT: daddiu $1, $1, %lo(.L.str.4)
322 ; MIPS64R6-NEXT: j .LBB0_10
323 ; MIPS64R6-NEXT: sd $1, 8($sp)
324 ; MIPS64R6-NEXT: .LBB0_8: # %sw.bb5
325 ; MIPS64R6-NEXT: lui $1, %highest(.L.str.5)
326 ; MIPS64R6-NEXT: daddiu $1, $1, %higher(.L.str.5)
327 ; MIPS64R6-NEXT: dsll $1, $1, 16
328 ; MIPS64R6-NEXT: daddiu $1, $1, %hi(.L.str.5)
329 ; MIPS64R6-NEXT: dsll $1, $1, 16
330 ; MIPS64R6-NEXT: daddiu $1, $1, %lo(.L.str.5)
331 ; MIPS64R6-NEXT: j .LBB0_10
332 ; MIPS64R6-NEXT: sd $1, 8($sp)
333 ; MIPS64R6-NEXT: .LBB0_9: # %sw.bb6
334 ; MIPS64R6-NEXT: lui $1, %highest(.L.str.6)
335 ; MIPS64R6-NEXT: daddiu $1, $1, %higher(.L.str.6)
336 ; MIPS64R6-NEXT: dsll $1, $1, 16
337 ; MIPS64R6-NEXT: daddiu $1, $1, %hi(.L.str.6)
338 ; MIPS64R6-NEXT: dsll $1, $1, 16
339 ; MIPS64R6-NEXT: daddiu $1, $1, %lo(.L.str.6)
340 ; MIPS64R6-NEXT: sd $1, 8($sp)
341 ; MIPS64R6-NEXT: .LBB0_10: # %return
342 ; MIPS64R6-NEXT: ld $2, 8($sp)
343 ; MIPS64R6-NEXT: jr $ra
344 ; MIPS64R6-NEXT: daddiu $sp, $sp, 16
345 ;
346 ; PIC-MIPS32R2-LABEL: _Z3fooi:
347 ; PIC-MIPS32R2: # %bb.0: # %entry
348 ; PIC-MIPS32R2-NEXT: lui $2, %hi(_gp_disp)
349 ; PIC-MIPS32R2-NEXT: addiu $2, $2, %lo(_gp_disp)
350 ; PIC-MIPS32R2-NEXT: addiu $sp, $sp, -16
351 ; PIC-MIPS32R2-NEXT: .cfi_def_cfa_offset 16
352 ; PIC-MIPS32R2-NEXT: addu $2, $2, $25
353 ; PIC-MIPS32R2-NEXT: sltiu $1, $4, 7
354 ; PIC-MIPS32R2-NEXT: beqz $1, $BB0_3
355 ; PIC-MIPS32R2-NEXT: sw $4, 4($sp)
356 ; PIC-MIPS32R2-NEXT: $BB0_1: # %entry
357 ; PIC-MIPS32R2-NEXT: sll $1, $4, 2
358 ; PIC-MIPS32R2-NEXT: lw $3, %got($JTI0_0)($2)
359 ; PIC-MIPS32R2-NEXT: addu $1, $1, $3
360 ; PIC-MIPS32R2-NEXT: lw $1, %lo($JTI0_0)($1)
361 ; PIC-MIPS32R2-NEXT: addu $1, $1, $2
362 ; PIC-MIPS32R2-NEXT: jr.hb $1
363 ; PIC-MIPS32R2-NEXT: nop
364 ; PIC-MIPS32R2-NEXT: $BB0_2: # %sw.bb
365 ; PIC-MIPS32R2-NEXT: lw $1, %got($.str)($2)
366 ; PIC-MIPS32R2-NEXT: addiu $1, $1, %lo($.str)
367 ; PIC-MIPS32R2-NEXT: b $BB0_10
368 ; PIC-MIPS32R2-NEXT: sw $1, 8($sp)
369 ; PIC-MIPS32R2-NEXT: $BB0_3: # %sw.epilog
370 ; PIC-MIPS32R2-NEXT: lw $1, %got($.str.7)($2)
371 ; PIC-MIPS32R2-NEXT: addiu $1, $1, %lo($.str.7)
372 ; PIC-MIPS32R2-NEXT: b $BB0_10
373 ; PIC-MIPS32R2-NEXT: sw $1, 8($sp)
374 ; PIC-MIPS32R2-NEXT: $BB0_4: # %sw.bb1
375 ; PIC-MIPS32R2-NEXT: lw $1, %got($.str.1)($2)
376 ; PIC-MIPS32R2-NEXT: addiu $1, $1, %lo($.str.1)
377 ; PIC-MIPS32R2-NEXT: b $BB0_10
378 ; PIC-MIPS32R2-NEXT: sw $1, 8($sp)
379 ; PIC-MIPS32R2-NEXT: $BB0_5: # %sw.bb2
380 ; PIC-MIPS32R2-NEXT: lw $1, %got($.str.2)($2)
381 ; PIC-MIPS32R2-NEXT: addiu $1, $1, %lo($.str.2)
382 ; PIC-MIPS32R2-NEXT: b $BB0_10
383 ; PIC-MIPS32R2-NEXT: sw $1, 8($sp)
384 ; PIC-MIPS32R2-NEXT: $BB0_6: # %sw.bb3
385 ; PIC-MIPS32R2-NEXT: lw $1, %got($.str.3)($2)
386 ; PIC-MIPS32R2-NEXT: addiu $1, $1, %lo($.str.3)
387 ; PIC-MIPS32R2-NEXT: b $BB0_10
388 ; PIC-MIPS32R2-NEXT: sw $1, 8($sp)
389 ; PIC-MIPS32R2-NEXT: $BB0_7: # %sw.bb4
390 ; PIC-MIPS32R2-NEXT: lw $1, %got($.str.4)($2)
391 ; PIC-MIPS32R2-NEXT: addiu $1, $1, %lo($.str.4)
392 ; PIC-MIPS32R2-NEXT: b $BB0_10
393 ; PIC-MIPS32R2-NEXT: sw $1, 8($sp)
394 ; PIC-MIPS32R2-NEXT: $BB0_8: # %sw.bb5
395 ; PIC-MIPS32R2-NEXT: lw $1, %got($.str.5)($2)
396 ; PIC-MIPS32R2-NEXT: addiu $1, $1, %lo($.str.5)
397 ; PIC-MIPS32R2-NEXT: b $BB0_10
398 ; PIC-MIPS32R2-NEXT: sw $1, 8($sp)
399 ; PIC-MIPS32R2-NEXT: $BB0_9: # %sw.bb6
400 ; PIC-MIPS32R2-NEXT: lw $1, %got($.str.6)($2)
401 ; PIC-MIPS32R2-NEXT: addiu $1, $1, %lo($.str.6)
402 ; PIC-MIPS32R2-NEXT: sw $1, 8($sp)
403 ; PIC-MIPS32R2-NEXT: $BB0_10: # %return
404 ; PIC-MIPS32R2-NEXT: lw $2, 8($sp)
405 ; PIC-MIPS32R2-NEXT: jr $ra
406 ; PIC-MIPS32R2-NEXT: addiu $sp, $sp, 16
407 ;
408 ; PIC-MIPS32R6-LABEL: _Z3fooi:
409 ; PIC-MIPS32R6: # %bb.0: # %entry
410 ; PIC-MIPS32R6-NEXT: lui $2, %hi(_gp_disp)
411 ; PIC-MIPS32R6-NEXT: addiu $2, $2, %lo(_gp_disp)
412 ; PIC-MIPS32R6-NEXT: addiu $sp, $sp, -16
413 ; PIC-MIPS32R6-NEXT: .cfi_def_cfa_offset 16
414 ; PIC-MIPS32R6-NEXT: addu $2, $2, $25
415 ; PIC-MIPS32R6-NEXT: sltiu $1, $4, 7
416 ; PIC-MIPS32R6-NEXT: beqz $1, $BB0_3
417 ; PIC-MIPS32R6-NEXT: sw $4, 4($sp)
418 ; PIC-MIPS32R6-NEXT: $BB0_1: # %entry
419 ; PIC-MIPS32R6-NEXT: sll $1, $4, 2
420 ; PIC-MIPS32R6-NEXT: lw $3, %got($JTI0_0)($2)
421 ; PIC-MIPS32R6-NEXT: addu $1, $1, $3
422 ; PIC-MIPS32R6-NEXT: lw $1, %lo($JTI0_0)($1)
423 ; PIC-MIPS32R6-NEXT: addu $1, $1, $2
424 ; PIC-MIPS32R6-NEXT: jr.hb $1
425 ; PIC-MIPS32R6-NEXT: nop
426 ; PIC-MIPS32R6-NEXT: $BB0_2: # %sw.bb
427 ; PIC-MIPS32R6-NEXT: lw $1, %got($.str)($2)
428 ; PIC-MIPS32R6-NEXT: addiu $1, $1, %lo($.str)
429 ; PIC-MIPS32R6-NEXT: b $BB0_10
430 ; PIC-MIPS32R6-NEXT: sw $1, 8($sp)
431 ; PIC-MIPS32R6-NEXT: $BB0_3: # %sw.epilog
432 ; PIC-MIPS32R6-NEXT: lw $1, %got($.str.7)($2)
433 ; PIC-MIPS32R6-NEXT: addiu $1, $1, %lo($.str.7)
434 ; PIC-MIPS32R6-NEXT: b $BB0_10
435 ; PIC-MIPS32R6-NEXT: sw $1, 8($sp)
436 ; PIC-MIPS32R6-NEXT: $BB0_4: # %sw.bb1
437 ; PIC-MIPS32R6-NEXT: lw $1, %got($.str.1)($2)
438 ; PIC-MIPS32R6-NEXT: addiu $1, $1, %lo($.str.1)
439 ; PIC-MIPS32R6-NEXT: b $BB0_10
440 ; PIC-MIPS32R6-NEXT: sw $1, 8($sp)
441 ; PIC-MIPS32R6-NEXT: $BB0_5: # %sw.bb2
442 ; PIC-MIPS32R6-NEXT: lw $1, %got($.str.2)($2)
443 ; PIC-MIPS32R6-NEXT: addiu $1, $1, %lo($.str.2)
444 ; PIC-MIPS32R6-NEXT: b $BB0_10
445 ; PIC-MIPS32R6-NEXT: sw $1, 8($sp)
446 ; PIC-MIPS32R6-NEXT: $BB0_6: # %sw.bb3
447 ; PIC-MIPS32R6-NEXT: lw $1, %got($.str.3)($2)
448 ; PIC-MIPS32R6-NEXT: addiu $1, $1, %lo($.str.3)
449 ; PIC-MIPS32R6-NEXT: b $BB0_10
450 ; PIC-MIPS32R6-NEXT: sw $1, 8($sp)
451 ; PIC-MIPS32R6-NEXT: $BB0_7: # %sw.bb4
452 ; PIC-MIPS32R6-NEXT: lw $1, %got($.str.4)($2)
453 ; PIC-MIPS32R6-NEXT: addiu $1, $1, %lo($.str.4)
454 ; PIC-MIPS32R6-NEXT: b $BB0_10
455 ; PIC-MIPS32R6-NEXT: sw $1, 8($sp)
456 ; PIC-MIPS32R6-NEXT: $BB0_8: # %sw.bb5
457 ; PIC-MIPS32R6-NEXT: lw $1, %got($.str.5)($2)
458 ; PIC-MIPS32R6-NEXT: addiu $1, $1, %lo($.str.5)
459 ; PIC-MIPS32R6-NEXT: b $BB0_10
460 ; PIC-MIPS32R6-NEXT: sw $1, 8($sp)
461 ; PIC-MIPS32R6-NEXT: $BB0_9: # %sw.bb6
462 ; PIC-MIPS32R6-NEXT: lw $1, %got($.str.6)($2)
463 ; PIC-MIPS32R6-NEXT: addiu $1, $1, %lo($.str.6)
464 ; PIC-MIPS32R6-NEXT: sw $1, 8($sp)
465 ; PIC-MIPS32R6-NEXT: $BB0_10: # %return
466 ; PIC-MIPS32R6-NEXT: lw $2, 8($sp)
467 ; PIC-MIPS32R6-NEXT: jr $ra
468 ; PIC-MIPS32R6-NEXT: addiu $sp, $sp, 16
469 ;
470 ; PIC-MIPS64R2-LABEL: _Z3fooi:
471 ; PIC-MIPS64R2: # %bb.0: # %entry
472 ; PIC-MIPS64R2-NEXT: daddiu $sp, $sp, -16
473 ; PIC-MIPS64R2-NEXT: .cfi_def_cfa_offset 16
474 ; PIC-MIPS64R2-NEXT: lui $1, %hi(%neg(%gp_rel(_Z3fooi)))
475 ; PIC-MIPS64R2-NEXT: daddu $1, $1, $25
476 ; PIC-MIPS64R2-NEXT: daddiu $2, $1, %lo(%neg(%gp_rel(_Z3fooi)))
477 ; PIC-MIPS64R2-NEXT: sw $4, 4($sp)
478 ; PIC-MIPS64R2-NEXT: lwu $3, 4($sp)
479 ; PIC-MIPS64R2-NEXT: sltiu $1, $3, 7
480 ; PIC-MIPS64R2-NEXT: beqz $1, .LBB0_3
481 ; PIC-MIPS64R2-NEXT: nop
482 ; PIC-MIPS64R2-NEXT: .LBB0_1: # %entry
483 ; PIC-MIPS64R2-NEXT: daddiu $1, $zero, 8
484 ; PIC-MIPS64R2-NEXT: dmult $3, $1
485 ; PIC-MIPS64R2-NEXT: mflo $1
486 ; PIC-MIPS64R2-NEXT: ld $3, %got_page(.LJTI0_0)($2)
487 ; PIC-MIPS64R2-NEXT: daddu $1, $1, $3
488 ; PIC-MIPS64R2-NEXT: ld $1, %got_ofst(.LJTI0_0)($1)
489 ; PIC-MIPS64R2-NEXT: daddu $1, $1, $2
490 ; PIC-MIPS64R2-NEXT: jr.hb $1
491 ; PIC-MIPS64R2-NEXT: nop
492 ; PIC-MIPS64R2-NEXT: .LBB0_2: # %sw.bb
493 ; PIC-MIPS64R2-NEXT: ld $1, %got_page(.L.str)($2)
494 ; PIC-MIPS64R2-NEXT: daddiu $1, $1, %got_ofst(.L.str)
495 ; PIC-MIPS64R2-NEXT: b .LBB0_10
496 ; PIC-MIPS64R2-NEXT: sd $1, 8($sp)
497 ; PIC-MIPS64R2-NEXT: .LBB0_3: # %sw.epilog
498 ; PIC-MIPS64R2-NEXT: ld $1, %got_page(.L.str.7)($2)
499 ; PIC-MIPS64R2-NEXT: daddiu $1, $1, %got_ofst(.L.str.7)
500 ; PIC-MIPS64R2-NEXT: b .LBB0_10
501 ; PIC-MIPS64R2-NEXT: sd $1, 8($sp)
502 ; PIC-MIPS64R2-NEXT: .LBB0_4: # %sw.bb1
503 ; PIC-MIPS64R2-NEXT: ld $1, %got_page(.L.str.1)($2)
504 ; PIC-MIPS64R2-NEXT: daddiu $1, $1, %got_ofst(.L.str.1)
505 ; PIC-MIPS64R2-NEXT: b .LBB0_10
506 ; PIC-MIPS64R2-NEXT: sd $1, 8($sp)
507 ; PIC-MIPS64R2-NEXT: .LBB0_5: # %sw.bb2
508 ; PIC-MIPS64R2-NEXT: ld $1, %got_page(.L.str.2)($2)
509 ; PIC-MIPS64R2-NEXT: daddiu $1, $1, %got_ofst(.L.str.2)
510 ; PIC-MIPS64R2-NEXT: b .LBB0_10
511 ; PIC-MIPS64R2-NEXT: sd $1, 8($sp)
512 ; PIC-MIPS64R2-NEXT: .LBB0_6: # %sw.bb3
513 ; PIC-MIPS64R2-NEXT: ld $1, %got_page(.L.str.3)($2)
514 ; PIC-MIPS64R2-NEXT: daddiu $1, $1, %got_ofst(.L.str.3)
515 ; PIC-MIPS64R2-NEXT: b .LBB0_10
516 ; PIC-MIPS64R2-NEXT: sd $1, 8($sp)
517 ; PIC-MIPS64R2-NEXT: .LBB0_7: # %sw.bb4
518 ; PIC-MIPS64R2-NEXT: ld $1, %got_page(.L.str.4)($2)
519 ; PIC-MIPS64R2-NEXT: daddiu $1, $1, %got_ofst(.L.str.4)
520 ; PIC-MIPS64R2-NEXT: b .LBB0_10
521 ; PIC-MIPS64R2-NEXT: sd $1, 8($sp)
522 ; PIC-MIPS64R2-NEXT: .LBB0_8: # %sw.bb5
523 ; PIC-MIPS64R2-NEXT: ld $1, %got_page(.L.str.5)($2)
524 ; PIC-MIPS64R2-NEXT: daddiu $1, $1, %got_ofst(.L.str.5)
525 ; PIC-MIPS64R2-NEXT: b .LBB0_10
526 ; PIC-MIPS64R2-NEXT: sd $1, 8($sp)
527 ; PIC-MIPS64R2-NEXT: .LBB0_9: # %sw.bb6
528 ; PIC-MIPS64R2-NEXT: ld $1, %got_page(.L.str.6)($2)
529 ; PIC-MIPS64R2-NEXT: daddiu $1, $1, %got_ofst(.L.str.6)
530 ; PIC-MIPS64R2-NEXT: sd $1, 8($sp)
531 ; PIC-MIPS64R2-NEXT: .LBB0_10: # %return
532 ; PIC-MIPS64R2-NEXT: ld $2, 8($sp)
533 ; PIC-MIPS64R2-NEXT: jr $ra
534 ; PIC-MIPS64R2-NEXT: daddiu $sp, $sp, 16
535 ;
536 ; PIC-MIPS64R6-LABEL: _Z3fooi:
537 ; PIC-MIPS64R6: # %bb.0: # %entry
538 ; PIC-MIPS64R6-NEXT: daddiu $sp, $sp, -16
539 ; PIC-MIPS64R6-NEXT: .cfi_def_cfa_offset 16
540 ; PIC-MIPS64R6-NEXT: lui $1, %hi(%neg(%gp_rel(_Z3fooi)))
541 ; PIC-MIPS64R6-NEXT: daddu $1, $1, $25
542 ; PIC-MIPS64R6-NEXT: daddiu $2, $1, %lo(%neg(%gp_rel(_Z3fooi)))
543 ; PIC-MIPS64R6-NEXT: sw $4, 4($sp)
544 ; PIC-MIPS64R6-NEXT: lwu $3, 4($sp)
545 ; PIC-MIPS64R6-NEXT: sltiu $1, $3, 7
546 ; PIC-MIPS64R6-NEXT: beqzc $1, .LBB0_3
547 ; PIC-MIPS64R6-NEXT: .LBB0_1: # %entry
548 ; PIC-MIPS64R6-NEXT: dsll $1, $3, 3
549 ; PIC-MIPS64R6-NEXT: ld $3, %got_page(.LJTI0_0)($2)
550 ; PIC-MIPS64R6-NEXT: daddu $1, $1, $3
551 ; PIC-MIPS64R6-NEXT: ld $1, %got_ofst(.LJTI0_0)($1)
552 ; PIC-MIPS64R6-NEXT: daddu $1, $1, $2
553 ; PIC-MIPS64R6-NEXT: jr.hb $1
554 ; PIC-MIPS64R6-NEXT: nop
555 ; PIC-MIPS64R6-NEXT: .LBB0_2: # %sw.bb
556 ; PIC-MIPS64R6-NEXT: ld $1, %got_page(.L.str)($2)
557 ; PIC-MIPS64R6-NEXT: daddiu $1, $1, %got_ofst(.L.str)
558 ; PIC-MIPS64R6-NEXT: b .LBB0_10
559 ; PIC-MIPS64R6-NEXT: sd $1, 8($sp)
560 ; PIC-MIPS64R6-NEXT: .LBB0_3: # %sw.epilog
561 ; PIC-MIPS64R6-NEXT: ld $1, %got_page(.L.str.7)($2)
562 ; PIC-MIPS64R6-NEXT: daddiu $1, $1, %got_ofst(.L.str.7)
563 ; PIC-MIPS64R6-NEXT: b .LBB0_10
564 ; PIC-MIPS64R6-NEXT: sd $1, 8($sp)
565 ; PIC-MIPS64R6-NEXT: .LBB0_4: # %sw.bb1
566 ; PIC-MIPS64R6-NEXT: ld $1, %got_page(.L.str.1)($2)
567 ; PIC-MIPS64R6-NEXT: daddiu $1, $1, %got_ofst(.L.str.1)
568 ; PIC-MIPS64R6-NEXT: b .LBB0_10
569 ; PIC-MIPS64R6-NEXT: sd $1, 8($sp)
570 ; PIC-MIPS64R6-NEXT: .LBB0_5: # %sw.bb2
571 ; PIC-MIPS64R6-NEXT: ld $1, %got_page(.L.str.2)($2)
572 ; PIC-MIPS64R6-NEXT: daddiu $1, $1, %got_ofst(.L.str.2)
573 ; PIC-MIPS64R6-NEXT: b .LBB0_10
574 ; PIC-MIPS64R6-NEXT: sd $1, 8($sp)
575 ; PIC-MIPS64R6-NEXT: .LBB0_6: # %sw.bb3
576 ; PIC-MIPS64R6-NEXT: ld $1, %got_page(.L.str.3)($2)
577 ; PIC-MIPS64R6-NEXT: daddiu $1, $1, %got_ofst(.L.str.3)
578 ; PIC-MIPS64R6-NEXT: b .LBB0_10
579 ; PIC-MIPS64R6-NEXT: sd $1, 8($sp)
580 ; PIC-MIPS64R6-NEXT: .LBB0_7: # %sw.bb4
581 ; PIC-MIPS64R6-NEXT: ld $1, %got_page(.L.str.4)($2)
582 ; PIC-MIPS64R6-NEXT: daddiu $1, $1, %got_ofst(.L.str.4)
583 ; PIC-MIPS64R6-NEXT: b .LBB0_10
584 ; PIC-MIPS64R6-NEXT: sd $1, 8($sp)
585 ; PIC-MIPS64R6-NEXT: .LBB0_8: # %sw.bb5
586 ; PIC-MIPS64R6-NEXT: ld $1, %got_page(.L.str.5)($2)
587 ; PIC-MIPS64R6-NEXT: daddiu $1, $1, %got_ofst(.L.str.5)
588 ; PIC-MIPS64R6-NEXT: b .LBB0_10
589 ; PIC-MIPS64R6-NEXT: sd $1, 8($sp)
590 ; PIC-MIPS64R6-NEXT: .LBB0_9: # %sw.bb6
591 ; PIC-MIPS64R6-NEXT: ld $1, %got_page(.L.str.6)($2)
592 ; PIC-MIPS64R6-NEXT: daddiu $1, $1, %got_ofst(.L.str.6)
593 ; PIC-MIPS64R6-NEXT: sd $1, 8($sp)
594 ; PIC-MIPS64R6-NEXT: .LBB0_10: # %return
595 ; PIC-MIPS64R6-NEXT: ld $2, 8($sp)
596 ; PIC-MIPS64R6-NEXT: jr $ra
597 ; PIC-MIPS64R6-NEXT: daddiu $sp, $sp, 16
598 entry:
599 %retval = alloca i8*, align 8
600 %Letter.addr = alloca i32, align 4
601 store i32 %Letter, i32* %Letter.addr, align 4
602 %0 = load i32, i32* %Letter.addr, align 4
603 switch i32 %0, label %sw.epilog [
604 i32 0, label %sw.bb
605 i32 1, label %sw.bb1
606 i32 2, label %sw.bb2
607 i32 3, label %sw.bb3
608 i32 4, label %sw.bb4
609 i32 5, label %sw.bb5
610 i32 6, label %sw.bb6
611 ]
612
613 sw.bb:
614 store i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str, i32 0, i32 0), i8** %retval, align 8
615 br label %return
616
617 sw.bb1:
618 store i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str.1, i32 0, i32 0), i8** %retval, align 8
619 br label %return
620
621 sw.bb2:
622 store i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str.2, i32 0, i32 0), i8** %retval, align 8
623 br label %return
624
625 sw.bb3:
626 store i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str.3, i32 0, i32 0), i8** %retval, align 8
627 br label %return
628
629 sw.bb4:
630 store i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str.4, i32 0, i32 0), i8** %retval, align 8
631 br label %return
632
633 sw.bb5:
634 store i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str.5, i32 0, i32 0), i8** %retval, align 8
635 br label %return
636
637 sw.bb6:
638 store i8* getelementptr inbounds ([2 x i8], [2 x i8]* @.str.6, i32 0, i32 0), i8** %retval, align 8
639 br label %return
640
641 sw.epilog:
642 store i8* getelementptr inbounds ([1 x i8], [1 x i8]* @.str.7, i32 0, i32 0), i8** %retval, align 8
643 br label %return
644
645 return:
646 %1 = load i8*, i8** %retval, align 8
647 ret i8* %1
648 }
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; Except for the NACL version which isn't parsed by update_llc_test_checks.py
2
3 ; RUN: llc -mtriple=mipsel-unknown-linux-gnu -force-mips-long-branch -O3 \
4 ; RUN: -mcpu=mips32r2 -mattr=+use-indirect-jump-hazard -relocation-model=pic \
5 ; RUN: -verify-machineinstrs < %s | FileCheck %s -check-prefix=O32-PIC
6
7 ; RUN: llc -mtriple=mipsel-unknown-linux-gnu -mcpu=mips32r6 \
8 ; RUN: -force-mips-long-branch -O3 -mattr=+use-indirect-jump-hazard \
9 ; RUN: -relocation-model=pic -verify-machineinstrs < %s \
10 ; RUN: | FileCheck %s -check-prefix=O32-R6-PIC
11
12 ; RUN: llc -mtriple=mips64el-unknown-linux-gnu -mcpu=mips64r2 -target-abi=n64 \
13 ; RUN: -force-mips-long-branch -O3 -relocation-model=pic \
14 ; RUN: -mattr=+use-indirect-jump-hazard -verify-machineinstrs \
15 ; RUN: < %s | FileCheck %s -check-prefix=MIPS64
16
17 ; RUN: llc -mtriple=mips64el-unknown-linux-gnu -mcpu=mips64r6 -target-abi=n64 \
18 ; RUN: -force-mips-long-branch -O3 -mattr=+use-indirect-jump-hazard \
19 ; RUN: -relocation-model=pic -verify-machineinstrs < %s \
20 ; RUN: | FileCheck %s -check-prefix=N64-R6
21
22 ; Test that the long branches also get changed to their hazard variants.
23
24 @x = external global i32
25
26 define void @test1(i32 signext %s) {
27 ; O32-PIC-LABEL: test1:
28 ; O32-PIC: # %bb.0: # %entry
29 ; O32-PIC-NEXT: lui $2, %hi(_gp_disp)
30 ; O32-PIC-NEXT: addiu $2, $2, %lo(_gp_disp)
31 ; O32-PIC-NEXT: bnez $4, $BB0_3
32 ; O32-PIC-NEXT: addu $2, $2, $25
33 ; O32-PIC-NEXT: # %bb.1: # %entry
34 ; O32-PIC-NEXT: addiu $sp, $sp, -8
35 ; O32-PIC-NEXT: sw $ra, 0($sp)
36 ; O32-PIC-NEXT: lui $1, %hi(($BB0_4)-($BB0_2))
37 ; O32-PIC-NEXT: bal $BB0_2
38 ; O32-PIC-NEXT: addiu $1, $1, %lo(($BB0_4)-($BB0_2))
39 ; O32-PIC-NEXT: $BB0_2: # %entry
40 ; O32-PIC-NEXT: addu $1, $ra, $1
41 ; O32-PIC-NEXT: lw $ra, 0($sp)
42 ; O32-PIC-NEXT: jr.hb $1
43 ; O32-PIC-NEXT: addiu $sp, $sp, 8
44 ; O32-PIC-NEXT: $BB0_3: # %then
45 ; O32-PIC-NEXT: lw $1, %got(x)($2)
46 ; O32-PIC-NEXT: addiu $2, $zero, 1
47 ; O32-PIC-NEXT: sw $2, 0($1)
48 ; O32-PIC-NEXT: $BB0_4: # %end
49 ; O32-PIC-NEXT: jr $ra
50 ; O32-PIC-NEXT: nop
51 ;
52 ; O32-R6-PIC-LABEL: test1:
53 ; O32-R6-PIC: # %bb.0: # %entry
54 ; O32-R6-PIC-NEXT: lui $2, %hi(_gp_disp)
55 ; O32-R6-PIC-NEXT: addiu $2, $2, %lo(_gp_disp)
56 ; O32-R6-PIC-NEXT: bnez $4, $BB0_3
57 ; O32-R6-PIC-NEXT: addu $2, $2, $25
58 ; O32-R6-PIC-NEXT: # %bb.1: # %entry
59 ; O32-R6-PIC-NEXT: addiu $sp, $sp, -8
60 ; O32-R6-PIC-NEXT: sw $ra, 0($sp)
61 ; O32-R6-PIC-NEXT: lui $1, %hi(($BB0_4)-($BB0_2))
62 ; O32-R6-PIC-NEXT: addiu $1, $1, %lo(($BB0_4)-($BB0_2))
63 ; O32-R6-PIC-NEXT: balc $BB0_2
64 ; O32-R6-PIC-NEXT: $BB0_2: # %entry
65 ; O32-R6-PIC-NEXT: addu $1, $ra, $1
66 ; O32-R6-PIC-NEXT: lw $ra, 0($sp)
67 ; O32-R6-PIC-NEXT: jr.hb $1
68 ; O32-R6-PIC-NEXT: addiu $sp, $sp, 8
69 ; O32-R6-PIC-NEXT: $BB0_3: # %then
70 ; O32-R6-PIC-NEXT: lw $1, %got(x)($2)
71 ; O32-R6-PIC-NEXT: addiu $2, $zero, 1
72 ; O32-R6-PIC-NEXT: sw $2, 0($1)
73 ; O32-R6-PIC-NEXT: $BB0_4: # %end
74 ; O32-R6-PIC-NEXT: jrc $ra
75 ;
76 ; MIPS64-LABEL: test1:
77 ; MIPS64: # %bb.0: # %entry
78 ; MIPS64-NEXT: lui $1, %hi(%neg(%gp_rel(test1)))
79 ; MIPS64-NEXT: bnez $4, .LBB0_3
80 ; MIPS64-NEXT: daddu $2, $1, $25
81 ; MIPS64-NEXT: # %bb.1: # %entry
82 ; MIPS64-NEXT: daddiu $sp, $sp, -16
83 ; MIPS64-NEXT: sd $ra, 0($sp)
84 ; MIPS64-NEXT: daddiu $1, $zero, %hi(.LBB0_4-.LBB0_2)
85 ; MIPS64-NEXT: dsll $1, $1, 16
86 ; MIPS64-NEXT: bal .LBB0_2
87 ; MIPS64-NEXT: daddiu $1, $1, %lo(.LBB0_4-.LBB0_2)
88 ; MIPS64-NEXT: .LBB0_2: # %entry
89 ; MIPS64-NEXT: daddu $1, $ra, $1
90 ; MIPS64-NEXT: ld $ra, 0($sp)
91 ; MIPS64-NEXT: jr.hb $1
92 ; MIPS64-NEXT: daddiu $sp, $sp, 16
93 ; MIPS64-NEXT: .LBB0_3: # %then
94 ; MIPS64-NEXT: daddiu $1, $2, %lo(%neg(%gp_rel(test1)))
95 ; MIPS64-NEXT: addiu $2, $zero, 1
96 ; MIPS64-NEXT: ld $1, %got_disp(x)($1)
97 ; MIPS64-NEXT: sw $2, 0($1)
98 ; MIPS64-NEXT: .LBB0_4: # %end
99 ; MIPS64-NEXT: jr $ra
100 ; MIPS64-NEXT: nop
101 ;
102 ; N64-R6-LABEL: test1:
103 ; N64-R6: # %bb.0: # %entry
104 ; N64-R6-NEXT: lui $1, %hi(%neg(%gp_rel(test1)))
105 ; N64-R6-NEXT: bnez $4, .LBB0_3
106 ; N64-R6-NEXT: daddu $2, $1, $25
107 ; N64-R6-NEXT: # %bb.1: # %entry
108 ; N64-R6-NEXT: daddiu $sp, $sp, -16
109 ; N64-R6-NEXT: sd $ra, 0($sp)
110 ; N64-R6-NEXT: daddiu $1, $zero, %hi(.LBB0_4-.LBB0_2)
111 ; N64-R6-NEXT: dsll $1, $1, 16
112 ; N64-R6-NEXT: daddiu $1, $1, %lo(.LBB0_4-.LBB0_2)
113 ; N64-R6-NEXT: balc .LBB0_2
114 ; N64-R6-NEXT: .LBB0_2: # %entry
115 ; N64-R6-NEXT: daddu $1, $ra, $1
116 ; N64-R6-NEXT: ld $ra, 0($sp)
117 ; N64-R6-NEXT: jr.hb $1
118 ; N64-R6-NEXT: daddiu $sp, $sp, 16
119 ; N64-R6-NEXT: .LBB0_3: # %then
120 ; N64-R6-NEXT: daddiu $1, $2, %lo(%neg(%gp_rel(test1)))
121 ; N64-R6-NEXT: addiu $2, $zero, 1
122 ; N64-R6-NEXT: ld $1, %got_disp(x)($1)
123 ; N64-R6-NEXT: sw $2, 0($1)
124 ; N64-R6-NEXT: .LBB0_4: # %end
125 ; N64-R6-NEXT: jrc $ra
126 entry:
127 %cmp = icmp eq i32 %s, 0
128 br i1 %cmp, label %end, label %then
129
130 then:
131 store i32 1, i32* @x, align 4
132 br label %end
133
134 end:
135 ret void
136
137 }
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -mtriple=mips-unknwon-linux-gnu -mcpu=mips32r2 \
2 ; RUN: -mattr=+use-indirect-jump-hazard,+long-calls,+noabicalls %s -o - \
3 ; RUN: -verify-machineinstrs | FileCheck -check-prefix=O32 %s
4
5 ; RUN: llc -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r2 -target-abi n32 \
6 ; RUN: -mattr=+use-indirect-jump-hazard,+long-calls,+noabicalls %s -o - \
7 ; RUN: -verify-machineinstrs | FileCheck -check-prefix=N32 %s
8
9 ; RUN: llc -mtriple=mips64-unknown-linux-gnu -mcpu=mips64r2 -target-abi n64 \
10 ; RUN: -mattr=+use-indirect-jump-hazard,+long-calls,+noabicalls %s -o - \
11 ; RUN: -verify-machineinstrs | FileCheck -check-prefix=N64 %s
12
13 declare void @callee()
14 declare void @llvm.memset.p0i8.i32(i8* nocapture writeonly, i8, i32, i32, i1)
15
16 @val = internal unnamed_addr global [20 x i32] zeroinitializer, align 4
17
18 ; Test that the long call sequence uses the hazard barrier instruction variant.
19 define void @caller() {
20 ; O32-LABEL: caller:
21 ; O32: # %bb.0:
22 ; O32-NEXT: addiu $sp, $sp, -24
23 ; O32-NEXT: .cfi_def_cfa_offset 24
24 ; O32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
25 ; O32-NEXT: .cfi_offset 31, -4
26 ; O32-NEXT: lui $1, %hi(callee)
27 ; O32-NEXT: addiu $25, $1, %lo(callee)
28 ; O32-NEXT: jalr.hb $25
29 ; O32-NEXT: nop
30 ; O32-NEXT: lui $1, %hi(val)
31 ; O32-NEXT: addiu $1, $1, %lo(val)
32 ; O32-NEXT: lui $2, 20560
33 ; O32-NEXT: ori $2, $2, 20560
34 ; O32-NEXT: sw $2, 96($1)
35 ; O32-NEXT: sw $2, 92($1)
36 ; O32-NEXT: sw $2, 88($1)
37 ; O32-NEXT: sw $2, 84($1)
38 ; O32-NEXT: sw $2, 80($1)
39 ; O32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
40 ; O32-NEXT: jr $ra
41 ; O32-NEXT: addiu $sp, $sp, 24
42 ;
43 ; N32-LABEL: caller:
44 ; N32: # %bb.0:
45 ; N32-NEXT: addiu $sp, $sp, -16
46 ; N32-NEXT: .cfi_def_cfa_offset 16
47 ; N32-NEXT: sd $ra, 8($sp) # 8-byte Folded Spill
48 ; N32-NEXT: .cfi_offset 31, -8
49 ; N32-NEXT: lui $1, %hi(callee)
50 ; N32-NEXT: addiu $25, $1, %lo(callee)
51 ; N32-NEXT: jalr.hb $25
52 ; N32-NEXT: nop
53 ; N32-NEXT: lui $1, %hi(val)
54 ; N32-NEXT: addiu $1, $1, %lo(val)
55 ; N32-NEXT: lui $2, 1285
56 ; N32-NEXT: daddiu $2, $2, 1285
57 ; N32-NEXT: dsll $2, $2, 16
58 ; N32-NEXT: daddiu $2, $2, 1285
59 ; N32-NEXT: dsll $2, $2, 20
60 ; N32-NEXT: daddiu $2, $2, 20560
61 ; N32-NEXT: sdl $2, 88($1)
62 ; N32-NEXT: sdl $2, 80($1)
63 ; N32-NEXT: lui $3, 20560
64 ; N32-NEXT: ori $3, $3, 20560
65 ; N32-NEXT: sw $3, 96($1)
66 ; N32-NEXT: sdr $2, 95($1)
67 ; N32-NEXT: sdr $2, 87($1)
68 ; N32-NEXT: ld $ra, 8($sp) # 8-byte Folded Reload
69 ; N32-NEXT: jr $ra
70 ; N32-NEXT: addiu $sp, $sp, 16
71 ;
72 ; N64-LABEL: caller:
73 ; N64: # %bb.0:
74 ; N64-NEXT: daddiu $sp, $sp, -16
75 ; N64-NEXT: .cfi_def_cfa_offset 16
76 ; N64-NEXT: sd $ra, 8($sp) # 8-byte Folded Spill
77 ; N64-NEXT: .cfi_offset 31, -8
78 ; N64-NEXT: lui $1, %highest(callee)
79 ; N64-NEXT: daddiu $1, $1, %higher(callee)
80 ; N64-NEXT: dsll $1, $1, 16
81 ; N64-NEXT: daddiu $1, $1, %hi(callee)
82 ; N64-NEXT: dsll $1, $1, 16
83 ; N64-NEXT: daddiu $25, $1, %lo(callee)
84 ; N64-NEXT: jalr.hb $25
85 ; N64-NEXT: nop
86 ; N64-NEXT: lui $1, %highest(val)
87 ; N64-NEXT: daddiu $1, $1, %higher(val)
88 ; N64-NEXT: dsll $1, $1, 16
89 ; N64-NEXT: daddiu $1, $1, %hi(val)
90 ; N64-NEXT: dsll $1, $1, 16
91 ; N64-NEXT: daddiu $1, $1, %lo(val)
92 ; N64-NEXT: lui $2, 1285
93 ; N64-NEXT: daddiu $2, $2, 1285
94 ; N64-NEXT: dsll $2, $2, 16
95 ; N64-NEXT: daddiu $2, $2, 1285
96 ; N64-NEXT: dsll $2, $2, 20
97 ; N64-NEXT: daddiu $2, $2, 20560
98 ; N64-NEXT: lui $3, 20560
99 ; N64-NEXT: sdl $2, 88($1)
100 ; N64-NEXT: sdl $2, 80($1)
101 ; N64-NEXT: ori $3, $3, 20560
102 ; N64-NEXT: sw $3, 96($1)
103 ; N64-NEXT: sdr $2, 95($1)
104 ; N64-NEXT: sdr $2, 87($1)
105 ; N64-NEXT: ld $ra, 8($sp) # 8-byte Folded Reload
106 ; N64-NEXT: jr $ra
107 ; N64-NEXT: daddiu $sp, $sp, 16
108 call void @callee()
109 call void @llvm.memset.p0i8.i32(i8* bitcast (i32* getelementptr inbounds ([20 x i32], [20 x i32]* @val, i64 1, i32 0) to i8*), i8 80, i32 20, i32 4, i1 false)
110 ret void
111 }
112
0 ; RUN: not llc -mtriple=mips-unknown-linux -mcpu=mips32r2 -mattr=+micromips,+use-indirect-jump-hazard %s 2>&1 | FileCheck %s
1
2 ; Test that microMIPS and indirect jump with hazard barriers is not supported.
3
4 ; CHECK: LLVM ERROR: cannot combine indirect jumps with hazard barriers and microMIPS
0 ; RUN: not llc -mtriple=mips-unknown-linux -mcpu=mips32 -mattr=+use-indirect-jump-hazard %s 2>&1 | FileCheck %s
1
2 ; Test that mips32 and indirect jump with hazard barriers is not supported.
3
4 ; CHECK: LLVM ERROR: indirect jumps with hazard barriers requires MIPS32R2 or later