llvm.org GIT mirror llvm / 845b189
Avoid creating an extract element to an illegal type after LegalizeTypes has run. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149548 91177308-0d34-0410-b5e6-96231b3b80d8 Mon P Wang 7 years ago
2 changed file(s) with 30 addition(s) and 2 deletion(s). Raw diff Collapse all Expand all
1360313603 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts
1360413604 /// when possible.
1360513605 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
13606 TargetLowering::DAGCombinerInfo &DCI,
1360613607 const X86Subtarget *Subtarget) {
1360713608 EVT VT = N->getValueType(0);
1360813609 if (N->getOpcode() == ISD::SHL) {
1366613667 BaseShAmt = InVec.getOperand(1);
1366713668 }
1366813669 }
13669 if (BaseShAmt.getNode() == 0)
13670 if (BaseShAmt.getNode() == 0) {
13671 // Don't create instructions with illegal types after legalize
13672 // types has run.
13673 if (!DAG.getTargetLoweringInfo().isTypeLegal(EltVT) &&
13674 !DCI.isBeforeLegalize())
13675 return SDValue();
13676
1367013677 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
1367113678 DAG.getIntPtrConstant(0));
13679 }
1367213680 } else
1367313681 return SDValue();
1367413682
1483214840 case ISD::MUL: return PerformMulCombine(N, DAG, DCI);
1483314841 case ISD::SHL:
1483414842 case ISD::SRA:
14835 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget);
14843 case ISD::SRL: return PerformShiftCombine(N, DAG, DCI, Subtarget);
1483614844 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
1483714845 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
1483814846 case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
0 ; RUN: llc -march=x86 < %s | FileCheck %s
1
2 ; Make sure that we don't generate an illegal i64 extract after LegalizeType.
3 ; CHECK: shll
4
5
6 define void @test_cl(<4 x i64>* %dst, <4 x i64>* %src, i32 %idx) {
7 entry:
8 %arrayidx = getelementptr inbounds <4 x i64> * %src, i32 %idx
9 %0 = load <4 x i64> * %arrayidx, align 32
10 %arrayidx1 = getelementptr inbounds <4 x i64> * %dst, i32 %idx
11 %1 = load <4 x i64> * %arrayidx1, align 32
12 %2 = extractelement <4 x i64> %1, i32 0
13 %and = and i64 %2, 63
14 %3 = insertelement <4 x i64> undef, i64 %and, i32 0
15 %splat = shufflevector <4 x i64> %3, <4 x i64> undef, <4 x i32> zeroinitializer
16 %shl = shl <4 x i64> %0, %splat
17 store <4 x i64> %shl, <4 x i64> * %arrayidx1, align 32
18 ret void
19 }