llvm.org GIT mirror llvm / 843ee2e
Added TargetPassConfig. The first little step toward configuring codegen passes. Allows command line overrides to be centralized in LLVMTargetMachine.cpp. LLVMTargetMachine can intercept common passes and give precedence to command line overrides. Allows adding "internal" target configuration options without touching TargetOptions. Encapsulates the PassManager. Provides a good point to initialize all CodeGen passes so that Pass ID's can be used in APIs. Allows modifying the target configuration hooks without rebuilding the world. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149672 91177308-0d34-0410-b5e6-96231b3b80d8 Andrew Trick 8 years ago
25 changed file(s) with 569 addition(s) and 272 deletion(s). Raw diff Collapse all Expand all
2525 class TargetLowering;
2626 class TargetRegisterClass;
2727 class raw_ostream;
28
28 }
29
30 namespace llvm {
31
32 /// Target-Independent Code Generator Pass Configuration Options.
33 ///
34 /// FIXME: Why are we passing the DisableVerify flags around instead of setting
35 /// an options in the target machine, like all the other driver options?
36 class TargetPassConfig {
37 protected:
38 TargetMachine *TM;
39 PassManagerBase ±
40 bool DisableVerify;
41
42 public:
43 TargetPassConfig(TargetMachine *tm, PassManagerBase &pm,
44 bool DisableVerifyFlag)
45 : TM(tm), PM(pm), DisableVerify(DisableVerifyFlag) {}
46
47 virtual ~TargetPassConfig() {}
48
49 /// Get the right type of TargetMachine for this target.
50 template TMC &getTM() const {
51 return *static_cast(TM);
52 }
53
54 CodeGenOpt::Level getOptLevel() const { return TM->getOptLevel(); }
55
56 const TargetLowering *getTargetLowering() const { return TM->getTargetLowering(); }
57
58 /// Add the complete, standard set of LLVM CodeGen passes.
59 /// Fully developed targets will not generally override this.
60 virtual bool addCodeGenPasses(MCContext *&OutContext);
61
62 protected:
63 /// Convenient points in the common codegen pass pipeline for inserting
64 /// passes, and major CodeGen stages that some targets may override.
65 ///
66
67 /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
68 /// passes (which are run just before instruction selector).
69 virtual bool addPreISel() {
70 return true;
71 }
72
73 /// addInstSelector - This method should install an instruction selector pass,
74 /// which converts from LLVM code to machine instructions.
75 virtual bool addInstSelector() {
76 return true;
77 }
78
79 /// addPreRegAlloc - This method may be implemented by targets that want to
80 /// run passes immediately before register allocation. This should return
81 /// true if -print-machineinstrs should print after these passes.
82 virtual bool addPreRegAlloc() {
83 return false;
84 }
85
86 /// addPostRegAlloc - This method may be implemented by targets that want
87 /// to run passes after register allocation but before prolog-epilog
88 /// insertion. This should return true if -print-machineinstrs should print
89 /// after these passes.
90 virtual bool addPostRegAlloc() {
91 return false;
92 }
93
94 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge
95 /// on this target. User flag overrides.
96 virtual bool getEnableTailMergeDefault() const { return true; }
97
98 /// addPreSched2 - This method may be implemented by targets that want to
99 /// run passes after prolog-epilog insertion and before the second instruction
100 /// scheduling pass. This should return true if -print-machineinstrs should
101 /// print after these passes.
102 virtual bool addPreSched2() {
103 return false;
104 }
105
106 /// addPreEmitPass - This pass may be implemented by targets that want to run
107 /// passes immediately before machine code is emitted. This should return
108 /// true if -print-machineinstrs should print out the code after the passes.
109 virtual bool addPreEmitPass() {
110 return false;
111 }
112
113 /// Utilities for targets to add passes to the pass manager.
114 ///
115
116 /// Add a target-independent CodeGen pass at this point in the pipeline.
117 void addCommonPass(char &ID);
118
119 /// printNoVerify - Add a pass to dump the machine function, if debugging is
120 /// enabled.
121 ///
122 void printNoVerify(const char *Banner) const;
123
124 /// printAndVerify - Add a pass to dump then verify the machine function, if
125 /// those steps are enabled.
126 ///
127 void printAndVerify(const char *Banner) const;
128 };
129 } // namespace llvm
130
131 /// List of target independent CodeGen pass IDs.
132 namespace llvm {
29133 /// createUnreachableBlockEliminationPass - The LLVM code generator does not
30134 /// work well with unreachable basic blocks (what live ranges make sense for a
31135 /// block that cannot be reached?). As such, a code generator should either
3737 class TargetIntrinsicInfo;
3838 class TargetJITInfo;
3939 class TargetLowering;
40 class TargetPassConfig;
4041 class TargetRegisterInfo;
4142 class TargetSelectionDAGInfo;
4243 class TargetSubtargetInfo;
199200 /// Default, or Aggressive.
200201 CodeGenOpt::Level getOptLevel() const;
201202
203 void setFastISel(bool Enable) { Options.EnableFastISel = Enable; }
204
205 bool shouldPrintMachineCode() const { return Options.PrintMachineCode; }
206
202207 /// getAsmVerbosityDefault - Returns the default value of asm verbosity.
203208 ///
204209 static bool getAsmVerbosityDefault();
230235 CGFT_ObjectFile,
231236 CGFT_Null // Do not emit any output.
232237 };
233
234 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge
235 /// on this target. User flag overrides.
236 virtual bool getEnableTailMergeDefault() const { return true; }
237238
238239 /// addPassesToEmitFile - Add passes to the specified pass manager to get the
239240 /// specified file emitted. Typically this will involve several steps of code
281282 Reloc::Model RM, CodeModel::Model CM,
282283 CodeGenOpt::Level OL);
283284
284 /// printNoVerify - Add a pass to dump the machine function, if debugging is
285 /// enabled.
286 ///
287 void printNoVerify(PassManagerBase &PM, const char *Banner) const;
288
289 /// printAndVerify - Add a pass to dump then verify the machine function, if
290 /// those steps are enabled.
291 ///
292 void printAndVerify(PassManagerBase &PM, const char *Banner) const;
293
294 private:
295 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
296 /// both emitting to assembly files or machine code output.
297 ///
298 bool addCommonCodeGenPasses(PassManagerBase &,
299 bool DisableVerify, MCContext *&OutCtx);
300
301285 public:
286 /// createPassConfig - Create a pass configuration object to be used by
287 /// addPassToEmitX methods for generating a pipeline of CodeGen passes.
288 virtual TargetPassConfig *createPassConfig(PassManagerBase &PM,
289 bool DisableVerify);
290
302291 /// addPassesToEmitFile - Add passes to the specified pass manager to get the
303292 /// specified file emitted. Typically this will involve several steps of code
304293 /// generation.
327316 raw_ostream &OS,
328317 bool DisableVerify = true);
329318
330 /// Target-Independent Code Generator Pass Configuration Options.
331
332 /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
333 /// passes (which are run just before instruction selector).
334 virtual bool addPreISel(PassManagerBase &) {
335 return true;
336 }
337
338 /// addInstSelector - This method should install an instruction selector pass,
339 /// which converts from LLVM code to machine instructions.
340 virtual bool addInstSelector(PassManagerBase &) {
341 return true;
342 }
343
344 /// addPreRegAlloc - This method may be implemented by targets that want to
345 /// run passes immediately before register allocation. This should return
346 /// true if -print-machineinstrs should print after these passes.
347 virtual bool addPreRegAlloc(PassManagerBase &) {
348 return false;
349 }
350
351 /// addPostRegAlloc - This method may be implemented by targets that want
352 /// to run passes after register allocation but before prolog-epilog
353 /// insertion. This should return true if -print-machineinstrs should print
354 /// after these passes.
355 virtual bool addPostRegAlloc(PassManagerBase &) {
356 return false;
357 }
358
359 /// addPreSched2 - This method may be implemented by targets that want to
360 /// run passes after prolog-epilog insertion and before the second instruction
361 /// scheduling pass. This should return true if -print-machineinstrs should
362 /// print after these passes.
363 virtual bool addPreSched2(PassManagerBase &) {
364 return false;
365 }
366
367 /// addPreEmitPass - This pass may be implemented by targets that want to run
368 /// passes immediately before machine code is emitted. This should return
369 /// true if -print-machineinstrs should print out the code after the passes.
370 virtual bool addPreEmitPass(PassManagerBase &) {
371 return false;
372 }
373
374
375319 /// addCodeEmitter - This pass should be overridden by the target to add a
376320 /// code emitter, if supported. If this is not supported, 'true' should be
377321 /// returned.
379323 JITCodeEmitter &) {
380324 return true;
381325 }
382
383 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge
384 /// on this target. User flag overrides.
385 virtual bool getEnableTailMergeDefault() const { return true; }
386326 };
387327
388328 } // End llvm namespace
124124 "and that InitializeAllTargetMCs() is being invoked!");
125125 }
126126
127 /// createPassConfig - Create a pass configuration object to be used by
128 /// addPassToEmitX methods for generating a pipeline of CodeGen passes.
129 TargetPassConfig *LLVMTargetMachine::createPassConfig(PassManagerBase &PM,
130 bool DisableVerify) {
131 return new TargetPassConfig(this, PM, DisableVerify);
132 }
133
127134 bool LLVMTargetMachine::addPassesToEmitFile(PassManagerBase &PM,
128135 formatted_raw_ostream &Out,
129136 CodeGenFileType FileType,
130137 bool DisableVerify) {
131138 // Add common CodeGen passes.
132139 MCContext *Context = 0;
133 if (addCommonCodeGenPasses(PM, DisableVerify, Context))
140 OwningPtr PassConfig(createPassConfig(PM, DisableVerify));
141 if (PassConfig->addCodeGenPasses(Context))
134142 return true;
135143 assert(Context != 0 && "Failed to get MCContext");
136144
214222 bool DisableVerify) {
215223 // Add common CodeGen passes.
216224 MCContext *Ctx = 0;
217 if (addCommonCodeGenPasses(PM, DisableVerify, Ctx))
225 OwningPtr PassConfig(createPassConfig(PM, DisableVerify));
226 if (PassConfig->addCodeGenPasses(Ctx))
218227 return true;
219228
220229 addCodeEmitter(PM, JCE);
233242 raw_ostream &Out,
234243 bool DisableVerify) {
235244 // Add common CodeGen passes.
236 if (addCommonCodeGenPasses(PM, DisableVerify, Ctx))
245 OwningPtr PassConfig(createPassConfig(PM, DisableVerify));
246 if (PassConfig->addCodeGenPasses(Ctx))
237247 return true;
238248
239249 if (hasMCSaveTempLabels())
267277 return false; // success!
268278 }
269279
270 void LLVMTargetMachine::printNoVerify(PassManagerBase &PM,
271 const char *Banner) const {
272 if (Options.PrintMachineCode)
280 void TargetPassConfig::printNoVerify(const char *Banner) const {
281 if (TM->shouldPrintMachineCode())
273282 PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
274283 }
275284
276 void LLVMTargetMachine::printAndVerify(PassManagerBase &PM,
277 const char *Banner) const {
278 if (Options.PrintMachineCode)
285 void TargetPassConfig::printAndVerify(const char *Banner) const {
286 if (TM->shouldPrintMachineCode())
279287 PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
280288
281289 if (VerifyMachineCode)
282290 PM.add(createMachineVerifierPass(Banner));
283291 }
284292
285 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for both
293 /// addCodeGenPasses - Add standard LLVM codegen passes used for both
286294 /// emitting to assembly files or machine code output.
287295 ///
288 bool LLVMTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
289 bool DisableVerify,
290 MCContext *&OutContext) {
296 bool TargetPassConfig::addCodeGenPasses(MCContext *&OutContext) {
291297 // Standard LLVM-Level Passes.
292298
293299 // Basic AliasAnalysis support.
316322
317323 // Turn exception handling constructs into something the code generators can
318324 // handle.
319 switch (getMCAsmInfo()->getExceptionHandlingType()) {
325 switch (TM->getMCAsmInfo()->getExceptionHandlingType()) {
320326 case ExceptionHandling::SjLj:
321327 // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
322328 // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
329335 case ExceptionHandling::DwarfCFI:
330336 case ExceptionHandling::ARM:
331337 case ExceptionHandling::Win64:
332 PM.add(createDwarfEHPass(this));
338 PM.add(createDwarfEHPass(TM));
333339 break;
334340 case ExceptionHandling::None:
335341 PM.add(createLowerInvokePass(getTargetLowering()));
344350
345351 PM.add(createStackProtectorPass(getTargetLowering()));
346352
347 addPreISel(PM);
353 addPreISel();
348354
349355 if (PrintISelInput)
350356 PM.add(createPrintFunctionPass("\n\n"
361367 // Install a MachineModuleInfo class, which is an immutable pass that holds
362368 // all the per-module stuff we're generating, including MCContext.
363369 MachineModuleInfo *MMI =
364 new MachineModuleInfo(*getMCAsmInfo(), *getRegisterInfo(),
370 new MachineModuleInfo(*TM->getMCAsmInfo(), *TM->getRegisterInfo(),
365371 &getTargetLowering()->getObjFileLowering());
366372 PM.add(MMI);
367373 OutContext = &MMI->getContext(); // Return the MCContext specifically by-ref.
368374
369375 // Set up a MachineFunction for the rest of CodeGen to work on.
370 PM.add(new MachineFunctionAnalysis(*this));
376 PM.add(new MachineFunctionAnalysis(*TM));
371377
372378 // Enable FastISel with -fast, but allow that to be overridden.
373379 if (EnableFastISelOption == cl::BOU_TRUE ||
374380 (getOptLevel() == CodeGenOpt::None &&
375381 EnableFastISelOption != cl::BOU_FALSE))
376 Options.EnableFastISel = true;
382 TM->setFastISel(true);
377383
378384 // Ask the target for an isel.
379 if (addInstSelector(PM))
385 if (addInstSelector())
380386 return true;
381387
382388 // Print the instruction selected machine code...
383 printAndVerify(PM, "After Instruction Selection");
389 printAndVerify("After Instruction Selection");
384390
385391 // Expand pseudo-instructions emitted by ISel.
386392 PM.add(createExpandISelPseudosPass());
388394 // Pre-ra tail duplication.
389395 if (getOptLevel() != CodeGenOpt::None && !DisableEarlyTailDup) {
390396 PM.add(createTailDuplicatePass(true));
391 printAndVerify(PM, "After Pre-RegAlloc TailDuplicate");
397 printAndVerify("After Pre-RegAlloc TailDuplicate");
392398 }
393399
394400 // Optimize PHIs before DCE: removing dead PHI cycles may make more
407413 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
408414 if (!DisableMachineDCE)
409415 PM.add(createDeadMachineInstructionElimPass());
410 printAndVerify(PM, "After codegen DCE pass");
416 printAndVerify("After codegen DCE pass");
411417
412418 if (!DisableMachineLICM)
413419 PM.add(createMachineLICMPass());
415421 PM.add(createMachineCSEPass());
416422 if (!DisableMachineSink)
417423 PM.add(createMachineSinkingPass());
418 printAndVerify(PM, "After Machine LICM, CSE and Sinking passes");
424 printAndVerify("After Machine LICM, CSE and Sinking passes");
419425
420426 PM.add(createPeepholeOptimizerPass());
421 printAndVerify(PM, "After codegen peephole optimization pass");
427 printAndVerify("After codegen peephole optimization pass");
422428 }
423429
424430 // Run pre-ra passes.
425 if (addPreRegAlloc(PM))
426 printAndVerify(PM, "After PreRegAlloc passes");
431 if (addPreRegAlloc())
432 printAndVerify("After PreRegAlloc passes");
427433
428434 // Perform register allocation.
429435 PM.add(createRegisterAllocator(getOptLevel()));
430 printAndVerify(PM, "After Register Allocation");
436 printAndVerify("After Register Allocation");
431437
432438 // Perform stack slot coloring and post-ra machine LICM.
433439 if (getOptLevel() != CodeGenOpt::None) {
440446 if (!DisablePostRAMachineLICM)
441447 PM.add(createMachineLICMPass(false));
442448
443 printAndVerify(PM, "After StackSlotColoring and postra Machine LICM");
449 printAndVerify("After StackSlotColoring and postra Machine LICM");
444450 }
445451
446452 // Run post-ra passes.
447 if (addPostRegAlloc(PM))
448 printAndVerify(PM, "After PostRegAlloc passes");
453 if (addPostRegAlloc())
454 printAndVerify("After PostRegAlloc passes");
449455
450456 // Insert prolog/epilog code. Eliminate abstract frame index references...
451457 PM.add(createPrologEpilogCodeInserter());
452 printAndVerify(PM, "After PrologEpilogCodeInserter");
458 printAndVerify("After PrologEpilogCodeInserter");
453459
454460 // Branch folding must be run after regalloc and prolog/epilog insertion.
455461 if (getOptLevel() != CodeGenOpt::None && !DisableBranchFold) {
456462 PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
457 printNoVerify(PM, "After BranchFolding");
463 printNoVerify("After BranchFolding");
458464 }
459465
460466 // Tail duplication.
461467 if (getOptLevel() != CodeGenOpt::None && !DisableTailDuplicate) {
462468 PM.add(createTailDuplicatePass(false));
463 printNoVerify(PM, "After TailDuplicate");
469 printNoVerify("After TailDuplicate");
464470 }
465471
466472 // Copy propagation.
467473 if (getOptLevel() != CodeGenOpt::None && !DisableCopyProp) {
468474 PM.add(createMachineCopyPropagationPass());
469 printNoVerify(PM, "After copy propagation pass");
475 printNoVerify("After copy propagation pass");
470476 }
471477
472478 // Expand pseudo instructions before second scheduling pass.
473479 PM.add(createExpandPostRAPseudosPass());
474 printNoVerify(PM, "After ExpandPostRAPseudos");
480 printNoVerify("After ExpandPostRAPseudos");
475481
476482 // Run pre-sched2 passes.
477 if (addPreSched2(PM))
478 printNoVerify(PM, "After PreSched2 passes");
483 if (addPreSched2())
484 printNoVerify("After PreSched2 passes");
479485
480486 // Second pass scheduler.
481487 if (getOptLevel() != CodeGenOpt::None && !DisablePostRA) {
482488 PM.add(createPostRAScheduler(getOptLevel()));
483 printNoVerify(PM, "After PostRAScheduler");
489 printNoVerify("After PostRAScheduler");
484490 }
485491
486492 PM.add(createGCMachineCodeAnalysisPass());
494500 // default currently. Eventually it should subsume CodePlacementOpt, so
495501 // when enabled, the other is disabled.
496502 PM.add(createMachineBlockPlacementPass());
497 printNoVerify(PM, "After MachineBlockPlacement");
503 printNoVerify("After MachineBlockPlacement");
498504 } else {
499505 PM.add(createCodePlacementOptPass());
500 printNoVerify(PM, "After CodePlacementOpt");
506 printNoVerify("After CodePlacementOpt");
501507 }
502508
503509 // Run a separate pass to collect block placement statistics.
504510 if (EnableBlockPlacementStats) {
505511 PM.add(createMachineBlockPlacementStatsPass());
506 printNoVerify(PM, "After MachineBlockPlacementStats");
512 printNoVerify("After MachineBlockPlacementStats");
507513 }
508514 }
509515
510 if (addPreEmitPass(PM))
511 printNoVerify(PM, "After PreEmit passes");
516 if (addPreEmitPass())
517 printNoVerify("After PreEmit passes");
512518
513519 return false;
514520 }
106106 : (ARMFrameLowering*)new Thumb1FrameLowering(Subtarget)) {
107107 }
108108
109 bool ARMBaseTargetMachine::addPreISel(PassManagerBase &PM) {
110 if (getOptLevel() != CodeGenOpt::None && EnableGlobalMerge)
111 PM.add(createGlobalMergePass(getTargetLowering()));
109 namespace {
110 /// ARM Code Generator Pass Configuration Options.
111 class ARMPassConfig : public TargetPassConfig {
112 public:
113 ARMPassConfig(ARMBaseTargetMachine *TM, PassManagerBase &PM,
114 bool DisableVerifyFlag)
115 : TargetPassConfig(TM, PM, DisableVerifyFlag) {}
116
117 ARMBaseTargetMachine &getARMTargetMachine() const {
118 return getTM();
119 }
120
121 const ARMSubtarget &getARMSubtarget() const {
122 return *getARMTargetMachine().getSubtargetImpl();
123 }
124
125 virtual bool addPreISel();
126 virtual bool addInstSelector();
127 virtual bool addPreRegAlloc();
128 virtual bool addPreSched2();
129 virtual bool addPreEmitPass();
130 };
131 } // namespace
132
133 TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM,
134 bool DisableVerify) {
135 return new ARMPassConfig(this, PM, DisableVerify);
136 }
137
138 bool ARMPassConfig::addPreISel() {
139 if (TM->getOptLevel() != CodeGenOpt::None && EnableGlobalMerge)
140 PM.add(createGlobalMergePass(TM->getTargetLowering()));
112141
113142 return false;
114143 }
115144
116 bool ARMBaseTargetMachine::addInstSelector(PassManagerBase &PM) {
117 PM.add(createARMISelDag(*this, getOptLevel()));
145 bool ARMPassConfig::addInstSelector() {
146 PM.add(createARMISelDag(getARMTargetMachine(), getOptLevel()));
118147 return false;
119148 }
120149
121 bool ARMBaseTargetMachine::addPreRegAlloc(PassManagerBase &PM) {
150 bool ARMPassConfig::addPreRegAlloc() {
122151 // FIXME: temporarily disabling load / store optimization pass for Thumb1.
123 if (getOptLevel() != CodeGenOpt::None && !Subtarget.isThumb1Only())
152 if (getOptLevel() != CodeGenOpt::None && !getARMSubtarget().isThumb1Only())
124153 PM.add(createARMLoadStoreOptimizationPass(true));
125 if (getOptLevel() != CodeGenOpt::None && Subtarget.isCortexA9())
154 if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA9())
126155 PM.add(createMLxExpansionPass());
127156 return true;
128157 }
129158
130 bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM) {
159 bool ARMPassConfig::addPreSched2() {
131160 // FIXME: temporarily disabling load / store optimization pass for Thumb1.
132161 if (getOptLevel() != CodeGenOpt::None) {
133 if (!Subtarget.isThumb1Only())
162 if (!getARMSubtarget().isThumb1Only())
134163 PM.add(createARMLoadStoreOptimizationPass());
135 if (Subtarget.hasNEON())
164 if (getARMSubtarget().hasNEON())
136165 PM.add(createExecutionDependencyFixPass(&ARM::DPRRegClass));
137166 }
138167
141170 PM.add(createARMExpandPseudoPass());
142171
143172 if (getOptLevel() != CodeGenOpt::None) {
144 if (!Subtarget.isThumb1Only())
173 if (!getARMSubtarget().isThumb1Only())
145174 PM.add(createIfConverterPass());
146175 }
147 if (Subtarget.isThumb2())
176 if (getARMSubtarget().isThumb2())
148177 PM.add(createThumb2ITBlockPass());
149178
150179 return true;
151180 }
152181
153 bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM) {
154 if (Subtarget.isThumb2()) {
155 if (!Subtarget.prefers32BitThumb())
182 bool ARMPassConfig::addPreEmitPass() {
183 if (getARMSubtarget().isThumb2()) {
184 if (!getARMSubtarget().prefers32BitThumb())
156185 PM.add(createThumb2SizeReductionPass());
157186
158187 // Constant island pass work on unbundled instructions.
164193 return true;
165194 }
166195
167 bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM,
168 JITCodeEmitter &JCE) {
196 bool ARMBaseTargetMachine::addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &JCE) {
169197 // Machine code emitter pass for ARM.
170198 PM.add(createARMJITCodeEmitterPass(*this, JCE));
171199 return false;
5151 }
5252
5353 // Pass Pipeline Configuration
54 virtual bool addPreISel(PassManagerBase &PM);
55 virtual bool addInstSelector(PassManagerBase &PM);
56 virtual bool addPreRegAlloc(PassManagerBase &PM);
57 virtual bool addPreSched2(PassManagerBase &PM);
58 virtual bool addPreEmitPass(PassManagerBase &PM);
54 virtual TargetPassConfig *createPassConfig(PassManagerBase &PM, bool DisableVerify);
55
5956 virtual bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &MCE);
6057 };
6158
2020
2121 using namespace llvm;
2222
23 extern "C" void LLVMInitializeCellSPUTarget() {
23 extern "C" void LLVMInitializeCellSPUTarget() {
2424 // Register the target.
2525 RegisterTargetMachine X(TheCellSPUTarget);
2626 }
5050 // Pass Pipeline Configuration
5151 //===----------------------------------------------------------------------===//
5252
53 bool SPUTargetMachine::addInstSelector(PassManagerBase &PM) {
53 namespace {
54 /// SPU Code Generator Pass Configuration Options.
55 class SPUPassConfig : public TargetPassConfig {
56 public:
57 SPUPassConfig(SPUTargetMachine *TM, PassManagerBase &PM,
58 bool DisableVerifyFlag)
59 : TargetPassConfig(TM, PM, DisableVerifyFlag) {}
60
61 SPUTargetMachine &getSPUTargetMachine() const {
62 return getTM();
63 }
64
65 virtual bool addInstSelector();
66 virtual bool addPreEmitPass();
67 };
68 } // namespace
69
70 TargetPassConfig *SPUTargetMachine::createPassConfig(PassManagerBase &PM,
71 bool DisableVerify) {
72 return new SPUPassConfig(this, PM, DisableVerify);
73 }
74
75 bool SPUPassConfig::addInstSelector() {
5476 // Install an instruction selector.
55 PM.add(createSPUISelDag(*this));
77 PM.add(createSPUISelDag(getSPUTargetMachine()));
5678 return false;
5779 }
5880
5981 // passes to run just before printing the assembly
60 bool SPUTargetMachine::
61 addPreEmitPass(PassManagerBase &PM) {
82 bool SPUPassConfig::addPreEmitPass() {
6283 // load the TCE instruction scheduler, if available via
6384 // loaded plugins
6485 typedef llvm::FunctionPass* (*BuilderFunc)(const char*);
6990 PM.add(schedulerCreator("cellspu"));
7091
7192 //align instructions with nops/lnops for dual issue
72 PM.add(createSPUNopFillerPass(*this));
93 PM.add(createSPUNopFillerPass(getSPUTargetMachine()));
7394 return true;
7495 }
6060 return NULL;
6161 }
6262
63 virtual const SPUTargetLowering *getTargetLowering() const {
63 virtual const SPUTargetLowering *getTargetLowering() const {
6464 return &TLInfo;
6565 }
6666
7171 virtual const SPURegisterInfo *getRegisterInfo() const {
7272 return &InstrInfo.getRegisterInfo();
7373 }
74
74
7575 virtual const TargetData *getTargetData() const {
7676 return &DataLayout;
7777 }
7979 virtual const InstrItineraryData *getInstrItineraryData() const {
8080 return &InstrItins;
8181 }
82
82
8383 // Pass Pipeline Configuration
84 virtual bool addInstSelector(PassManagerBase &PM);
85 virtual bool addPreEmitPass(PassManagerBase &);
84 virtual TargetPassConfig *createPassConfig(PassManagerBase &PM,
85 bool DisableVerify);
8686 };
8787
8888 } // end namespace llvm
7575 return true;
7676 }
7777
78 bool HexagonTargetMachine::addInstSelector(PassManagerBase &PM) {
79 PM.add(createHexagonRemoveExtendOps(*this));
80 PM.add(createHexagonISelDag(*this));
78 namespace {
79 /// Hexagon Code Generator Pass Configuration Options.
80 class HexagonPassConfig : public TargetPassConfig {
81 public:
82 HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM,
83 bool DisableVerifyFlag)
84 : TargetPassConfig(TM, PM, DisableVerifyFlag) {}
85
86 HexagonTargetMachine &getHexagonTargetMachine() const {
87 return getTM();
88 }
89
90 virtual bool addInstSelector();
91 virtual bool addPreRegAlloc();
92 virtual bool addPostRegAlloc();
93 virtual bool addPreSched2();
94 virtual bool addPreEmitPass();
95 };
96 } // namespace
97
98 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM,
99 bool DisableVerify) {
100 return new HexagonPassConfig(this, PM, DisableVerify);
101 }
102
103 bool HexagonPassConfig::addInstSelector() {
104 PM.add(createHexagonRemoveExtendOps(getHexagonTargetMachine()));
105 PM.add(createHexagonISelDag(getHexagonTargetMachine()));
81106 return false;
82107 }
83108
84109
85 bool HexagonTargetMachine::addPreRegAlloc(PassManagerBase &PM) {
110 bool HexagonPassConfig::addPreRegAlloc() {
86111 if (!DisableHardwareLoops) {
87112 PM.add(createHexagonHardwareLoops());
88113 }
90115 return false;
91116 }
92117
93 bool HexagonTargetMachine::addPostRegAlloc(PassManagerBase &PM) {
94 PM.add(createHexagonCFGOptimizer(*this));
118 bool HexagonPassConfig::addPostRegAlloc() {
119 PM.add(createHexagonCFGOptimizer(getHexagonTargetMachine()));
95120 return true;
96121 }
97122
98123
99 bool HexagonTargetMachine::addPreSched2(PassManagerBase &PM) {
124 bool HexagonPassConfig::addPreSched2() {
100125 PM.add(createIfConverterPass());
101126 return true;
102127 }
103128
104 bool HexagonTargetMachine::addPreEmitPass(PassManagerBase &PM) {
129 bool HexagonPassConfig::addPreEmitPass() {
105130
106131 if (!DisableHardwareLoops) {
107132 PM.add(createHexagonFixupHwLoops());
108133 }
109134
110135 // Expand Spill code for predicate registers.
111 PM.add(createHexagonExpandPredSpillCode(*this));
136 PM.add(createHexagonExpandPredSpillCode(getHexagonTargetMachine()));
112137
113138 // Split up TFRcondsets into conditional transfers.
114 PM.add(createHexagonSplitTFRCondSets(*this));
139 PM.add(createHexagonSplitTFRCondSets(getHexagonTargetMachine()));
115140
116141 return false;
117142 }
7171
7272 // Pass Pipeline Configuration.
7373 virtual bool addPassesForOptimizations(PassManagerBase &PM);
74 virtual bool addInstSelector(PassManagerBase &PM);
75 virtual bool addPreEmitPass(PassManagerBase &PM);
76 virtual bool addPreRegAlloc(llvm::PassManagerBase &PM);
77 virtual bool addPostRegAlloc(PassManagerBase &PM);
78 virtual bool addPreSched2(PassManagerBase &PM);
74 virtual TargetPassConfig *createPassConfig(PassManagerBase &PM,
75 bool DisableVerify);
7976 };
8077
8178 extern bool flag_aligned_memcpy;
4444 InstrItins(Subtarget.getInstrItineraryData()) {
4545 }
4646
47 namespace {
48 /// MBlaze Code Generator Pass Configuration Options.
49 class MBlazePassConfig : public TargetPassConfig {
50 public:
51 MBlazePassConfig(MBlazeTargetMachine *TM, PassManagerBase &PM,
52 bool DisableVerifyFlag)
53 : TargetPassConfig(TM, PM, DisableVerifyFlag) {}
54
55 MBlazeTargetMachine &getMBlazeTargetMachine() const {
56 return getTM();
57 }
58
59 virtual bool addInstSelector();
60 virtual bool addPreEmitPass();
61 };
62 } // namespace
63
64 TargetPassConfig *MBlazeTargetMachine::createPassConfig(PassManagerBase &PM,
65 bool DisableVerify) {
66 return new MBlazePassConfig(this, PM, DisableVerify);
67 }
68
4769 // Install an instruction selector pass using
4870 // the ISelDag to gen MBlaze code.
49 bool MBlazeTargetMachine::addInstSelector(PassManagerBase &PM) {
50 PM.add(createMBlazeISelDag(*this));
71 bool MBlazePassConfig::addInstSelector() {
72 PM.add(createMBlazeISelDag(getMBlazeTargetMachine()));
5173 return false;
5274 }
5375
5476 // Implemented by targets that want to run passes immediately before
5577 // machine code is emitted. return true if -print-machineinstrs should
5678 // print out the code after the passes.
57 bool MBlazeTargetMachine::addPreEmitPass(PassManagerBase &PM) {
58 PM.add(createMBlazeDelaySlotFillerPass(*this));
79 bool MBlazePassConfig::addPreEmitPass() {
80 PM.add(createMBlazeDelaySlotFillerPass(getMBlazeTargetMachine()));
5981 return true;
6082 }
7878 }
7979
8080 // Pass Pipeline Configuration
81 virtual bool addInstSelector(PassManagerBase &PM);
82 virtual bool addPreEmitPass(PassManagerBase &PM);
81 virtual TargetPassConfig *createPassConfig(PassManagerBase &PM,
82 bool DisableVerify);
8383 };
8484 } // End llvm namespace
8585
3737 InstrInfo(*this), TLInfo(*this), TSInfo(*this),
3838 FrameLowering(Subtarget) { }
3939
40 namespace {
41 /// MSP430 Code Generator Pass Configuration Options.
42 class MSP430PassConfig : public TargetPassConfig {
43 public:
44 MSP430PassConfig(MSP430TargetMachine *TM, PassManagerBase &PM,
45 bool DisableVerifyFlag)
46 : TargetPassConfig(TM, PM, DisableVerifyFlag) {}
4047
41 bool MSP430TargetMachine::addInstSelector(PassManagerBase &PM) {
48 MSP430TargetMachine &getMSP430TargetMachine() const {
49 return getTM();
50 }
51
52 virtual bool addInstSelector();
53 virtual bool addPreEmitPass();
54 };
55 } // namespace
56
57 TargetPassConfig *MSP430TargetMachine::createPassConfig(PassManagerBase &PM,
58 bool DisableVerify) {
59 return new MSP430PassConfig(this, PM, DisableVerify);
60 }
61
62 bool MSP430PassConfig::addInstSelector() {
4263 // Install an instruction selector.
43 PM.add(createMSP430ISelDag(*this, getOptLevel()));
64 PM.add(createMSP430ISelDag(getMSP430TargetMachine(), getOptLevel()));
4465 return false;
4566 }
4667
47 bool MSP430TargetMachine::addPreEmitPass(PassManagerBase &PM) {
68 bool MSP430PassConfig::addPreEmitPass() {
4869 // Must run branch selection immediately preceding the asm printer.
4970 PM.add(createMSP430BranchSelectionPass());
5071 return false;
6161 return &TSInfo;
6262 }
6363
64 virtual bool addInstSelector(PassManagerBase &PM);
65 virtual bool addPreEmitPass(PassManagerBase &PM);
64 virtual TargetPassConfig *createPassConfig(PassManagerBase &PM,
65 bool DisableVerify);
6666 }; // MSP430TargetMachine.
6767
6868 } // end namespace llvm
1313 #include "Mips.h"
1414 #include "MipsTargetMachine.h"
1515 #include "llvm/PassManager.h"
16 #include "llvm/CodeGen/Passes.h"
1617 #include "llvm/Support/TargetRegistry.h"
1718 using namespace llvm;
1819
8788 CodeGenOpt::Level OL)
8889 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
8990
91 namespace {
92 /// Mips Code Generator Pass Configuration Options.
93 class MipsPassConfig : public TargetPassConfig {
94 public:
95 MipsPassConfig(MipsTargetMachine *TM, PassManagerBase &PM,
96 bool DisableVerifyFlag)
97 : TargetPassConfig(TM, PM, DisableVerifyFlag) {}
98
99 MipsTargetMachine &getMipsTargetMachine() const {
100 return getTM();
101 }
102
103 const MipsSubtarget &getMipsSubtarget() const {
104 return *getMipsTargetMachine().getSubtargetImpl();
105 }
106
107 virtual bool addInstSelector();
108 virtual bool addPreRegAlloc();
109 virtual bool addPostRegAlloc();
110 virtual bool addPreEmitPass();
111 };
112 } // namespace
113
114 TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM,
115 bool DisableVerify) {
116 return new MipsPassConfig(this, PM, DisableVerify);
117 }
118
90119 // Install an instruction selector pass using
91120 // the ISelDag to gen Mips code.
92 bool MipsTargetMachine::
93 addInstSelector(PassManagerBase &PM)
121 bool MipsPassConfig::addInstSelector()
94122 {
95 PM.add(createMipsISelDag(*this));
123 PM.add(createMipsISelDag(getMipsTargetMachine()));
96124 return false;
97125 }
98126
99127 // Implemented by targets that want to run passes immediately before
100128 // machine code is emitted. return true if -print-machineinstrs should
101129 // print out the code after the passes.
102 bool MipsTargetMachine::
103 addPreEmitPass(PassManagerBase &PM)
130 bool MipsPassConfig::addPreEmitPass()
104131 {
105 PM.add(createMipsDelaySlotFillerPass(*this));
132 PM.add(createMipsDelaySlotFillerPass(getMipsTargetMachine()));
106133 return true;
107134 }
108135
109 bool MipsTargetMachine::
110 addPreRegAlloc(PassManagerBase &PM) {
136 bool MipsPassConfig::addPreRegAlloc() {
111137 // Do not restore $gp if target is Mips64.
112138 // In N32/64, $gp is a callee-saved register.
113 if (!Subtarget.hasMips64())
114 PM.add(createMipsEmitGPRestorePass(*this));
139 if (!getMipsSubtarget().hasMips64())
140 PM.add(createMipsEmitGPRestorePass(getMipsTargetMachine()));
115141 return true;
116142 }
117143
118 bool MipsTargetMachine::
119 addPostRegAlloc(PassManagerBase &PM) {
120 PM.add(createMipsExpandPseudoPass(*this));
144 bool MipsPassConfig::addPostRegAlloc() {
145 PM.add(createMipsExpandPseudoPass(getMipsTargetMachine()));
121146 return true;
122147 }
123148
6767 }
6868
6969 // Pass Pipeline Configuration
70 virtual bool addInstSelector(PassManagerBase &PM);
71 virtual bool addPreEmitPass(PassManagerBase &PM);
72 virtual bool addPreRegAlloc(PassManagerBase &PM);
73 virtual bool addPostRegAlloc(PassManagerBase &);
70 virtual TargetPassConfig *createPassConfig(PassManagerBase &PM,
71 bool DisableVerify);
7472 virtual bool addCodeEmitter(PassManagerBase &PM,
7573 JITCodeEmitter &JCE);
7674
104104 : PTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
105105 }
106106
107 bool PTXTargetMachine::addInstSelector(PassManagerBase &PM) {
108 PM.add(createPTXISelDag(*this, getOptLevel()));
107 namespace {
108 /// PTX Code Generator Pass Configuration Options.
109 class PTXPassConfig : public TargetPassConfig {
110 public:
111 PTXPassConfig(PTXTargetMachine *TM, PassManagerBase &PM, bool DisableVerifyFlag)
112 : TargetPassConfig(TM, PM, DisableVerifyFlag) {}
113
114 PTXTargetMachine &getPTXTargetMachine() const {
115 return getTM();
116 }
117
118 bool addInstSelector();
119 bool addPostRegAlloc();
120 bool addCodeGenPasses(MCContext *&OutContext);
121 };
122 } // namespace
123
124 TargetPassConfig *PTXTargetMachine::createPassConfig(PassManagerBase &PM,
125 bool DisableVerify) {
126 return new PTXPassConfig(this, PM, DisableVerify);
127 }
128
129 bool PTXPassConfig::addInstSelector() {
130 PM.add(createPTXISelDag(getPTXTargetMachine(), getOptLevel()));
109131 return false;
110132 }
111133
112 bool PTXTargetMachine::addPostRegAlloc(PassManagerBase &PM) {
134 bool PTXPassConfig::addPostRegAlloc() {
113135 // PTXMFInfoExtract must after register allocation!
114 //PM.add(createPTXMFInfoExtract(*this));
136 //PM.add(createPTXMFInfoExtract(getPTXTargetMachine()));
115137 return false;
116138 }
117139
123145
124146 // Add common CodeGen passes.
125147 MCContext *Context = 0;
126 if (addCommonCodeGenPasses(PM, DisableVerify, Context))
148 OwningPtr PassConfig(createPassConfig(PM, DisableVerify));
149 if (PassConfig->addCodeGenPasses(Context))
127150 return true;
128151 assert(Context != 0 && "Failed to get MCContext");
129152
178201 return false;
179202 }
180203
181 bool PTXTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM,
182 bool DisableVerify,
183 MCContext *&OutContext) {
204 bool PTXPassConfig::addCodeGenPasses(MCContext *&OutContext) {
184205 // Add standard LLVM codegen passes.
185206 // This is derived from LLVMTargetMachine::addCommonCodeGenPasses, with some
186207 // modifications for the PTX target.
219240
220241 PM.add(createStackProtectorPass(getTargetLowering()));
221242
222 addPreISel(PM);
243 addPreISel();
223244
224245 //PM.add(createPrintFunctionPass("\n\n"
225246 // "*** Final LLVM Code input to ISel ***\n",
234255
235256 // Install a MachineModuleInfo class, which is an immutable pass that holds
236257 // all the per-module stuff we're generating, including MCContext.
237 MachineModuleInfo *MMI = new MachineModuleInfo(*getMCAsmInfo(),
238 *getRegisterInfo(),
258 MachineModuleInfo *MMI = new MachineModuleInfo(*TM->getMCAsmInfo(),
259 *TM->getRegisterInfo(),
239260 &getTargetLowering()->getObjFileLowering());
240261 PM.add(MMI);
241262 OutContext = &MMI->getContext(); // Return the MCContext specifically by-ref.
242263
243264 // Set up a MachineFunction for the rest of CodeGen to work on.
244 PM.add(new MachineFunctionAnalysis(*this));
265 PM.add(new MachineFunctionAnalysis(*TM));
245266
246267 // Ask the target for an isel.
247 if (addInstSelector(PM))
268 if (addInstSelector())
248269 return true;
249270
250271 // Print the instruction selected machine code...
251 printAndVerify(PM, "After Instruction Selection");
272 printAndVerify("After Instruction Selection");
252273
253274 // Expand pseudo-instructions emitted by ISel.
254275 PM.add(createExpandISelPseudosPass());
256277 // Pre-ra tail duplication.
257278 if (getOptLevel() != CodeGenOpt::None) {
258279 PM.add(createTailDuplicatePass(true));
259 printAndVerify(PM, "After Pre-RegAlloc TailDuplicate");
280 printAndVerify("After Pre-RegAlloc TailDuplicate");
260281 }
261282
262283 // Optimize PHIs before DCE: removing dead PHI cycles may make more
274295 // used by tail calls, where the tail calls reuse the incoming stack
275296 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
276297 PM.add(createDeadMachineInstructionElimPass());
277 printAndVerify(PM, "After codegen DCE pass");
298 printAndVerify("After codegen DCE pass");
278299
279300 PM.add(createMachineLICMPass());
280301 PM.add(createMachineCSEPass());
281302 PM.add(createMachineSinkingPass());
282 printAndVerify(PM, "After Machine LICM, CSE and Sinking passes");
303 printAndVerify("After Machine LICM, CSE and Sinking passes");
283304
284305 PM.add(createPeepholeOptimizerPass());
285 printAndVerify(PM, "After codegen peephole optimization pass");
306 printAndVerify("After codegen peephole optimization pass");
286307 }
287308
288309 // Run pre-ra passes.
289 if (addPreRegAlloc(PM))
290 printAndVerify(PM, "After PreRegAlloc passes");
310 if (addPreRegAlloc())
311 printAndVerify("After PreRegAlloc passes");
291312
292313 // Perform register allocation.
293314 PM.add(createPTXRegisterAllocator());
294 printAndVerify(PM, "After Register Allocation");
315 printAndVerify("After Register Allocation");
295316
296317 // Perform stack slot coloring and post-ra machine LICM.
297318 if (getOptLevel() != CodeGenOpt::None) {
304325 //if (!DisablePostRAMachineLICM)
305326 // PM.add(createMachineLICMPass(false));
306327
307 printAndVerify(PM, "After StackSlotColoring and postra Machine LICM");
328 printAndVerify("After StackSlotColoring and postra Machine LICM");
308329 }
309330
310331 // Run post-ra passes.
311 if (addPostRegAlloc(PM))
312 printAndVerify(PM, "After PostRegAlloc passes");
332 if (addPostRegAlloc())
333 printAndVerify("After PostRegAlloc passes");
313334
314335 PM.add(createExpandPostRAPseudosPass());
315 printAndVerify(PM, "After ExpandPostRAPseudos");
336 printAndVerify("After ExpandPostRAPseudos");
316337
317338 // Insert prolog/epilog code. Eliminate abstract frame index references...
318339 PM.add(createPrologEpilogCodeInserter());
319 printAndVerify(PM, "After PrologEpilogCodeInserter");
340 printAndVerify("After PrologEpilogCodeInserter");
320341
321342 // Run pre-sched2 passes.
322 if (addPreSched2(PM))
323 printAndVerify(PM, "After PreSched2 passes");
343 if (addPreSched2())
344 printAndVerify("After PreSched2 passes");
324345
325346 // Second pass scheduler.
326347 if (getOptLevel() != CodeGenOpt::None) {
327348 PM.add(createPostRAScheduler(getOptLevel()));
328 printAndVerify(PM, "After PostRAScheduler");
349 printAndVerify("After PostRAScheduler");
329350 }
330351
331352 // Branch folding must be run after regalloc and prolog/epilog insertion.
332353 if (getOptLevel() != CodeGenOpt::None) {
333354 PM.add(createBranchFoldingPass(getEnableTailMergeDefault()));
334 printNoVerify(PM, "After BranchFolding");
355 printNoVerify("After BranchFolding");
335356 }
336357
337358 // Tail duplication.
338359 if (getOptLevel() != CodeGenOpt::None) {
339360 PM.add(createTailDuplicatePass(false));
340 printNoVerify(PM, "After TailDuplicate");
361 printNoVerify("After TailDuplicate");
341362 }
342363
343364 PM.add(createGCMachineCodeAnalysisPass());
347368
348369 if (getOptLevel() != CodeGenOpt::None) {
349370 PM.add(createCodePlacementOptPass());
350 printNoVerify(PM, "After CodePlacementOpt");
351 }
352
353 if (addPreEmitPass(PM))
354 printNoVerify(PM, "After PreEmit passes");
355
356 PM.add(createPTXMFInfoExtract(*this, getOptLevel()));
357 PM.add(createPTXFPRoundingModePass(*this, getOptLevel()));
371 printNoVerify("After CodePlacementOpt");
372 }
373
374 if (addPreEmitPass())
375 printNoVerify("After PreEmit passes");
376
377 PM.add(createPTXMFInfoExtract(getPTXTargetMachine(), getOptLevel()));
378 PM.add(createPTXFPRoundingModePass(getPTXTargetMachine(), getOptLevel()));
358379
359380 return false;
360381 }
5858
5959 virtual const PTXSubtarget *getSubtargetImpl() const { return &Subtarget; }
6060
61 virtual bool addInstSelector(PassManagerBase &PM);
62 virtual bool addPostRegAlloc(PassManagerBase &PM);
63
6461 // We override this method to supply our own set of codegen passes.
6562 virtual bool addPassesToEmitFile(PassManagerBase &,
6663 formatted_raw_ostream &,
8279 return true;
8380 }
8481
85 private:
86
87 bool addCommonCodeGenPasses(PassManagerBase &,
88 bool DisableVerify, MCContext *&OutCtx);
82 // Pass Pipeline Configuration
83 virtual TargetPassConfig *createPassConfig(PassManagerBase &PM,
84 bool DisableVerify);
8985 }; // class PTXTargetMachine
9086
9187
1414 #include "PPCTargetMachine.h"
1515 #include "llvm/PassManager.h"
1616 #include "llvm/MC/MCStreamer.h"
17 #include "llvm/CodeGen/Passes.h"
1718 #include "llvm/Target/TargetOptions.h"
1819 #include "llvm/Support/FormattedStream.h"
1920 #include "llvm/Support/TargetRegistry.h"
3839 TLInfo(*this), TSInfo(*this),
3940 InstrItins(Subtarget.getInstrItineraryData()) {
4041 }
41
42 /// Override this for PowerPC. Tail merging happily breaks up instruction issue
43 /// groups, which typically degrades performance.
44 bool PPCTargetMachine::getEnableTailMergeDefault() const { return false; }
4542
4643 void PPC32TargetMachine::anchor() { }
4744
6865 // Pass Pipeline Configuration
6966 //===----------------------------------------------------------------------===//
7067
71 bool PPCTargetMachine::addInstSelector(PassManagerBase &PM) {
68 namespace {
69 /// PPC Code Generator Pass Configuration Options.
70 class PPCPassConfig : public TargetPassConfig {
71 public:
72 PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM,
73 bool DisableVerifyFlag)
74 : TargetPassConfig(TM, PM, DisableVerifyFlag) {}
75
76 PPCTargetMachine &getPPCTargetMachine() const {
77 return getTM();
78 }
79
80 virtual bool addInstSelector();
81 virtual bool getEnableTailMergeDefault() const;
82 virtual bool addPreEmitPass();
83 };
84 } // namespace
85
86 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM,
87 bool DisableVerify) {
88 return new PPCPassConfig(this, PM, DisableVerify);
89 }
90
91 bool PPCPassConfig::addInstSelector() {
7292 // Install an instruction selector.
73 PM.add(createPPCISelDag(*this));
93 PM.add(createPPCISelDag(getPPCTargetMachine()));
7494 return false;
7595 }
7696
77 bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM) {
97 /// Override this for PowerPC. Tail merging happily breaks up instruction issue
98 /// groups, which typically degrades performance.
99 bool PPCPassConfig::getEnableTailMergeDefault() const { return false; }
100
101 bool PPCPassConfig::addPreEmitPass() {
78102 // Must run branch selection immediately preceding the asm printer.
79103 PM.add(createPPCBranchSelectionPass());
80104 return false;
6666 }
6767
6868 // Pass Pipeline Configuration
69 virtual bool addInstSelector(PassManagerBase &PM);
70 virtual bool addPreEmitPass(PassManagerBase &PM);
69 virtual TargetPassConfig *createPassConfig(PassManagerBase &PM,
70 bool DisableVerify);
7171 virtual bool addCodeEmitter(PassManagerBase &PM,
7272 JITCodeEmitter &JCE);
73 virtual bool getEnableTailMergeDefault() const;
7473 };
7574
7675 /// PPC32TargetMachine - PowerPC 32-bit target machine.
1212 #include "Sparc.h"
1313 #include "SparcTargetMachine.h"
1414 #include "llvm/PassManager.h"
15 #include "llvm/CodeGen/Passes.h"
1516 #include "llvm/Support/TargetRegistry.h"
1617 using namespace llvm;
1718
2324
2425 /// SparcTargetMachine ctor - Create an ILP32 architecture model
2526 ///
26 SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT,
27 SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT,
2728 StringRef CPU, StringRef FS,
2829 const TargetOptions &Options,
2930 Reloc::Model RM, CodeModel::Model CM,
3637 FrameLowering(Subtarget) {
3738 }
3839
39 bool SparcTargetMachine::addInstSelector(PassManagerBase &PM) {
40 PM.add(createSparcISelDag(*this));
40 namespace {
41 /// Sparc Code Generator Pass Configuration Options.
42 class SparcPassConfig : public TargetPassConfig {
43 public:
44 SparcPassConfig(SparcTargetMachine *TM, PassManagerBase &PM,
45 bool DisableVerifyFlag)
46 : TargetPassConfig(TM, PM, DisableVerifyFlag) {}
47
48 SparcTargetMachine &getSparcTargetMachine() const {
49 return getTM();
50 }
51
52 virtual bool addInstSelector();
53 virtual bool addPreEmitPass();
54 };
55 } // namespace
56
57 TargetPassConfig *SparcTargetMachine::createPassConfig(PassManagerBase &PM,
58 bool DisableVerify) {
59 return new SparcPassConfig(this, PM, DisableVerify);
60 }
61
62 bool SparcPassConfig::addInstSelector() {
63 PM.add(createSparcISelDag(getSparcTargetMachine()));
4164 return false;
4265 }
4366
4467 /// addPreEmitPass - This pass may be implemented by targets that want to run
4568 /// passes immediately before machine code is emitted. This should return
4669 /// true if -print-machineinstrs should print out the code after the passes.
47 bool SparcTargetMachine::addPreEmitPass(PassManagerBase &PM){
48 PM.add(createSparcFPMoverPass(*this));
49 PM.add(createSparcDelaySlotFillerPass(*this));
70 bool SparcPassConfig::addPreEmitPass(){
71 PM.add(createSparcFPMoverPass(getSparcTargetMachine()));
72 PM.add(createSparcDelaySlotFillerPass(getSparcTargetMachine()));
5073 return true;
5174 }
5275
6487
6588 void SparcV9TargetMachine::anchor() { }
6689
67 SparcV9TargetMachine::SparcV9TargetMachine(const Target &T,
90 SparcV9TargetMachine::SparcV9TargetMachine(const Target &T,
6891 StringRef TT, StringRef CPU,
6992 StringRef FS,
7093 const TargetOptions &Options,
5454 virtual const TargetData *getTargetData() const { return &DataLayout; }
5555
5656 // Pass Pipeline Configuration
57 virtual bool addInstSelector(PassManagerBase &PM);
58 virtual bool addPreEmitPass(PassManagerBase &PM);
57 virtual TargetPassConfig *createPassConfig(PassManagerBase &PM,
58 bool DisableVerify);
5959 };
6060
6161 /// SparcV8TargetMachine - Sparc 32-bit target machine
116116 // Pass Pipeline Configuration
117117 //===----------------------------------------------------------------------===//
118118
119 bool X86TargetMachine::addInstSelector(PassManagerBase &PM) {
119 namespace {
120 /// X86 Code Generator Pass Configuration Options.
121 class X86PassConfig : public TargetPassConfig {
122 public:
123 X86PassConfig(X86TargetMachine *TM, PassManagerBase &PM,
124 bool DisableVerifyFlag)
125 : TargetPassConfig(TM, PM, DisableVerifyFlag) {}
126
127 X86TargetMachine &getX86TargetMachine() const {
128 return getTM();
129 }
130
131 const X86Subtarget &getX86Subtarget() const {
132 return *getX86TargetMachine().getSubtargetImpl();
133 }
134
135 virtual bool addInstSelector();
136 virtual bool addPreRegAlloc();
137 virtual bool addPostRegAlloc();
138 virtual bool addPreEmitPass();
139 };
140 } // namespace
141
142 TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM,
143 bool DisableVerify) {
144 return new X86PassConfig(this, PM, DisableVerify);
145 }
146
147 bool X86PassConfig::addInstSelector() {
120148 // Install an instruction selector.
121 PM.add(createX86ISelDag(*this, getOptLevel()));
149 PM.add(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
122150
123151 // For 32-bit, prepend instructions to set the "global base reg" for PIC.
124 if (!Subtarget.is64Bit())
152 if (!getX86Subtarget().is64Bit())
125153 PM.add(createGlobalBaseRegPass());
126154
127155 return false;
128156 }
129157
130 bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM) {
158 bool X86PassConfig::addPreRegAlloc() {
131159 PM.add(createX86MaxStackAlignmentHeuristicPass());
132160 return false; // -print-machineinstr shouldn't print after this.
133161 }
134162
135 bool X86TargetMachine::addPostRegAlloc(PassManagerBase &PM) {
163 bool X86PassConfig::addPostRegAlloc() {
136164 PM.add(createX86FloatingPointStackifierPass());
137165 return true; // -print-machineinstr should print after this.
138166 }
139167
140 bool X86TargetMachine::addPreEmitPass(PassManagerBase &PM) {
168 bool X86PassConfig::addPreEmitPass() {
141169 bool ShouldPrint = false;
142 if (getOptLevel() != CodeGenOpt::None && Subtarget.hasSSE2()) {
170 if (getOptLevel() != CodeGenOpt::None && getX86Subtarget().hasSSE2()) {
143171 PM.add(createExecutionDependencyFixPass(&X86::VR128RegClass));
144172 ShouldPrint = true;
145173 }
146174
147 if (Subtarget.hasAVX() && UseVZeroUpper) {
175 if (getX86Subtarget().hasAVX() && UseVZeroUpper) {
148176 PM.add(createX86IssueVZeroUpperPass());
149177 ShouldPrint = true;
150178 }
7070 }
7171
7272 // Set up the pass pipeline.
73 virtual bool addInstSelector(PassManagerBase &PM);
74 virtual bool addPreRegAlloc(PassManagerBase &PM);
75 virtual bool addPostRegAlloc(PassManagerBase &PM);
76 virtual bool addPreEmitPass(PassManagerBase &PM);
73 virtual TargetPassConfig *createPassConfig(PassManagerBase &PM,
74 bool DisableVerify);
75
7776 virtual bool addCodeEmitter(PassManagerBase &PM,
7877 JITCodeEmitter &JCE);
7978 };
1313 #include "XCore.h"
1414 #include "llvm/Module.h"
1515 #include "llvm/PassManager.h"
16 #include "llvm/CodeGen/Passes.h"
1617 #include "llvm/Support/TargetRegistry.h"
1718 using namespace llvm;
1819
3334 TSInfo(*this) {
3435 }
3536
36 bool XCoreTargetMachine::addInstSelector(PassManagerBase &PM) {
37 PM.add(createXCoreISelDag(*this, getOptLevel()));
37 namespace {
38 /// XCore Code Generator Pass Configuration Options.
39 class XCorePassConfig : public TargetPassConfig {
40 public:
41 XCorePassConfig(XCoreTargetMachine *TM, PassManagerBase &PM,
42 bool DisableVerifyFlag)
43 : TargetPassConfig(TM, PM, DisableVerifyFlag) {}
44
45 XCoreTargetMachine &getXCoreTargetMachine() const {
46 return getTM();
47 }
48
49 virtual bool addInstSelector();
50 };
51 } // namespace
52
53 TargetPassConfig *XCoreTargetMachine::createPassConfig(PassManagerBase &PM,
54 bool DisableVerify) {
55 return new XCorePassConfig(this, PM, DisableVerify);
56 }
57
58 bool XCorePassConfig::addInstSelector() {
59 PM.add(createXCoreISelDag(getXCoreTargetMachine(), getOptLevel()));
3860 return false;
3961 }
4062
5555 virtual const TargetData *getTargetData() const { return &DataLayout; }
5656
5757 // Pass Pipeline Configuration
58 virtual bool addInstSelector(PassManagerBase &PM);
58 virtual TargetPassConfig *createPassConfig(PassManagerBase &PM,
59 bool DisableVerify);
5960 };
6061
6162 } // end namespace llvm