llvm.org GIT mirror llvm / 84023e0
Reapply bottom-up fast-isel, with several fixes for x86-32: - Check getBytesToPopOnReturn(). - Eschew ST0 and ST1 for return values. - Fix the PIC base register initialization so that it doesn't ever fail to end up the top of the entry block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108039 91177308-0d34-0410-b5e6-96231b3b80d8 Dan Gohman 10 years ago
26 changed file(s) with 782 addition(s) and 398 deletion(s). Raw diff Collapse all Expand all
187187 /// CheckReturn - Analyze the return values of a function, returning
188188 /// true if the return can be performed without sret-demotion, and
189189 /// false otherwise.
190 bool CheckReturn(const SmallVectorImpl &OutTys,
191 const SmallVectorImpl> &ArgsFlags,
190 bool CheckReturn(const SmallVectorImpl> &ArgsFlags,
192191 CCAssignFn Fn);
193192
194193 /// AnalyzeCallOperands - Analyze the outgoing arguments to a call,
1818 #include "llvm/ADT/SmallSet.h"
1919 #endif
2020 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/CodeGen/MachineBasicBlock.h"
2122
2223 namespace llvm {
2324
4344 /// lowering, but runs quickly.
4445 class FastISel {
4546 protected:
46 MachineBasicBlock *MBB;
4747 DenseMap LocalValueMap;
4848 FunctionLoweringInfo &FuncInfo;
4949 MachineRegisterInfo &MRI;
5555 const TargetInstrInfo &TII;
5656 const TargetLowering &TLI;
5757 const TargetRegisterInfo &TRI;
58 bool IsBottomUp;
58 MachineInstr *LastLocalValue;
5959
6060 public:
61 /// getLastLocalValue - Return the position of the last instruction
62 /// emitted for materializing constants for use in the current block.
63 MachineInstr *getLastLocalValue() { return LastLocalValue; }
64
65 /// setLastLocalValue - Update the position of the last instruction
66 /// emitted for materializing constants for use in the current block.
67 void setLastLocalValue(MachineInstr *I) { LastLocalValue = I; }
68
6169 /// startNewBlock - Set the current block to which generated machine
6270 /// instructions will be appended, and clear the local CSE map.
6371 ///
64 void startNewBlock(MachineBasicBlock *mbb) {
65 setCurrentBlock(mbb);
66 LocalValueMap.clear();
67 }
68
69 /// setCurrentBlock - Set the current block to which generated machine
70 /// instructions will be appended.
71 ///
72 void setCurrentBlock(MachineBasicBlock *mbb) {
73 MBB = mbb;
74 }
72 void startNewBlock();
7573
7674 /// getCurDebugLoc() - Return current debug location information.
7775 DebugLoc getCurDebugLoc() const { return DL; }
102100 /// takes care of truncating or sign-extending the given getelementptr
103101 /// index value.
104102 std::pair getRegForGEPIndex(const Value *V);
103
104 /// recomputeInsertPt - Reset InsertPt to prepare for insterting instructions
105 /// into the current block.
106 void recomputeInsertPt();
107
108 /// enterLocalValueArea - Prepare InsertPt to begin inserting instructions
109 /// into the local value area and return the old insert position.
110 MachineBasicBlock::iterator enterLocalValueArea();
111
112 /// leaveLocalValueArea - Reset InsertPt to the given old insert position
113 void leaveLocalValueArea(MachineBasicBlock::iterator OldInsertPt);
105114
106115 virtual ~FastISel();
107116
2424 #endif
2525 #include "llvm/CodeGen/ValueTypes.h"
2626 #include "llvm/CodeGen/ISDOpcodes.h"
27 #include "llvm/CodeGen/MachineBasicBlock.h"
2728 #include "llvm/Support/CallSite.h"
2829 #include
2930
7879 /// ArgDbgValues - A list of DBG_VALUE instructions created during isel for
7980 /// function arguments that are inserted after scheduling is completed.
8081 SmallVector ArgDbgValues;
82
83 /// RegFixups - Registers which need to be replaced after isel is done.
84 DenseMap RegFixups;
85
86 /// MBB - The current block.
87 MachineBasicBlock *MBB;
88
89 /// MBB - The current insert position inside the current block.
90 MachineBasicBlock::iterator InsertPt;
8191
8292 #ifndef NDEBUG
8393 SmallSet CatchInfoLost;
279279 SDNode *MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTs,
280280 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo);
281281
282 void PrepareEHLandingPad(MachineBasicBlock *BB);
282 void PrepareEHLandingPad();
283283 void SelectAllBasicBlocks(const Function &Fn);
284 void FinishBasicBlock(MachineBasicBlock *BB);
285
286 MachineBasicBlock *SelectBasicBlock(MachineBasicBlock *BB,
287 BasicBlock::const_iterator Begin,
288 BasicBlock::const_iterator End,
289 bool &HadTailCall);
290 MachineBasicBlock *CodeGenAndEmitDAG(MachineBasicBlock *BB);
284 void FinishBasicBlock();
285
286 void SelectBasicBlock(BasicBlock::const_iterator Begin,
287 BasicBlock::const_iterator End,
288 bool &HadTailCall);
289 void CodeGenAndEmitDAG();
291290 void LowerArguments(const BasicBlock *BB);
292291
293292 void ComputeLiveOutVRegInfo();
2323
2424 #include "llvm/CallingConv.h"
2525 #include "llvm/InlineAsm.h"
26 #include "llvm/Attributes.h"
2627 #include "llvm/CodeGen/SelectionDAGNodes.h"
2728 #include "llvm/CodeGen/RuntimeLibcalls.h"
2829 #include "llvm/ADT/APFloat.h"
11581159 /// registers. If false is returned, an sret-demotion is performed.
11591160 ///
11601161 virtual bool CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
1161 const SmallVectorImpl &OutTys,
1162 const SmallVectorImplArgFlagsTy> &ArgsFlags,
1162 const SmallVectorImplOutputArg> &Outs,
11631163 LLVMContext &Context) const
11641164 {
11651165 // Return true by default to get preexisting behavior.
16551655 /// optimization.
16561656 bool benefitFromCodePlacementOpt;
16571657 };
1658
1659 /// GetReturnInfo - Given an LLVM IR type and return type attributes,
1660 /// compute the return value EVTs and flags, and optionally also
1661 /// the offsets, if the return value is being lowered to memory.
1662 void GetReturnInfo(const Type* ReturnType, Attributes attr,
1663 SmallVectorImpl &Outs,
1664 const TargetLowering &TLI,
1665 SmallVectorImpl *Offsets = 0);
1666
16581667 } // end llvm namespace
16591668
16601669 #endif
7979
8080 /// CheckReturn - Analyze the return values of a function, returning true if
8181 /// the return can be performed without sret-demotion, and false otherwise.
82 bool CCState::CheckReturn(const SmallVectorImpl &OutTys,
83 const SmallVectorImpl &ArgsFlags,
82 bool CCState::CheckReturn(const SmallVectorImpl &Outs,
8483 CCAssignFn Fn) {
8584 // Determine which register each value should be copied into.
86 for (unsigned i = 0, e = OutTys.size(); i != e; ++i) {
87 EVT VT = OutTys[i];
88 ISD::ArgFlagsTy ArgFlags = ArgsFlags[i];
85 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
86 EVT VT = Outs[i].VT;
87 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
8988 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this))
9089 return false;
9190 }
328328 if (OptLevel != CodeGenOpt::None)
329329 PM.add(createOptimizePHIsPass());
330330
331 // Delete dead machine instructions regardless of optimization level.
332 //
333 // At -O0, fast-isel frequently creates dead instructions.
334 //
335 // With optimization, dead code should already be eliminated. However
336 // there is one known exception: lowered code for arguments that are only
337 // used by tail calls, where the tail calls reuse the incoming stack
338 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
339 PM.add(createDeadMachineInstructionElimPass());
340 printAndVerify(PM, "After codegen DCE pass",
341 /* allowDoubleDefs= */ true);
342
343331 if (OptLevel != CodeGenOpt::None) {
332 // With optimization, dead code should already be eliminated. However
333 // there is one known exception: lowered code for arguments that are only
334 // used by tail calls, where the tail calls reuse the incoming stack
335 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
336 PM.add(createDeadMachineInstructionElimPass());
337 printAndVerify(PM, "After codegen DCE pass",
338 /* allowDoubleDefs= */ true);
339
344340 PM.add(createOptimizeExtsPass());
345341 if (!DisableMachineLICM)
346342 PM.add(createMachineLICMPass());
5656 #include "llvm/Support/ErrorHandling.h"
5757 using namespace llvm;
5858
59 /// startNewBlock - Set the current block to which generated machine
60 /// instructions will be appended, and clear the local CSE map.
61 ///
62 void FastISel::startNewBlock() {
63 LocalValueMap.clear();
64
65 // Start out as null, meaining no local-value instructions have
66 // been emitted.
67 LastLocalValue = 0;
68
69 // Advance the last local value past any EH_LABEL instructions.
70 MachineBasicBlock::iterator
71 I = FuncInfo.MBB->begin(), E = FuncInfo.MBB->end();
72 while (I != E && I->getOpcode() == TargetOpcode::EH_LABEL) {
73 LastLocalValue = I;
74 ++I;
75 }
76 }
77
5978 bool FastISel::hasTrivialKill(const Value *V) const {
6079 // Don't consider constants or arguments to have trivial kills.
6180 const Instruction *I = dyn_cast(V);
100119 // only locally. This is because Instructions already have the SSA
101120 // def-dominates-use requirement enforced.
102121 DenseMap::iterator I = FuncInfo.ValueMap.find(V);
103 if (I != FuncInfo.ValueMap.end())
104 return I->second;
122 if (I != FuncInfo.ValueMap.end()) {
123 unsigned Reg = I->second;
124 return Reg;
125 }
105126 unsigned Reg = LocalValueMap[V];
106127 if (Reg != 0)
107128 return Reg;
108129
109130 // In bottom-up mode, just create the virtual register which will be used
110131 // to hold the value. It will be materialized later.
111 if (IsBottomUp) {
112 Reg = createResultReg(TLI.getRegClassFor(VT));
113 if (isa(V))
114 FuncInfo.ValueMap[V] = Reg;
115 else
116 LocalValueMap[V] = Reg;
117 return Reg;
118 }
119
120 return materializeRegForValue(V, VT);
132 if (isa(V) &&
133 (!isa(V) ||
134 !FuncInfo.StaticAllocaMap.count(cast(V))))
135 return FuncInfo.InitializeRegForValue(V);
136
137 MachineBasicBlock::iterator SaveInsertPt = enterLocalValueArea();
138
139 // Materialize the value in a register. Emit any instructions in the
140 // local value area.
141 Reg = materializeRegForValue(V, VT);
142
143 leaveLocalValueArea(SaveInsertPt);
144
145 return Reg;
121146 }
122147
123148 /// materializeRegForValue - Helper for getRegForVale. This function is
168193 Reg = lookUpRegForValue(Op);
169194 } else if (isa(V)) {
170195 Reg = createResultReg(TLI.getRegClassFor(VT));
171 BuildMI(MBB, DL, TII.get(TargetOpcode::IMPLICIT_DEF), Reg);
196 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
197 TII.get(TargetOpcode::IMPLICIT_DEF), Reg);
172198 }
173199
174200 // If target-independent code couldn't handle the value, give target-specific
178204
179205 // Don't cache constant materializations in the general ValueMap.
180206 // To do so would require tracking what uses they dominate.
181 if (Reg != 0)
207 if (Reg != 0) {
182208 LocalValueMap[V] = Reg;
209 LastLocalValue = MRI.getVRegDef(Reg);
210 }
183211 return Reg;
184212 }
185213
208236
209237 unsigned &AssignedReg = FuncInfo.ValueMap[I];
210238 if (AssignedReg == 0)
239 // Use the new register.
211240 AssignedReg = Reg;
212241 else if (Reg != AssignedReg) {
213 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg);
214 TII.copyRegToReg(*MBB, MBB->end(), AssignedReg,
215 Reg, RegClass, RegClass, DL);
216 }
242 // Arrange for uses of AssignedReg to be replaced by uses of Reg.
243 FuncInfo.RegFixups[AssignedReg] = Reg;
244
245 AssignedReg = Reg;
246 }
247
217248 return AssignedReg;
218249 }
219250
239270 IdxNIsKill = true;
240271 }
241272 return std::pair(IdxN, IdxNIsKill);
273 }
274
275 void FastISel::recomputeInsertPt() {
276 if (getLastLocalValue()) {
277 FuncInfo.InsertPt = getLastLocalValue();
278 ++FuncInfo.InsertPt;
279 } else
280 FuncInfo.InsertPt = FuncInfo.MBB->getFirstNonPHI();
281
282 // Now skip past any EH_LABELs, which must remain at the beginning.
283 while (FuncInfo.InsertPt != FuncInfo.MBB->end() &&
284 FuncInfo.InsertPt->getOpcode() == TargetOpcode::EH_LABEL)
285 ++FuncInfo.InsertPt;
286 }
287
288 MachineBasicBlock::iterator FastISel::enterLocalValueArea() {
289 MachineBasicBlock::iterator OldInsertPt = FuncInfo.InsertPt;
290 recomputeInsertPt();
291 return OldInsertPt;
292 }
293
294 void FastISel::leaveLocalValueArea(MachineBasicBlock::iterator OldInsertPt) {
295 if (FuncInfo.InsertPt != FuncInfo.MBB->begin())
296 LastLocalValue = llvm::prior(FuncInfo.InsertPt);
297
298 // Restore the previous insert position.
299 FuncInfo.InsertPt = OldInsertPt;
242300 }
243301
244302 /// SelectBinaryOp - Select and emit code for a binary operator instruction,
433491 if (!V) {
434492 // Currently the optimizer can produce this; insert an undef to
435493 // help debugging. Probably the optimizer should not do this.
436 BuildMI(MBB, DL, II).addReg(0U).addImm(DI->getOffset()).
437 addMetadata(DI->getVariable());
494 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
495 .addReg(0U).addImm(DI->getOffset())
496 .addMetadata(DI->getVariable());
438497 } else if (const ConstantInt *CI = dyn_cast(V)) {
439 BuildMI(MBB, DL, II).addImm(CI->getZExtValue()).addImm(DI->getOffset()).
440 addMetadata(DI->getVariable());
498 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
499 .addImm(CI->getZExtValue()).addImm(DI->getOffset())
500 .addMetadata(DI->getVariable());
441501 } else if (const ConstantFP *CF = dyn_cast(V)) {
442 BuildMI(MBB, DL, II).addFPImm(CF).addImm(DI->getOffset()).
443 addMetadata(DI->getVariable());
502 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
503 .addFPImm(CF).addImm(DI->getOffset())
504 .addMetadata(DI->getVariable());
444505 } else if (unsigned Reg = lookUpRegForValue(V)) {
445 BuildMI(MBB, DL, II).addReg(Reg, RegState::Debug).addImm(DI->getOffset()).
446 addMetadata(DI->getVariable());
506 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
507 .addReg(Reg, RegState::Debug).addImm(DI->getOffset())
508 .addMetadata(DI->getVariable());
447509 } else {
448510 // We can't yet handle anything else here because it would require
449511 // generating code, thus altering codegen because of debug info.
450512 // Insert an undef so we can see what we dropped.
451 BuildMI(MBB, DL, II).addReg(0U).addImm(DI->getOffset()).
452 addMetadata(DI->getVariable());
513 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
514 .addReg(0U).addImm(DI->getOffset())
515 .addMetadata(DI->getVariable());
453516 }
454517 return true;
455518 }
458521 switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) {
459522 default: break;
460523 case TargetLowering::Expand: {
461 assert(MBB->isLandingPad() && "Call to eh.exception not in landing pad!");
524 assert(FuncInfo.MBB->isLandingPad() &&
525 "Call to eh.exception not in landing pad!");
462526 unsigned Reg = TLI.getExceptionAddressRegister();
463527 const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
464528 unsigned ResultReg = createResultReg(RC);
465 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
466 Reg, RC, RC, DL);
529 bool InsertedCopy = TII.copyRegToReg(*FuncInfo.MBB, FuncInfo.InsertPt,
530 ResultReg, Reg, RC, RC, DL);
467531 assert(InsertedCopy && "Can't copy address registers!");
468532 InsertedCopy = InsertedCopy;
469533 UpdateValueMap(I, ResultReg);
477541 switch (TLI.getOperationAction(ISD::EHSELECTION, VT)) {
478542 default: break;
479543 case TargetLowering::Expand: {
480 if (MBB->isLandingPad())
481 AddCatchInfo(*cast(I), &FuncInfo.MF->getMMI(), MBB);
544 if (FuncInfo.MBB->isLandingPad())
545 AddCatchInfo(*cast(I), &FuncInfo.MF->getMMI(), FuncInfo.MBB);
482546 else {
483547 #ifndef NDEBUG
484548 FuncInfo.CatchInfoLost.insert(cast(I));
485549 #endif
486550 // FIXME: Mark exception selector register as live in. Hack for PR1508.
487551 unsigned Reg = TLI.getExceptionSelectorRegister();
488 if (Reg) MBB->addLiveIn(Reg);
552 if (Reg) FuncInfo.MBB->addLiveIn(Reg);
489553 }
490554
491555 unsigned Reg = TLI.getExceptionSelectorRegister();
492556 EVT SrcVT = TLI.getPointerTy();
493557 const TargetRegisterClass *RC = TLI.getRegClassFor(SrcVT);
494558 unsigned ResultReg = createResultReg(RC);
495 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, Reg,
496 RC, RC, DL);
559 bool InsertedCopy = TII.copyRegToReg(*FuncInfo.MBB, FuncInfo.InsertPt,
560 ResultReg, Reg, RC, RC, DL);
497561 assert(InsertedCopy && "Can't copy address registers!");
498562 InsertedCopy = InsertedCopy;
499563
612676 TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
613677 ResultReg = createResultReg(DstClass);
614678
615 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
616 Op0, DstClass, SrcClass, DL);
679 bool InsertedCopy = TII.copyRegToReg(*FuncInfo.MBB, FuncInfo.InsertPt,
680 ResultReg, Op0,
681 DstClass, SrcClass, DL);
617682 if (!InsertedCopy)
618683 ResultReg = 0;
619684 }
661726 /// the CFG.
662727 void
663728 FastISel::FastEmitBranch(MachineBasicBlock *MSucc, DebugLoc DL) {
664 if (MBB->isLayoutSuccessor(MSucc)) {
729 if (FuncInfo.MBB->isLayoutSuccessor(MSucc)) {
665730 // The unconditional fall-through case, which needs no instructions.
666731 } else {
667732 // The unconditional branch case.
668 TII.InsertBranch(*MBB, MSucc, NULL, SmallVector(), DL);
669 }
670 MBB->addSuccessor(MSucc);
733 TII.InsertBranch(*FuncInfo.MBB, MSucc, NULL,
734 SmallVector(), DL);
735 }
736 FuncInfo.MBB->addSuccessor(MSucc);
671737 }
672738
673739 /// SelectFNeg - Emit an FNeg operation.
726792 BasicBlock::iterator ScanFrom = LI;
727793 if (const Value *V = FindAvailableLoadedValue(LI->getPointerOperand(),
728794 LI->getParent(), ScanFrom)) {
795 if (!V->use_empty() &&
796 (!isa(V) ||
797 cast(V)->getParent() == LI->getParent() ||
798 (isa(V) &&
799 FuncInfo.StaticAllocaMap.count(cast(V)))) &&
800 (!isa(V) ||
801 LI->getParent() == &LI->getParent()->getParent()->getEntryBlock())) {
729802 unsigned ResultReg = getRegForValue(V);
730803 if (ResultReg != 0) {
731804 UpdateValueMap(I, ResultReg);
732805 return true;
806 }
733807 }
734808 }
735809 }
853927 }
854928
855929 FastISel::FastISel(FunctionLoweringInfo &funcInfo)
856 : MBB(0),
857 FuncInfo(funcInfo),
930 : FuncInfo(funcInfo),
858931 MRI(FuncInfo.MF->getRegInfo()),
859932 MFI(*FuncInfo.MF->getFrameInfo()),
860933 MCP(*FuncInfo.MF->getConstantPool()),
862935 TD(*TM.getTargetData()),
863936 TII(*TM.getInstrInfo()),
864937 TLI(*TM.getTargetLowering()),
865 TRI(*TM.getRegisterInfo()),
866 IsBottomUp(false) {
938 TRI(*TM.getRegisterInfo()) {
867939 }
868940
869941 FastISel::~FastISel() {}
9921064 unsigned ResultReg = createResultReg(RC);
9931065 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
9941066
995 BuildMI(MBB, DL, II, ResultReg);
1067 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg);
9961068 return ResultReg;
9971069 }
9981070
10031075 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
10041076
10051077 if (II.getNumDefs() >= 1)
1006 BuildMI(MBB, DL, II, ResultReg).addReg(Op0, Op0IsKill * RegState::Kill);
1078 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
1079 .addReg(Op0, Op0IsKill * RegState::Kill);
10071080 else {
1008 BuildMI(MBB, DL, II).addReg(Op0, Op0IsKill * RegState::Kill);
1009 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1010 II.ImplicitDefs[0], RC, RC, DL);
1081 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
1082 .addReg(Op0, Op0IsKill * RegState::Kill);
1083 bool InsertedCopy = TII.copyRegToReg(*FuncInfo.MBB, FuncInfo.InsertPt,
1084 ResultReg, II.ImplicitDefs[0],
1085 RC, RC, DL);
10111086 if (!InsertedCopy)
10121087 ResultReg = 0;
10131088 }
10231098 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
10241099
10251100 if (II.getNumDefs() >= 1)
1026 BuildMI(MBB, DL, II, ResultReg)
1101 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
10271102 .addReg(Op0, Op0IsKill * RegState::Kill)
10281103 .addReg(Op1, Op1IsKill * RegState::Kill);
10291104 else {
1030 BuildMI(MBB, DL, II)
1105 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
10311106 .addReg(Op0, Op0IsKill * RegState::Kill)
10321107 .addReg(Op1, Op1IsKill * RegState::Kill);
1033 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1034 II.ImplicitDefs[0], RC, RC, DL);
1108 bool InsertedCopy = TII.copyRegToReg(*FuncInfo.MBB, FuncInfo.InsertPt,
1109 ResultReg, II.ImplicitDefs[0],
1110 RC, RC, DL);
10351111 if (!InsertedCopy)
10361112 ResultReg = 0;
10371113 }
10461122 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
10471123
10481124 if (II.getNumDefs() >= 1)
1049 BuildMI(MBB, DL, II, ResultReg)
1125 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
10501126 .addReg(Op0, Op0IsKill * RegState::Kill)
10511127 .addImm(Imm);
10521128 else {
1053 BuildMI(MBB, DL, II)
1129 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
10541130 .addReg(Op0, Op0IsKill * RegState::Kill)
10551131 .addImm(Imm);
1056 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1057 II.ImplicitDefs[0], RC, RC, DL);
1132 bool InsertedCopy = TII.copyRegToReg(*FuncInfo.MBB, FuncInfo.InsertPt,
1133 ResultReg, II.ImplicitDefs[0],
1134 RC, RC, DL);
10581135 if (!InsertedCopy)
10591136 ResultReg = 0;
10601137 }
10691146 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
10701147
10711148 if (II.getNumDefs() >= 1)
1072 BuildMI(MBB, DL, II, ResultReg)
1149 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
10731150 .addReg(Op0, Op0IsKill * RegState::Kill)
10741151 .addFPImm(FPImm);
10751152 else {
1076 BuildMI(MBB, DL, II)
1153 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
10771154 .addReg(Op0, Op0IsKill * RegState::Kill)
10781155 .addFPImm(FPImm);
1079 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1080 II.ImplicitDefs[0], RC, RC, DL);
1156 bool InsertedCopy = TII.copyRegToReg(*FuncInfo.MBB, FuncInfo.InsertPt,
1157 ResultReg, II.ImplicitDefs[0],
1158 RC, RC, DL);
10811159 if (!InsertedCopy)
10821160 ResultReg = 0;
10831161 }
10931171 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
10941172
10951173 if (II.getNumDefs() >= 1)
1096 BuildMI(MBB, DL, II, ResultReg)
1174 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
10971175 .addReg(Op0, Op0IsKill * RegState::Kill)
10981176 .addReg(Op1, Op1IsKill * RegState::Kill)
10991177 .addImm(Imm);
11001178 else {
1101 BuildMI(MBB, DL, II)
1179 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
11021180 .addReg(Op0, Op0IsKill * RegState::Kill)
11031181 .addReg(Op1, Op1IsKill * RegState::Kill)
11041182 .addImm(Imm);
1105 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1106 II.ImplicitDefs[0], RC, RC, DL);
1183 bool InsertedCopy = TII.copyRegToReg(*FuncInfo.MBB, FuncInfo.InsertPt,
1184 ResultReg, II.ImplicitDefs[0],
1185 RC, RC, DL);
11071186 if (!InsertedCopy)
11081187 ResultReg = 0;
11091188 }
11171196 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
11181197
11191198 if (II.getNumDefs() >= 1)
1120 BuildMI(MBB, DL, II, ResultReg).addImm(Imm);
1199 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg).addImm(Imm);
11211200 else {
1122 BuildMI(MBB, DL, II).addImm(Imm);
1123 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1124 II.ImplicitDefs[0], RC, RC, DL);
1201 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II).addImm(Imm);
1202 bool InsertedCopy = TII.copyRegToReg(*FuncInfo.MBB, FuncInfo.InsertPt,
1203 ResultReg, II.ImplicitDefs[0],
1204 RC, RC, DL);
11251205 if (!InsertedCopy)
11261206 ResultReg = 0;
11271207 }
11341214 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
11351215 assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
11361216 "Cannot yet extract from physregs");
1137 BuildMI(MBB, DL, TII.get(TargetOpcode::COPY), ResultReg)
1217 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
1218 DL, TII.get(TargetOpcode::COPY), ResultReg)
11381219 .addReg(Op0, getKillRegState(Op0IsKill), Idx);
11391220 return ResultReg;
11401221 }
8181 MF = &mf;
8282 RegInfo = &MF->getRegInfo();
8383
84 // Check whether the function can return without sret-demotion.
85 SmallVector Outs;
86 GetReturnInfo(Fn->getReturnType(),
87 Fn->getAttributes().getRetAttributes(), Outs, TLI);
88 CanLowerReturn = TLI.CanLowerReturn(Fn->getCallingConv(), Fn->isVarArg(),
89 Outs, Fn->getContext());
90
8491 // Create a vreg for each argument register that is not dead and is used
8592 // outside of the entry block for the function.
8693 for (Function::const_arg_iterator AI = Fn->arg_begin(), E = Fn->arg_end();
173180 #endif
174181 LiveOutRegInfo.clear();
175182 ArgDbgValues.clear();
183 RegFixups.clear();
176184 }
177185
178186 /// CreateReg - Allocate a single virtual register for the given type.
733733 if (II.usesCustomInsertionHook()) {
734734 // Insert this instruction into the basic block using a target
735735 // specific inserter which may returns a new basic block.
736 MBB = TLI->EmitInstrWithCustomInserter(MI, MBB);
737 InsertPos = MBB->end();
736 bool AtEnd = InsertPos == MBB->end();
737 MachineBasicBlock *NewMBB = TLI->EmitInstrWithCustomInserter(MI, MBB);
738 if (NewMBB != MBB) {
739 if (AtEnd)
740 InsertPos = NewMBB->end();
741 MBB = NewMBB;
742 }
738743 return;
739744 }
740745
518518 return;
519519
520520 MachineBasicBlock *BB = Emitter.getBlock();
521 if (BB->empty() || BB->back().isPHI()) {
521 if (Emitter.getInsertPos() == BB->begin() || BB->back().isPHI()) {
522522 // Did not insert any instruction.
523523 Orders.push_back(std::make_pair(Order, (MachineInstr*)0));
524524 return;
525525 }
526526
527 Orders.push_back(std::make_pair(Order, &BB->back()));
527 Orders.push_back(std::make_pair(Order, prior(Emitter.getInsertPos())));
528528 if (!N->getHasDebugValue())
529529 return;
530530 // Opportunistically insert immediate dbg_value uses, i.e. those with source
563563 for (; PDI != PDE; ++PDI) {
564564 MachineInstr *DbgMI= Emitter.EmitDbgValue(*PDI, VRBaseMap);
565565 if (DbgMI)
566 BB->push_back(DbgMI);
566 BB->insert(InsertPos, DbgMI);
567567 }
568568 }
569569
607607 // Insert all the dbg_values which have not already been inserted in source
608608 // order sequence.
609609 if (HasDbg) {
610 MachineBasicBlock::iterator BBBegin = BB->empty() ? BB->end() : BB->begin();
611 while (BBBegin != BB->end() && BBBegin->isPHI())
612 ++BBBegin;
610 MachineBasicBlock::iterator BBBegin = BB->getFirstNonPHI();
613611
614612 // Sort the source order instructions and use the order to insert debug
615613 // values.
625623 // Insert all SDDbgValue's whose order(s) are before "Order".
626624 if (!MI)
627625 continue;
628 MachineBasicBlock *MIBB = MI->getParent();
629626 #ifndef NDEBUG
630627 unsigned LastDIOrder = 0;
631628 #endif
645642 BB->insert(BBBegin, DbgMI);
646643 else {
647644 MachineBasicBlock::iterator Pos = MI;
648 MIBB->insert(llvm::next(Pos), DbgMI);
645 BB->insert(llvm::next(Pos), DbgMI);
649646 }
650647 }
651648 }
950950
951951 // If this is an instruction which fast-isel has deferred, select it now.
952952 if (const Instruction *Inst = dyn_cast(V)) {
953 assert(Inst->isSafeToSpeculativelyExecute() &&
954 "Instruction with side effects deferred!");
955 visit(*Inst);
956 DenseMap::iterator NIt = NodeMap.find(Inst);
957 if (NIt != NodeMap.end() && NIt->second.getNode())
958 return NIt->second;
953 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
954 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType());
955 SDValue Chain = DAG.getEntryNode();
956 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL);
959957 }
960958
961959 llvm_unreachable("Can't get register for value!");
962960 return SDValue();
963 }
964
965 /// Get the EVTs and ArgFlags collections that represent the legalized return
966 /// type of the given function. This does not require a DAG or a return value,
967 /// and is suitable for use before any DAGs for the function are constructed.
968 static void getReturnInfo(const Type* ReturnType,
969 Attributes attr, SmallVectorImpl &OutVTs,
970 SmallVectorImpl &OutFlags,
971 const TargetLowering &TLI,
972 SmallVectorImpl *Offsets = 0) {
973 SmallVector ValueVTs;
974 ComputeValueVTs(TLI, ReturnType, ValueVTs);
975 unsigned NumValues = ValueVTs.size();
976 if (NumValues == 0) return;
977 unsigned Offset = 0;
978
979 for (unsigned j = 0, f = NumValues; j != f; ++j) {
980 EVT VT = ValueVTs[j];
981 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
982
983 if (attr & Attribute::SExt)
984 ExtendKind = ISD::SIGN_EXTEND;
985 else if (attr & Attribute::ZExt)
986 ExtendKind = ISD::ZERO_EXTEND;
987
988 // FIXME: C calling convention requires the return type to be promoted to
989 // at least 32-bit. But this is not necessary for non-C calling
990 // conventions. The frontend should mark functions whose return values
991 // require promoting with signext or zeroext attributes.
992 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
993 EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
994 if (VT.bitsLT(MinVT))
995 VT = MinVT;
996 }
997
998 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
999 EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
1000 unsigned PartSize = TLI.getTargetData()->getTypeAllocSize(
1001 PartVT.getTypeForEVT(ReturnType->getContext()));
1002
1003 // 'inreg' on function refers to return value
1004 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1005 if (attr & Attribute::InReg)
1006 Flags.setInReg();
1007
1008 // Propagate extension type if any
1009 if (attr & Attribute::SExt)
1010 Flags.setSExt();
1011 else if (attr & Attribute::ZExt)
1012 Flags.setZExt();
1013
1014 for (unsigned i = 0; i < NumParts; ++i) {
1015 OutVTs.push_back(PartVT);
1016 OutFlags.push_back(Flags);
1017 if (Offsets)
1018 {
1019 Offsets->push_back(Offset);
1020 Offset += PartSize;
1021 }
1022 }
1023 }
1024961 }
1025962
1026963 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
13191256 }
13201257
13211258 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1322 MachineBasicBlock *BrMBB = FuncInfo.MBBMap[I.getParent()];
1259 MachineBasicBlock *BrMBB = FuncInfo.MBB;
13231260
13241261 // Update machine-CFG edges.
13251262 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
16451582 }
16461583
16471584 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1648 MachineBasicBlock *InvokeMBB = FuncInfo.MBBMap[I.getParent()];
1585 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
16491586
16501587 // Retrieve successors.
16511588 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
21732110 }
21742111
21752112 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
2176 MachineBasicBlock *SwitchMBB = FuncInfo.MBBMap[SI.getParent()];
2113 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
21772114
21782115 // Figure out which block is immediately after the current one.
21792116 MachineBasicBlock *NextBlock = 0;
22392176 }
22402177
22412178 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2242 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBBMap[I.getParent()];
2179 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
22432180
22442181 // Update machine-CFG edges with unique successors.
22452182 SmallVector succs;
38993836 if (DV.isInlinedFnArgument(MF.getFunction()))
39003837 return false;
39013838
3902 MachineBasicBlock *MBB = FuncInfo.MBBMap[DI.getParent()];
3839 MachineBasicBlock *MBB = FuncInfo.MBB;
39033840 if (MBB != &MF.front())
39043841 return false;
39053842
41624099 }
41634100 case Intrinsic::eh_exception: {
41644101 // Insert the EXCEPTIONADDR instruction.
4165 assert(FuncInfo.MBBMap[I.getParent()]->isLandingPad() &&
4102 assert(FuncInfo.MBB->isLandingPad() &&
41664103 "Call to eh.exception not in landing pad!");
41674104 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
41684105 SDValue Ops[1];
41744111 }
41754112
41764113 case Intrinsic::eh_selector: {
4177 MachineBasicBlock *CallMBB = FuncInfo.MBBMap[I.getParent()];
4114 MachineBasicBlock *CallMBB = FuncInfo.MBB;
41784115 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
41794116 if (CallMBB->isLandingPad())
41804117 AddCatchInfo(I, &MMI, CallMBB);
41844121 #endif
41854122 // FIXME: Mark exception selector register as live in. Hack for PR1508.
41864123 unsigned Reg = TLI.getExceptionSelectorRegister();
4187 if (Reg) FuncInfo.MBBMap[I.getParent()]->addLiveIn(Reg);
4124 if (Reg) FuncInfo.MBB->addLiveIn(Reg);
41884125 }
41894126
41904127 // Insert the EHSELECTION instruction.
45584495 Args.reserve(CS.arg_size());
45594496
45604497 // Check whether the function can return without sret-demotion.
4561 SmallVector OutVTs;
4562 SmallVectorArgFlagsTy, 4> OutsFlags;
4498 SmallVectorOutputArg, 4> Outs;
45634499 SmallVector Offsets;
4564 getReturnInfo(RetTy, CS.getAttributes().getRetAttributes(),
4565 OutVTs, OutsFlags, TLI, &Offsets);
4500 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(),
4501 Outs, TLI, &Offsets);
45664502
45674503 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(),
4568 FTy->isVarArg(), OutVTs, OutsFlags, FTy->getContext());
4504 FTy->isVarArg(), Outs, FTy->getContext());
45694505
45704506 SDValue DemoteStackSlot;
45714507
46584594 ComputeValueVTs(TLI, PtrRetTy, PVTs);
46594595 assert(PVTs.size() == 1 && "Pointers should fit in one register");
46604596 EVT PtrVT = PVTs[0];
4661 unsigned NumValues = OutVTs.size();
4597 unsigned NumValues = Outs.size();
46624598 SmallVector Values(NumValues);
46634599 SmallVector Chains(NumValues);
46644600
46664602 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT,
46674603 DemoteStackSlot,
46684604 DAG.getConstant(Offsets[i], PtrVT));
4669 SDValue L = DAG.getLoad(OutVTs[i], getCurDebugLoc(), Result.second,
4605 SDValue L = DAG.getLoad(Outs[i].VT, getCurDebugLoc(), Result.second,
46704606 Add, NULL, Offsets[i], false, false, 1);
46714607 Values[i] = L;
46724608 Chains[i] = L.getValue(1);
59585894 SmallVector Ins;
59595895
59605896 // Check whether the function can return without sret-demotion.
5961 SmallVector OutVTs;
5962 SmallVector OutsFlags;
5963 getReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
5964 OutVTs, OutsFlags, TLI);
5965
5966 FuncInfo->CanLowerReturn = TLI.CanLowerReturn(F.getCallingConv(),
5967 F.isVarArg(),
5968 OutVTs, OutsFlags,
5969 F.getContext());
5897 SmallVector Outs;
5898 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
5899 Outs, TLI);
5900
59705901 if (!FuncInfo->CanLowerReturn) {
59715902 // Put in an sret pointer parameter before all the other parameters.
59725903 SmallVector ValueVTs;
315315 // Determine if there is a call to setjmp in the machine function.
316316 MF->setCallsSetJmp(FunctionCallsSetJmp(&Fn));
317317
318 // Replace forward-declared registers with the registers containing
319 // the desired value.
320 MachineRegisterInfo &MRI = MF->getRegInfo();
321 for (DenseMap::iterator
322 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end();
323 I != E; ++I) {
324 unsigned From = I->first;
325 unsigned To = I->second;
326 // If To is also scheduled to be replaced, find what its ultimate
327 // replacement is.
328 for (;;) {
329 DenseMap::iterator J =
330 FuncInfo->RegFixups.find(To);
331 if (J == E) break;
332 To = J->second;
333 }
334 // Replace it.
335 MRI.replaceRegWith(From, To);
336 }
337
318338 // Release function-specific state. SDB and CurDAG are already cleared
319339 // at this point.
320340 FuncInfo->clear();
322342 return true;
323343 }
324344
325 MachineBasicBlock *
326 SelectionDAGISel::SelectBasicBlock(MachineBasicBlock *BB,
327 BasicBlock::const_iterator Begin,
345 void
346 SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
328347 BasicBlock::const_iterator End,
329348 bool &HadTailCall) {
330349 // Lower all of the non-terminator instructions. If a call is emitted
339358 SDB->clear();
340359
341360 // Final step, emit the lowered DAG as machine code.
342 return CodeGenAndEmitDAG(BB);
361 CodeGenAndEmitDAG();
343362 }
344363
345364 namespace {
428447 } while (!Worklist.empty());
429448 }
430449
431 MachineBasicBlock *SelectionDAGISel::CodeGenAndEmitDAG(MachineBasicBlock *BB) {
450 void SelectionDAGISel::CodeGenAndEmitDAG() {
432451 std::string GroupName;
433452 if (TimePassesIsEnabled)
434453 GroupName = "Instruction Selection and Scheduling";
437456 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
438457 ViewSUnitDAGs)
439458 BlockName = MF->getFunction()->getNameStr() + ":" +
440 BB->getBasicBlock()->getNameStr();
459 FuncInfo->MBB->getBasicBlock()->getNameStr();
441460
442461 DEBUG(dbgs() << "Initial selection DAG:\n"; CurDAG->dump());
443462
544563 {
545564 NamedRegionTimer T("Instruction Scheduling", GroupName,
546565 TimePassesIsEnabled);
547 Scheduler->Run(CurDAG, BB, BB->end());
566 Scheduler->Run(CurDAG, FuncInfo->MBB, FuncInfo->InsertPt);
548567 }
549568
550569 if (ViewSUnitDAGs) Scheduler->viewGraph();
553572 // inserted into.
554573 {
555574 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
556 BB = Scheduler->EmitSchedule();
575
576 FuncInfo->MBB = Scheduler->EmitSchedule();
577 FuncInfo->InsertPt = Scheduler->InsertPos;
557578 }
558579
559580 // Free the scheduler state.
565586
566587 // Free the SelectionDAG state, now that we're finished with it.
567588 CurDAG->clear();
568
569 return BB;
570589 }
571590
572591 void SelectionDAGISel::DoInstructionSelection() {
628647
629648 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
630649 /// do other setup for EH landing-pad blocks.
631 void SelectionDAGISel::PrepareEHLandingPad(MachineBasicBlock *BB) {
650 void SelectionDAGISel::PrepareEHLandingPad() {
632651 // Add a label to mark the beginning of the landing pad. Deletion of the
633652 // landing pad can thus be detected via the MachineModuleInfo.
634 MCSymbol *Label = MF->getMMI().addLandingPad(BB);
653 MCSymbol *Label = MF->getMMI().addLandingPad(FuncInfo->MBB);
635654
636655 const TargetInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
637 BuildMI(BB, SDB->getCurDebugLoc(), II).addSym(Label);
656 BuildMI(*FuncInfo->MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
657 .addSym(Label);
638658
639659 // Mark exception register as live in.
640660 unsigned Reg = TLI.getExceptionAddressRegister();
641 if (Reg) BB->addLiveIn(Reg);
661 if (Reg) FuncInfo->MBB->addLiveIn(Reg);
642662
643663 // Mark exception selector register as live in.
644664 Reg = TLI.getExceptionSelectorRegister();
645 if (Reg) BB->addLiveIn(Reg);
665 if (Reg) FuncInfo->MBB->addLiveIn(Reg);
646666
647667 // FIXME: Hack around an exception handling flaw (PR1508): the personality
648668 // function and list of typeids logically belong to the invoke (or, if you
655675 // in exceptions not being caught because no typeids are associated with
656676 // the invoke. This may not be the only way things can go wrong, but it
657677 // is the only way we try to work around for the moment.
658 const BasicBlock *LLVMBB = BB->getBasicBlock();
678 const BasicBlock *LLVMBB = FuncInfo->MBB->getBasicBlock();
659679 const BranchInst *Br = dyn_cast(LLVMBB->getTerminator());
660680
661681 if (Br && Br->isUnconditional()) { // Critical edge?
679699 // Iterate over all basic blocks in the function.
680700 for (Function::const_iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
681701 const BasicBlock *LLVMBB = &*I;
682 MachineBasicBlock *BB = FuncInfo->MBBMap[LLVMBB];
702 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
703 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
683704
684705 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
685706 BasicBlock::const_iterator const End = LLVMBB->end();
686 BasicBlock::const_iterator BI = Begin;
687
707 BasicBlock::const_iterator BI = End;
708
709 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
710
711 // Setup an EH landing-pad block.
712 if (FuncInfo->MBB->isLandingPad())
713 PrepareEHLandingPad();
714
688715 // Lower any arguments needed in this block if this is the entry block.
689716 if (LLVMBB == &Fn.getEntryBlock())
690717 LowerArguments(LLVMBB);
691718
692 // Setup an EH landing-pad block.
693 if (BB->isLandingPad())
694 PrepareEHLandingPad(BB);
695
696719 // Before doing SelectionDAG ISel, see if FastISel has been requested.
697720 if (FastIS) {
721 FastIS->startNewBlock();
722
698723 // Emit code for any incoming arguments. This must happen before
699724 // beginning FastISel on the entry block.
700725 if (LLVMBB == &Fn.getEntryBlock()) {
701726 CurDAG->setRoot(SDB->getControlRoot());
702727 SDB->clear();
703 BB = CodeGenAndEmitDAG(BB);
728 CodeGenAndEmitDAG();
729
730 // If we inserted any instructions at the beginning, make a note of
731 // where they are, so we can be sure to emit subsequent instructions
732 // after them.
733 if (FuncInfo->InsertPt != FuncInfo->MBB->begin())
734 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt));
735 else
736 FastIS->setLastLocalValue(0);
704737 }
705 FastIS->startNewBlock(BB);
738
706739 // Do FastISel on as many instructions as possible.
707 for (; BI != End; ++BI) {
708 #if 0
709 // Defer instructions with no side effects; they'll be emitted
710 // on-demand later.
711 if (BI->isSafeToSpeculativelyExecute() &&
712 !FuncInfo->isExportedInst(BI))
740 for (; BI != Begin; --BI) {
741 const Instruction *Inst = llvm::prior(BI);
742
743 // If we no longer require this instruction, skip it.
744 if (!Inst->mayWriteToMemory() &&
745 !isa(Inst) &&
746 !isa(Inst) &&
747 !FuncInfo->isExportedInst(Inst))
713748 continue;
714 #endif
749
750 // Bottom-up: reset the insert pos at the top, after any local-value
751 // instructions.
752 FastIS->recomputeInsertPt();
715753
716754 // Try to select the instruction with FastISel.
717 if (FastIS->SelectInstruction(BI))
755 if (FastIS->SelectInstruction(Inst))
718756 continue;
719757
720758 // Then handle certain instructions as single-LLVM-Instruction blocks.
721 if (isa(BI)) {
759 if (isa(Inst)) {
722760 ++NumFastIselFailures;
723761 if (EnableFastISelVerbose || EnableFastISelAbort) {
724762 dbgs() << "FastISel missed call: ";
725 BI->dump();
763 Inst->dump();
726764 }
727765
728 if (!BI->getType()->isVoidTy() && !BI->use_empty()) {
729 unsigned &R = FuncInfo->ValueMap[BI];
766 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
767 unsigned &R = FuncInfo->ValueMap[Inst];
730768 if (!R)
731 R = FuncInfo->CreateRegs(BI->getType());
769 R = FuncInfo->CreateRegs(Inst->getType());
732770 }
733771
734772 bool HadTailCall = false;
735 BB = SelectBasicBlock(BB, BI, llvm::next(BI), HadTailCall);
773 SelectBasicBlock(Inst, BI, HadTailCall);
736774
737775 // If the call was emitted as a tail call, we're done with the block.
738776 if (HadTailCall) {
739 BI = End;
777 --BI;
740778 break;
741779 }
742780
743 // If the instruction was codegen'd with multiple blocks,
744 // inform the FastISel object where to resume inserting.
745 FastIS->setCurrentBlock(BB);
746781 continue;
747782 }
748783
749784 // Otherwise, give up on FastISel for the rest of the block.
750785 // For now, be a little lenient about non-branch terminators.
751 if (!isa(BI) || isa(BI)) {
786 if (!isa(Inst) || isa(Inst)) {
752787 ++NumFastIselFailures;
753788 if (EnableFastISelVerbose || EnableFastISelAbort) {
754789 dbgs() << "FastISel miss: ";
755 BI->dump();
790 Inst->dump();
756791 }
757792 if (EnableFastISelAbort)
758793 // The "fast" selector couldn't handle something and bailed.
761796 }
762797 break;
763798 }
799
800 FastIS->recomputeInsertPt();
764801 }
765802
766803 // Run SelectionDAG instruction selection on the remainder of the block
767804 // not handled by FastISel. If FastISel is not run, this is the entire
768805 // block.
769 if (BI != End) {
770 bool HadTailCall;
771 BB = SelectBasicBlock(BB, BI, End, HadTailCall);
772 }
773
774 FinishBasicBlock(BB);
806 bool HadTailCall;
807 SelectBasicBlock(Begin, BI, HadTailCall);
808
809 FinishBasicBlock();
775810 FuncInfo->PHINodesToUpdate.clear();
776811 }
777812
779814 }
780815
781816 void
782 SelectionDAGISel::FinishBasicBlock(MachineBasicBlock *BB) {
817 SelectionDAGISel::FinishBasicBlock() {
783818
784819 DEBUG(dbgs() << "Total amount of phi nodes to update: "
785820 << FuncInfo->PHINodesToUpdate.size() << "\n";
797832 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
798833 assert(PHI->isPHI() &&
799834 "This is not a machine PHI node that we are updating!");
800 if (!BB->isSuccessor(PHI->getParent()))
835 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
801836 continue;
802837 PHI->addOperand(
803838 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
804 PHI->addOperand(MachineOperand::CreateMBB(BB));
839 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
805840 }
806841 return;
807842 }
810845 // Lower header first, if it wasn't already lowered
811846 if (!SDB->BitTestCases[i].Emitted) {
812847 // Set the current basic block to the mbb we wish to insert the code into
813 BB = SDB->BitTestCases[i].Parent;
848 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
849 FuncInfo->InsertPt = FuncInfo->MBB->end();
814850 // Emit the code
815 SDB->visitBitTestHeader(SDB->BitTestCases[i], BB);
851 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
816852 CurDAG->setRoot(SDB->getRoot());
817853 SDB->clear();
818 BB = CodeGenAndEmitDAG(BB);
854 CodeGenAndEmitDAG();
819855 }
820856
821857 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
822858 // Set the current basic block to the mbb we wish to insert the code into
823 BB = SDB->BitTestCases[i].Cases[j].ThisBB;
859 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
860 FuncInfo->InsertPt = FuncInfo->MBB->end();
824861 // Emit the code
825862 if (j+1 != ej)
826863 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB,
827864 SDB->BitTestCases[i].Reg,
828865 SDB->BitTestCases[i].Cases[j],
829 BB);
866 FuncInfo->MBB);
830867 else
831868 SDB->visitBitTestCase(SDB->BitTestCases[i].Default,
832869 SDB->BitTestCases[i].Reg,
833870 SDB->BitTestCases[i].Cases[j],
834 BB);
871 FuncInfo->MBB);
835872
836873
837874 CurDAG->setRoot(SDB->getRoot());
838875 SDB->clear();
839 BB = CodeGenAndEmitDAG(BB);
876 CodeGenAndEmitDAG();
840877 }
841878
842879 // Update PHI Nodes
881918 // Lower header first, if it wasn't already lowered
882919 if (!SDB->JTCases[i].first.Emitted) {
883920 // Set the current basic block to the mbb we wish to insert the code into
884 BB = SDB->JTCases[i].first.HeaderBB;
921 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
922 FuncInfo->InsertPt = FuncInfo->MBB->end();
885923 // Emit the code
886924 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
887 BB);
925 FuncInfo->MBB);
888926 CurDAG->setRoot(SDB->getRoot());
889927 SDB->clear();
890 BB = CodeGenAndEmitDAG(BB);
928 CodeGenAndEmitDAG();
891929 }
892930
893931 // Set the current basic block to the mbb we wish to insert the code into
894 BB = SDB->JTCases[i].second.MBB;
932 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
933 FuncInfo->InsertPt = FuncInfo->MBB->end();
895934 // Emit the code
896935 SDB->visitJumpTable(SDB->JTCases[i].second);
897936 CurDAG->setRoot(SDB->getRoot());
898937 SDB->clear();
899 BB = CodeGenAndEmitDAG(BB);
938 CodeGenAndEmitDAG();
900939
901940 // Update PHI Nodes
902941 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
914953 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB));
915954 }
916955 // JT BB. Just iterate over successors here
917 if (BB->isSuccessor(PHIBB)) {
956 if (FuncInfo->MBB->isSuccessor(PHIBB)) {
918957 PHI->addOperand
919958 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
920959 false));
921 PHI->addOperand(MachineOperand::CreateMBB(BB));
960 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
922961 }
923962 }
924963 }
930969 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
931970 assert(PHI->isPHI() &&
932971 "This is not a machine PHI node that we are updating!");
933 if (BB->isSuccessor(PHI->getParent())) {
972 if (FuncInfo->MBB->isSuccessor(PHI->getParent())) {
934973 PHI->addOperand(
935974 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
936 PHI->addOperand(MachineOperand::CreateMBB(BB));
975 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
937976 }
938977 }
939978
941980 // additional DAGs necessary.
942981 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
943982 // Set the current basic block to the mbb we wish to insert the code into
944 MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB;
983 MachineBasicBlock *ThisBB = FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
984 FuncInfo->InsertPt = FuncInfo->MBB->end();
945985
946986 // Determine the unique successors.
947987 SmallVector Succs;
951991
952992 // Emit the code. Note that this could result in ThisBB being split, so
953993 // we need to check for updates.
954 SDB->visitSwitchCase(SDB->SwitchCases[i], BB);
994 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
955995 CurDAG->setRoot(SDB->getRoot());
956996 SDB->clear();
957 ThisBB = CodeGenAndEmitDAG(BB);
997 CodeGenAndEmitDAG();
998 ThisBB = FuncInfo->MBB;
958999
9591000 // Handle any PHI nodes in successors of this chunk, as if we were coming
9601001 // from the original BB before switch expansion. Note that PHI nodes can
9611002 // occur multiple times in PHINodesToUpdate. We have to be very careful to
9621003 // handle them the right number of times.
9631004 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
964 BB = Succs[i];
965 // BB may have been removed from the CFG if a branch was constant folded.
966 if (ThisBB->isSuccessor(BB)) {
967 for (MachineBasicBlock::iterator Phi = BB->begin();
968 Phi != BB->end() && Phi->isPHI();
1005 FuncInfo->MBB = Succs[i];
1006 FuncInfo->InsertPt = FuncInfo->MBB->end();
1007 // FuncInfo->MBB may have been removed from the CFG if a branch was
1008 // constant folded.
1009 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
1010 for (MachineBasicBlock::iterator Phi = FuncInfo->MBB->begin();
1011 Phi != FuncInfo->MBB->end() && Phi->isPHI();
9691012 ++Phi) {
9701013 // This value for this PHI node is recorded in PHINodesToUpdate.
9711014 for (unsigned pn = 0; ; ++pn) {
1919 #include "llvm/Target/TargetRegisterInfo.h"
2020 #include "llvm/GlobalVariable.h"
2121 #include "llvm/DerivedTypes.h"
22 #include "llvm/CodeGen/Analysis.h"
2223 #include "llvm/CodeGen/MachineFrameInfo.h"
2324 #include "llvm/CodeGen/MachineJumpTableInfo.h"
2425 #include "llvm/CodeGen/MachineFunction.h"
837838 return 1;
838839 }
839840
841 /// Get the EVTs and ArgFlags collections that represent the legalized return
842 /// type of the given function. This does not require a DAG or a return value,
843 /// and is suitable for use before any DAGs for the function are constructed.
844 /// TODO: Move this out of TargetLowering.cpp.
845 void llvm::GetReturnInfo(const Type* ReturnType, Attributes attr,
846 SmallVectorImpl &Outs,
847 const TargetLowering &TLI,
848 SmallVectorImpl *Offsets) {
849 SmallVector ValueVTs;
850 ComputeValueVTs(TLI, ReturnType, ValueVTs);
851 unsigned NumValues = ValueVTs.size();
852 if (NumValues == 0) return;
853 unsigned Offset = 0;
854
855 for (unsigned j = 0, f = NumValues; j != f; ++j) {
856 EVT VT = ValueVTs[j];
857 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
858
859 if (attr & Attribute::SExt)
860 ExtendKind = ISD::SIGN_EXTEND;
861 else if (attr & Attribute::ZExt)
862 ExtendKind = ISD::ZERO_EXTEND;
863
864 // FIXME: C calling convention requires the return type to be promoted to
865 // at least 32-bit. But this is not necessary for non-C calling
866 // conventions. The frontend should mark functions whose return values
867 // require promoting with signext or zeroext attributes.
868 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
869 EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
870 if (VT.bitsLT(MinVT))
871 VT = MinVT;
872 }
873
874 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
875 EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
876 unsigned PartSize = TLI.getTargetData()->getTypeAllocSize(
877 PartVT.getTypeForEVT(ReturnType->getContext()));
878
879 // 'inreg' on function refers to return value
880 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
881 if (attr & Attribute::InReg)
882 Flags.setInReg();
883
884 // Propagate extension type if any
885 if (attr & Attribute::SExt)
886 Flags.setSExt();
887 else if (attr & Attribute::ZExt)
888 Flags.setZExt();
889
890 for (unsigned i = 0; i < NumParts; ++i) {
891 Outs.push_back(ISD::OutputArg(Flags, PartVT, /*isFixed=*/true));
892 if (Offsets) {
893 Offsets->push_back(Offset);
894 Offset += PartSize;
895 }
896 }
897 }
898 }
899
840900 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
841901 /// function arguments in the caller parameter area. This is the actual
842902 /// alignment, not its logarithm.
3333 ///
3434 FunctionPass *createX86ISelDag(X86TargetMachine &TM,
3535 CodeGenOpt::Level OptLevel);
36
37 /// createGlobalBaseRegPass - This pass initializes a global base
38 /// register for PIC on x86-32.
39 FunctionPass* createGlobalBaseRegPass();
3640
3741 /// createX86FloatingPointStackifierPass - This function returns a pass which
3842 /// converts floating point register references and pseudo instructions into
2222 #include "llvm/GlobalVariable.h"
2323 #include "llvm/Instructions.h"
2424 #include "llvm/IntrinsicInst.h"
25 #include "llvm/CodeGen/Analysis.h"
2526 #include "llvm/CodeGen/FastISel.h"
2627 #include "llvm/CodeGen/FunctionLoweringInfo.h"
2728 #include "llvm/CodeGen/MachineConstantPool.h"
8384
8485 bool X86SelectStore(const Instruction *I);
8586
87 bool X86SelectRet(const Instruction *I);
88
8689 bool X86SelectCmp(const Instruction *I);
8790
8891 bool X86SelectZExt(const Instruction *I);
104107 bool X86SelectCall(const Instruction *I);
105108
106109 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool isTailCall = false);
110 CCAssignFn *CCAssignFnForRet(CallingConv::ID CC, bool isTailCall = false);
107111
108112 const X86InstrInfo *getInstrInfo() const {
109113 return getTargetMachine()->getInstrInfo();
175179 return CC_X86_32_GHC;
176180 else
177181 return CC_X86_32_C;
182 }
183
184 /// CCAssignFnForRet - Selects the correct CCAssignFn for a given calling
185 /// convention.
186 CCAssignFn *X86FastISel::CCAssignFnForRet(CallingConv::ID CC,
187 bool isTaillCall) {
188 if (Subtarget->is64Bit()) {
189 if (Subtarget->isTargetWin64())
190 return RetCC_X86_Win64_C;
191 else
192 return RetCC_X86_64_C;
193 }
194
195 return RetCC_X86_32_C;
178196 }
179197
180198 /// X86FastEmitLoad - Emit a machine instruction to load a value of type VT.
229247 }
230248
231249 ResultReg = createResultReg(RC);
232 addFullAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
250 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
251 DL, TII.get(Opc), ResultReg), AM);
233252 return true;
234253 }
235254
248267 case MVT::i1: {
249268 // Mask out all but lowest bit.
250269 unsigned AndResult = createResultReg(X86::GR8RegisterClass);
251 BuildMI(MBB, DL,
270 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
252271 TII.get(X86::AND8ri), AndResult).addReg(Val).addImm(1);
253272 Val = AndResult;
254273 }
265284 break;
266285 }
267286
268 addFullAddress(BuildMI(MBB, DL, TII.get(Opc)), AM).addReg(Val);
287 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
288 DL, TII.get(Opc)), AM).addReg(Val);
269289 return true;
270290 }
271291
293313 }
294314
295315 if (Opc) {
296 addFullAddress(BuildMI(MBB, DL, TII.get(Opc)), AM)
316 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
317 DL, TII.get(Opc)), AM)
297318 .addImm(Signed ? (uint64_t) CI->getSExtValue() :
298319 CI->getZExtValue());
299320 return true;
332353 // Don't walk into other basic blocks; it's possible we haven't
333354 // visited them yet, so the instructions may not yet be assigned
334355 // virtual registers.
335 if (FuncInfo.MBBMap[I->getParent()] != MBB)
356 if (FuncInfo.MBBMap[I->getParent()] != FuncInfo.MBB)
336357 return false;
337358
338359 Opcode = I->getOpcode();
517538 StubAM.GV = GV;
518539 StubAM.GVOpFlags = GVFlags;
519540
541 // Prepare for inserting code in the local-value area.
542 MachineBasicBlock::iterator SaveInsertPt = enterLocalValueArea();
543
520544 if (TLI.getPointerTy() == MVT::i64) {
521545 Opc = X86::MOV64rm;
522546 RC = X86::GR64RegisterClass;
529553 }
530554
531555 LoadReg = createResultReg(RC);
532 addFullAddress(BuildMI(MBB, DL, TII.get(Opc), LoadReg), StubAM);
533
556 MachineInstrBuilder LoadMI =
557 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), LoadReg);
558 addFullAddress(LoadMI, StubAM);
559
560 // Ok, back to normal mode.
561 leaveLocalValueArea(SaveInsertPt);
562
534563 // Prevent loading GV stub multiple times in same MBB.
535564 LocalValueMap[V] = LoadReg;
536565 }
653682 return false;
654683
655684 return X86FastEmitStore(VT, I->getOperand(0), AM);
685 }
686
687 /// X86SelectRet - Select and emit code to implement ret instructions.
688 bool X86FastISel::X86SelectRet(const Instruction *I) {
689 const ReturnInst *Ret = cast(I);
690 const Function &F = *I->getParent()->getParent();
691
692 if (!FuncInfo.CanLowerReturn)
693 return false;
694
695 CallingConv::ID CC = F.getCallingConv();
696 if (CC != CallingConv::C &&
697 CC != CallingConv::Fast &&
698 CC != CallingConv::X86_FastCall)
699 return false;
700
701 if (Subtarget->isTargetWin64())
702 return false;
703
704 // Don't handle popping bytes on return for now.
705 if (FuncInfo.MF->getInfo()
706 ->getBytesToPopOnReturn() != 0)
707 return 0;
708
709 // fastcc with -tailcallopt is intended to provide a guaranteed
710 // tail call optimization. Fastisel doesn't know how to do that.
711 if (CC == CallingConv::Fast && GuaranteedTailCallOpt)
712 return false;
713
714 // Let SDISel handle vararg functions.
715 if (F.isVarArg())
716 return false;
717
718 if (Ret->getNumOperands() > 0) {
719 SmallVector Outs;
720 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
721 Outs, TLI);
722
723 // Analyze operands of the call, assigning locations to each operand.
724 SmallVector ValLocs;
725 CCState CCInfo(CC, F.isVarArg(), TM, ValLocs, I->getContext());
726 CCInfo.AnalyzeReturn(Outs, CCAssignFnForRet(CC));
727
728 const Value *RV = Ret->getOperand(0);
729 unsigned Reg = getRegForValue(RV);
730 if (Reg == 0)
731 return false;
732
733 // Only handle a single return value for now.
734 if (ValLocs.size() != 1)
735 return false;
736
737 CCValAssign &VA = ValLocs[0];
738
739 // Don't bother handling odd stuff for now.
740 if (VA.getLocInfo() != CCValAssign::Full)
741 return false;
742 // Only handle register returns for now.
743 if (!VA.isRegLoc())
744 return false;
745 // TODO: For now, don't try to handle cases where getLocInfo()
746 // says Full but the types don't match.
747 if (VA.getValVT() != TLI.getValueType(RV->getType()))
748 return false;
749
750 // The calling-convention tables for x87 returns don't tell
751 // the whole story.
752 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1)
753 return false;
754
755 // Make the copy.
756 unsigned SrcReg = Reg + VA.getValNo();
757 unsigned DstReg = VA.getLocReg();
758 const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg);
759 const TargetRegisterClass* DstRC = TRI.getMinimalPhysRegClass(DstReg);
760 bool Emitted = TII.copyRegToReg(*FuncInfo.MBB, FuncInfo.InsertPt,
761 DstReg, SrcReg, DstRC, SrcRC, DL);
762
763 // If the target couldn't make the copy for some reason, bail.
764 if (!Emitted)
765 return false;
766
767 // Mark the register as live out of the function.
768 MRI.addLiveOut(VA.getLocReg());
769 }
770
771 // Now emit the RET.
772 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::RET));
773 return true;
656774 }
657775
658776 /// X86SelectLoad - Select and emit code to implement load instructions.
719837 // CMPri, otherwise use CMPrr.
720838 if (const ConstantInt *Op1C = dyn_cast(Op1)) {
721839 if (unsigned CompareImmOpc = X86ChooseCmpImmediateOpcode(VT, Op1C)) {
722 BuildMI(MBB, DL, TII.get(CompareImmOpc)).addReg(Op0Reg)
723 .addImm(Op1C->getSExtValue());
840 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CompareImmOpc))
841 .addReg(Op0Reg)
842 .addImm(Op1C->getSExtValue());
724843 return true;
725844 }
726845 }
730849
731850 unsigned Op1Reg = getRegForValue(Op1);
732851 if (Op1Reg == 0) return false;
733 BuildMI(MBB, DL, TII.get(CompareOpc)).addReg(Op0Reg).addReg(Op1Reg);
852 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CompareOpc))
853 .addReg(Op0Reg)
854 .addReg(Op1Reg);
734855
735856 return true;
736857 }
752873
753874 unsigned EReg = createResultReg(&X86::GR8RegClass);
754875 unsigned NPReg = createResultReg(&X86::GR8RegClass);
755 BuildMI(MBB, DL, TII.get(X86::SETEr), EReg);
756 BuildMI(MBB, DL, TII.get(X86::SETNPr), NPReg);
757 BuildMI(MBB, DL,
876 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::SETEr), EReg);
877 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
878 TII.get(X86::SETNPr), NPReg);
879 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
758880 TII.get(X86::AND8rr), ResultReg).addReg(NPReg).addReg(EReg);
759881 UpdateValueMap(I, ResultReg);
760882 return true;
765887
766888 unsigned NEReg = createResultReg(&X86::GR8RegClass);
767889 unsigned PReg = createResultReg(&X86::GR8RegClass);
768 BuildMI(MBB, DL, TII.get(X86::SETNEr), NEReg);
769 BuildMI(MBB, DL, TII.get(X86::SETPr), PReg);
770 BuildMI(MBB, DL, TII.get(X86::OR8rr), ResultReg).addReg(PReg).addReg(NEReg);
890 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
891 TII.get(X86::SETNEr), NEReg);
892 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
893 TII.get(X86::SETPr), PReg);
894 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
895 TII.get(X86::OR8rr), ResultReg)
896 .addReg(PReg).addReg(NEReg);
771897 UpdateValueMap(I, ResultReg);
772898 return true;
773899 }
806932 if (!X86FastEmitCompare(Op0, Op1, VT))
807933 return false;
808934
809 BuildMI(MBB, DL, TII.get(SetCCOpc), ResultReg);
935 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(SetCCOpc), ResultReg);
810936 UpdateValueMap(I, ResultReg);
811937 return true;
812938 }
842968
843969 // Try to take advantage of fallthrough opportunities.
844970 CmpInst::Predicate Predicate = CI->getPredicate();
845 if (MBB->isLayoutSuccessor(TrueMBB)) {
971 if (FuncInfo.MBB->isLayoutSuccessor(TrueMBB)) {
846972 std::swap(TrueMBB, FalseMBB);
847973 Predicate = CmpInst::getInversePredicate(Predicate);
848974 }
8911017 if (!X86FastEmitCompare(Op0, Op1, VT))
8921018 return false;
8931019
894 BuildMI(MBB, DL, TII.get(BranchOpc)).addMBB(TrueMBB);
1020 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BranchOpc))
1021 .addMBB(TrueMBB);
8951022
8961023 if (Predicate == CmpInst::FCMP_UNE) {
8971024 // X86 requires a second branch to handle UNE (and OEQ,
8981025 // which is mapped to UNE above).
899 BuildMI(MBB, DL, TII.get(X86::JP_4)).addMBB(TrueMBB);
1026 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::JP_4))
1027 .addMBB(TrueMBB);
9001028 }
9011029
9021030 FastEmitBranch(FalseMBB, DL);
903 MBB->addSuccessor(TrueMBB);
1031 FuncInfo.MBB->addSuccessor(TrueMBB);
9041032 return true;
9051033 }
9061034 } else if (ExtractValueInst *EI =
9261054 unsigned Reg = getRegForValue(EI);
9271055
9281056 for (MachineBasicBlock::const_reverse_iterator
929 RI = MBB->rbegin(), RE = MBB->rend(); RI != RE; ++RI) {
1057 RI = FuncInfo.MBB->rbegin(), RE = FuncInfo.MBB->rend();
1058 RI != RE; ++RI) {
9301059 const MachineInstr &MI = *RI;
9311060
9321061 if (MI.definesRegister(Reg)) {
9511080 unsigned OpCode = SetMI->getOpcode();
9521081
9531082 if (OpCode == X86::SETOr || OpCode == X86::SETBr) {
954 BuildMI(MBB, DL, TII.get(OpCode == X86::SETOr ?
955 X86::JO_4 : X86::JB_4))
1083 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1084 TII.get(OpCode == X86::SETOr ? X86::JO_4 : X86::JB_4))
9561085 .addMBB(TrueMBB);
9571086 FastEmitBranch(FalseMBB, DL);
958 MBB->addSuccessor(TrueMBB);
1087 FuncInfo.MBB->addSuccessor(TrueMBB);
9591088 return true;
9601089 }
9611090 }
9671096 unsigned OpReg = getRegForValue(BI->getCondition());
9681097 if (OpReg == 0) return false;
9691098
970 BuildMI(MBB, DL, TII.get(X86::TEST8rr)).addReg(OpReg).addReg(OpReg);
971 BuildMI(MBB, DL, TII.get(X86::JNE_4)).addMBB(TrueMBB);
1099 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::TEST8rr))
1100 .addReg(OpReg).addReg(OpReg);
1101 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::JNE_4))
1102 .addMBB(TrueMBB);
9721103 FastEmitBranch(FalseMBB, DL);
973 MBB->addSuccessor(TrueMBB);
1104 FuncInfo.MBB->addSuccessor(TrueMBB);
9741105 return true;
9751106 }
9761107
10271158 // Fold immediate in shl(x,3).
10281159 if (const ConstantInt *CI = dyn_cast(I->getOperand(1))) {
10291160 unsigned ResultReg = createResultReg(RC);
1030 BuildMI(MBB, DL, TII.get(OpImm),
1161 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(OpImm),
10311162 ResultReg).addReg(Op0Reg).addImm(CI->getZExtValue() & 0xff);
10321163 UpdateValueMap(I, ResultReg);
10331164 return true;
10351166
10361167 unsigned Op1Reg = getRegForValue(I->getOperand(1));
10371168 if (Op1Reg == 0) return false;
1038 TII.copyRegToReg(*MBB, MBB->end(), CReg, Op1Reg, RC, RC, DL);
1169 TII.copyRegToReg(*FuncInfo.MBB, FuncInfo.InsertPt,
1170 CReg, Op1Reg, RC, RC, DL);
10391171
10401172 // The shift instruction uses X86::CL. If we defined a super-register
10411173 // of X86::CL, emit a subreg KILL to precisely describe what we're doing here.
10421174 if (CReg != X86::CL)
1043 BuildMI(MBB, DL, TII.get(TargetOpcode::KILL), X86::CL)
1175 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1176 TII.get(TargetOpcode::KILL), X86::CL)
10441177 .addReg(CReg, RegState::Kill);
10451178
10461179 unsigned ResultReg = createResultReg(RC);
1047 BuildMI(MBB, DL, TII.get(OpReg), ResultReg).addReg(Op0Reg);
1180 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(OpReg), ResultReg)
1181 .addReg(Op0Reg);
10481182 UpdateValueMap(I, ResultReg);
10491183 return true;
10501184 }
10761210 unsigned Op2Reg = getRegForValue(I->getOperand(2));
10771211 if (Op2Reg == 0) return false;
10781212
1079 BuildMI(MBB, DL, TII.get(X86::TEST8rr)).addReg(Op0Reg).addReg(Op0Reg);
1213 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::TEST8rr))
1214 .addReg(Op0Reg).addReg(Op0Reg);
10801215 unsigned ResultReg = createResultReg(RC);
1081 BuildMI(MBB, DL, TII.get(Opc), ResultReg).addReg(Op1Reg).addReg(Op2Reg);
1216 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg)
1217 .addReg(Op1Reg).addReg(Op2Reg);
10821218 UpdateValueMap(I, ResultReg);
10831219 return true;
10841220 }
10921228 unsigned OpReg = getRegForValue(V);
10931229 if (OpReg == 0) return false;
10941230 unsigned ResultReg = createResultReg(X86::FR64RegisterClass);
1095 BuildMI(MBB, DL, TII.get(X86::CVTSS2SDrr), ResultReg).addReg(OpReg);
1231 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1232 TII.get(X86::CVTSS2SDrr), ResultReg)
1233 .addReg(OpReg);
10961234 UpdateValueMap(I, ResultReg);
10971235 return true;
10981236 }
11091247 unsigned OpReg = getRegForValue(V);
11101248 if (OpReg == 0) return false;
11111249 unsigned ResultReg = createResultReg(X86::FR32RegisterClass);
1112 BuildMI(MBB, DL, TII.get(X86::CVTSD2SSrr), ResultReg).addReg(OpReg);
1250 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1251 TII.get(X86::CVTSD2SSrr), ResultReg)
1252 .addReg(OpReg);
11131253 UpdateValueMap(I, ResultReg);
11141254 return true;
11151255 }
11441284 const TargetRegisterClass *CopyRC = (SrcVT == MVT::i16)
11451285 ? X86::GR16_ABCDRegisterClass : X86::GR32_ABCDRegisterClass;
11461286 unsigned CopyReg = createResultReg(CopyRC);
1147 BuildMI(MBB, DL, TII.get(CopyOpc), CopyReg).addReg(InputReg);
1287 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CopyOpc), CopyReg)
1288 .addReg(InputReg);
11481289
11491290 // Then issue an extract_subreg.
11501291 unsigned ResultReg = FastEmitInst_extractsubreg(MVT::i8,
11651306 switch (CI->getIntrinsicID()) {
11661307 default: break;
11671308 case Intrinsic::sadd_with_overflow:
1168 case Intrinsic::uadd_with_overflow:
1309 case Intrinsic::uadd_with_overflow: {
11691310 // Cheat a little. We know that the registers for "add" and "seto" are
11701311 // allocated sequentially. However, we only keep track of the register
11711312 // for "add" in the value map. Use extractvalue's index to get the
11721313 // correct register for "seto".
1173 UpdateValueMap(I, lookUpRegForValue(Agg) + *EI->idx_begin());
1314 unsigned OpReg = getRegForValue(Agg);
1315 if (OpReg == 0)
1316 return false;
1317 UpdateValueMap(I, OpReg + *EI->idx_begin());
11741318 return true;
1319 }
11751320 }
11761321 }
11771322
12161361 return false;
12171362
12181363 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
1219 BuildMI(MBB, DL, TII.get(OpC), ResultReg).
1364 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(OpC), ResultReg).
12201365 addImm(CI->isZero() ? -1ULL : 0);
12211366 UpdateValueMap(&I, ResultReg);
12221367 return true;
12301375 const TargetInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE);
12311376 // FIXME may need to add RegState::Debug to any registers produced,
12321377 // although ESP/EBP should be the only ones at the moment.
1233 addFullAddress(BuildMI(MBB, DL, II), AM).addImm(0).
1234 addMetadata(DI->getVariable());
1378 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II), AM).
1379 addImm(0).addMetadata(DI->getVariable());
12351380 return true;
12361381 }
12371382 case Intrinsic::trap: {
1238 BuildMI(MBB, DL, TII.get(X86::TRAP));
1383 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::TRAP));
12391384 return true;
12401385 }
12411386 case Intrinsic::sadd_with_overflow:
12711416 return false;
12721417
12731418 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
1274 BuildMI(MBB, DL, TII.get(OpC), ResultReg).addReg(Reg1).addReg(Reg2);
1419 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(OpC), ResultReg)
1420 .addReg(Reg1).addReg(Reg2);
12751421 unsigned DestReg1 = UpdateValueMap(&I, ResultReg);
12761422
12771423 // If the add with overflow is an intra-block value then we just want to
12891435 unsigned Opc = X86::SETBr;
12901436 if (I.getIntrinsicID() == Intrinsic::sadd_with_overflow)
12911437 Opc = X86::SETOr;
1292 BuildMI(MBB, DL, TII.get(Opc), ResultReg);
1438 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg);
12931439 return true;
12941440 }
12951441 }
14161562
14171563 // Issue CALLSEQ_START
14181564 unsigned AdjStackDown = TM.getRegisterInfo()->getCallFrameSetupOpcode();
1419 BuildMI(MBB, DL, TII.get(AdjStackDown)).addImm(NumBytes);
1565 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(AdjStackDown))
1566 .addImm(NumBytes);
14201567
14211568 // Process argument: walk the register/memloc assignments, inserting
14221569 // copies / loads.
14721619
14731620 if (VA.isRegLoc()) {
14741621 TargetRegisterClass* RC = TLI.getRegClassFor(ArgVT);
1475 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), VA.getLocReg(),
1476 Arg, RC, RC, DL);
1622 bool Emitted = TII.copyRegToReg(*FuncInfo.MBB, FuncInfo.InsertPt,
1623 VA.getLocReg(), Arg, RC, RC, DL);
14771624 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted;
14781625 Emitted = true;
14791626 RegArgs.push_back(VA.getLocReg());
14991646 if (Subtarget->isPICStyleGOT()) {
15001647 TargetRegisterClass *RC = X86::GR32RegisterClass;
15011648 unsigned Base = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF);
1502 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), X86::EBX, Base, RC, RC,
1503 DL);
1649 bool Emitted = TII.copyRegToReg(*FuncInfo.MBB, FuncInfo.InsertPt,
1650 X86::EBX, Base, RC, RC, DL);
15041651 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted;
15051652 Emitted = true;
15061653 }
15101657 if (CalleeOp) {
15111658 // Register-indirect call.
15121659 unsigned CallOpc = Subtarget->is64Bit() ? X86::CALL64r : X86::CALL32r;
1513 MIB = BuildMI(MBB, DL, TII.get(CallOpc)).addReg(CalleeOp);
1660 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc))
1661 .addReg(CalleeOp);
15141662
15151663 } else {
15161664 // Direct call.
15391687 }
15401688
15411689
1542 MIB = BuildMI(MBB, DL, TII.get(CallOpc)).addGlobalAddress(GV, 0, OpFlags);
1690 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc))
1691 .addGlobalAddress(GV, 0, OpFlags);
15431692 }
15441693
15451694 // Add an implicit use GOT pointer in EBX.
15521701
15531702 // Issue CALLSEQ_END
15541703 unsigned AdjStackUp = TM.getRegisterInfo()->getCallFrameDestroyOpcode();
1555 BuildMI(MBB, DL, TII.get(AdjStackUp)).addImm(NumBytes).addImm(0);
1704 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(AdjStackUp))
1705 .addImm(NumBytes).addImm(0);
15561706
15571707 // Now handle call return value (if any).
15581708 SmallVector UsedRegs;
15791729 }
15801730
15811731 unsigned ResultReg = createResultReg(DstRC);
1582 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1732 bool Emitted = TII.copyRegToReg(*FuncInfo.MBB, FuncInfo.InsertPt, ResultReg,
15831733 RVLocs[0].getLocReg(), DstRC, SrcRC, DL);
15841734 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted;
15851735 Emitted = true;
15931743 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64;
15941744 unsigned MemSize = ResVT.getSizeInBits()/8;
15951745 int FI = MFI.CreateStackObject(MemSize, MemSize, false);
1596 addFrameReference(BuildMI(MBB, DL, TII.get(Opc)), FI).addReg(ResultReg);
1746 addFrameReference(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1747 TII.get(Opc)), FI)
1748 .addReg(ResultReg);
15971749 DstRC = ResVT == MVT::f32
15981750 ? X86::FR32RegisterClass : X86::FR64RegisterClass;
15991751 Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm;
16001752 ResultReg = createResultReg(DstRC);
1601 addFrameReference(BuildMI(MBB, DL, TII.get(Opc), ResultReg), FI);
1753 addFrameReference(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1754 TII.get(Opc), ResultReg), FI);
16021755 }
16031756
16041757 if (AndToI1) {
16051758 // Mask out all but lowest bit for some call which produces an i1.
16061759 unsigned AndResult = createResultReg(X86::GR8RegisterClass);
1607 BuildMI(MBB, DL,
1760 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
16081761 TII.get(X86::AND8ri), AndResult).addReg(ResultReg).addImm(1);
16091762 ResultReg = AndResult;
16101763 }
16271780 return X86SelectLoad(I);
16281781 case Instruction::Store:
16291782 return X86SelectStore(I);
1783 case Instruction::Ret:
1784 return X86SelectRet(I);
16301785 case Instruction::ICmp:
16311786 case Instruction::FCmp:
16321787 return X86SelectCmp(I);
17271882 else
17281883 Opc = X86::LEA64r;
17291884 unsigned ResultReg = createResultReg(RC);
1730 addFullAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
1885 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1886 TII.get(Opc), ResultReg), AM);
17311887 return ResultReg;
17321888 }
17331889 return 0;
17571913 // Create the load from the constant pool.
17581914 unsigned MCPOffset = MCP.getConstantPoolIndex(C, Align);
17591915 unsigned ResultReg = createResultReg(RC);
1760 addConstantPoolReference(BuildMI(MBB, DL, TII.get(Opc), ResultReg),
1916 addConstantPoolReference(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1917 TII.get(Opc), ResultReg),
17611918 MCPOffset, PICBase, OpFlag);
17621919
17631920 return ResultReg;
17801937 unsigned Opc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
17811938 TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy());
17821939 unsigned ResultReg = createResultReg(RC);
1783 addFullAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
1940 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1941 TII.get(Opc), ResultReg), AM);
17841942 return ResultReg;
17851943 }
17861944
12171217
12181218 bool
12191219 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
1220 const SmallVectorImpl &OutTys,
1221 const SmallVectorImplArgFlagsTy> &ArgsFlags,
1220 const SmallVectorImplOutputArg> &Outs,
12221221 LLVMContext &Context) const {
12231222 SmallVector RVLocs;
12241223 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
12251224 RVLocs, Context);
1226 return CCInfo.CheckReturn(OutTys, ArgsFlags, RetCC_X86);
1225 return CCInfo.CheckReturn(Outs, RetCC_X86);
12271226 }
12281227
12291228 SDValue
739739
740740 virtual bool
741741 CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
742 const SmallVectorImpl &OutTys,
743 const SmallVectorImplArgFlagsTy> &ArgsFlags,
742 const SmallVectorImplOutputArg> &Outs,
744743 LLVMContext &Context) const;
745744
746745 void ReplaceATOMIC_BINARY_64(SDNode *N, SmallVectorImpl &Results,
26412641 if (TM.getSubtarget().is64Bit())
26422642 PICBase = X86::RIP;
26432643 else
2644 // FIXME: PICBase = TM.getInstrInfo()->getGlobalBaseReg(&MF);
2644 // FIXME: PICBase = getGlobalBaseReg(&MF);
26452645 // This doesn't work for several reasons.
26462646 // 1. GlobalBaseReg may have been spilled.
26472647 // 2. It may not be live at MI.
37163716 /// the global base register value. Output instructions required to
37173717 /// initialize the register in the function entry block, if necessary.
37183718 ///
3719 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
3720 ///
37193721 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
37203722 assert(!TM.getSubtarget().is64Bit() &&
37213723 "X86-64 PIC uses RIP relative addressing");
37253727 if (GlobalBaseReg != 0)
37263728 return GlobalBaseReg;
37273729
3728 // Insert the set of GlobalBaseReg into the first MBB of the function
3729 MachineBasicBlock &FirstMBB = MF->front();
3730 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
3731 DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
3730 // Create the register. The code to initialize it is inserted
3731 // later, by the CGBR pass (below).
37323732 MachineRegisterInfo &RegInfo = MF->getRegInfo();
3733 unsigned PC = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3734
3735 const TargetInstrInfo *TII = TM.getInstrInfo();
3736 // Operand of MovePCtoStack is completely ignored by asm printer. It's
3737 // only used in JIT code emission as displacement to pc.
3738 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
3739
3740 // If we're using vanilla 'GOT' PIC style, we should use relative addressing
3741 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
3742 if (TM.getSubtarget().isPICStyleGOT()) {
3743 GlobalBaseReg = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3744 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
3745 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
3746 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
3747 X86II::MO_GOT_ABSOLUTE_ADDRESS);
3748 } else {
3749 GlobalBaseReg = PC;
3750 }
3751
3733 GlobalBaseReg = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
37523734 X86FI->setGlobalBaseReg(GlobalBaseReg);
37533735 return GlobalBaseReg;
37543736 }
38053787 void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
38063788 NopInst.setOpcode(X86::NOOP);
38073789 }
3790
3791 namespace {
3792 /// CGBR - Create Global Base Reg pass. This initializes the PIC
3793 /// global base register for x86-32.
3794 struct CGBR : public MachineFunctionPass {
3795 static char ID;
3796 CGBR() : MachineFunctionPass(&ID) {}
3797
3798 virtual bool runOnMachineFunction(MachineFunction &MF) {
3799 const X86TargetMachine *TM =
3800 static_cast(&MF.getTarget());
3801
3802 assert(!TM->getSubtarget().is64Bit() &&
3803 "X86-64 PIC uses RIP relative addressing");
3804
3805 // Only emit a global base reg in PIC mode.
3806 if (TM->getRelocationModel() != Reloc::PIC_)
3807 return false;
3808
3809 // Insert the set of GlobalBaseReg into the first MBB of the function
3810 MachineBasicBlock &FirstMBB = MF.front();
3811 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
3812 DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
3813 MachineRegisterInfo &RegInfo = MF.getRegInfo();
3814 const X86InstrInfo *TII = TM->getInstrInfo();
3815
3816 unsigned PC;
3817 if (TM->getSubtarget().isPICStyleGOT())
3818 PC = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3819 else
3820 PC = TII->getGlobalBaseReg(&MF);
3821
3822 // Operand of MovePCtoStack is completely ignored by asm printer. It's
3823 // only used in JIT code emission as displacement to pc.
3824 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
3825
3826 // If we're using vanilla 'GOT' PIC style, we should use relative addressing
3827 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
3828 if (TM->getSubtarget().isPICStyleGOT()) {
3829 unsigned GlobalBaseReg = TII->getGlobalBaseReg(&MF);
3830 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
3831 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
3832 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
3833 X86II::MO_GOT_ABSOLUTE_ADDRESS);
3834 }
3835
3836 return true;
3837 }
3838
3839 virtual const char *getPassName() const {
3840 return "X86 PIC Global Base Reg Initialization";
3841 }
3842
3843 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
3844 AU.setPreservesCFG();
3845 MachineFunctionPass::getAnalysisUsage(AU);
3846 }
3847 };
3848 }
3849
3850 char CGBR::ID = 0;
3851 FunctionPass*
3852 llvm::createGlobalBaseRegPass() { return new CGBR(); }
172172 // Install an instruction selector.
173173 PM.add(createX86ISelDag(*this, OptLevel));
174174
175 // For 32-bit, prepend instructions to set the "global base reg" for PIC.
176 if (!Subtarget.is64Bit())
177 PM.add(createGlobalBaseRegPass());
178
175179 return false;
176180 }
177181
11341134
11351135 bool XCoreTargetLowering::
11361136 CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
1137 const SmallVectorImpl &OutTys,
1138 const SmallVectorImplArgFlagsTy> &ArgsFlags,
1137 const SmallVectorImplOutputArg> &Outs,
11391138 LLVMContext &Context) const {
11401139 SmallVector RVLocs;
11411140 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
11421141 RVLocs, Context);
1143 return CCInfo.CheckReturn(OutTys, ArgsFlags, RetCC_XCore);
1142 return CCInfo.CheckReturn(Outs, RetCC_XCore);
11441143 }
11451144
11461145 SDValue
192192
193193 virtual bool
194194 CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
195 const SmallVectorImpl &OutTys,
196 const SmallVectorImplArgFlagsTy> &ArgsFlags,
195 const SmallVectorImplOutputArg> &ArgsFlags,
197196 LLVMContext &Context) const;
198197 };
199198 }
44 ; CHECK: foo:
55 ; CHECK-NEXT: movq %rdi, -8(%rsp)
66 ; CHECK-NEXT: movq %rsi, -16(%rsp)
7 ; CHECK: movsd 128(%rsi,%rdi,8), %xmm0
7 ; CHECK-NEXT: movsd 128(%rsi,%rdi,8), %xmm0
88 ; CHECK-NEXT: ret
99
1010 define double @foo(i64 %x, double* %p) nounwind {
0 ; RUN: llc -march=x86 -relocation-model=pic
1
2 ; This should use flds to set the return value.
3 ; CHECK: test0:
4 ; CHECK: flds
5 ; CHECK: ret
6 @G = external global float
7 define float @test0() nounwind {
8 %t = load float* @G
9 ret float %t
10 }
11
12 ; This should pop 4 bytes on return.
13 ; CHECK: test1:
14 ; CHECK: ret $4
15 define void @test1({i32, i32, i32, i32}* sret %p) nounwind {
16 store {i32, i32, i32, i32} zeroinitializer, {i32, i32, i32, i32}* %p
17 ret void
18 }
19
20 ; Properly initialize the pic base.
21 ; CHECK: test2:
22 ; CHECK-NOT: HHH
23 ; CHECK: call{{.*}}L2$pb
24 ; CHECK-NEXT: L2$pb:
25 ; CHECK-NEXT: pop
26 ; CHECK: HHH
27 ; CHECK: ret
28 @HHH = external global i32
29 define i32 @test2() nounwind {
30 %t = load i32* @H
31 ret i32 %t
32 }
4848 ret i32 %tmp2
4949 }
5050
51 define i1 @ptrtoint_i1(i8* %p) nounwind {
51 define void @ptrtoint_i1(i8* %p, i1* %q) nounwind {
5252 %t = ptrtoint i8* %p to i1
53 ret i1 %t
53 store i1 %t, i1* %q
54 ret void
5455 }
5556 define i8* @inttoptr_i1(i1 %p) nounwind {
5657 %t = inttoptr i1 %p to i8*
8586 ret i8 %tmp
8687 }
8788
88 define void @store_i1(i1* %p, i1 %t) nounwind {
89 store i1 %t, i1* %p
89 define void @load_store_i1(i1* %p, i1* %q) nounwind {
90 %t = load i1* %p
91 store i1 %t, i1* %q
9092 ret void
9193 }
92 define i1 @load_i1(i1* %p) nounwind {
93 %t = load i1* %p
94 ret i1 %t
95 }
431431
432432 for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) {
433433 if ((*Memo.PhysRegs)[i] != "")
434 OS << " TII.copyRegToReg(*MBB, MBB->end(), "
434 OS << " TII.copyRegToReg(*FuncInfo.MBB, FuncInfo.InsertPt, "
435435 << (*Memo.PhysRegs)[i] << ", Op" << i << ", "
436436 << "TM.getRegisterInfo()->getPhysicalRegisterRegClass("
437437 << (*Memo.PhysRegs)[i] << "), "
525525
526526 for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) {
527527 if ((*Memo.PhysRegs)[i] != "")
528 OS << " TII.copyRegToReg(*MBB, MBB->end(), "
528 OS << " TII.copyRegToReg(*FuncInfo.MBB, FuncInfo.InsertPt, "
529529 << (*Memo.PhysRegs)[i] << ", Op" << i << ", "
530530 << "TM.getRegisterInfo()->getPhysicalRegisterRegClass("
531531 << (*Memo.PhysRegs)[i] << "), "