llvm.org GIT mirror llvm / 83ec4b6
Wrap MVT::ValueType in a struct to get type safety and better control the abstraction. Rename the type to MVT. To update out-of-tree patches, the main thing to do is to rename MVT::ValueType to MVT, and rewrite expressions like MVT::getSizeInBits(VT) in the form VT.getSizeInBits(). Use VT.getSimpleVT() to extract a MVT::SimpleValueType for use in switch statements (you will get an assert failure if VT is an extended value type - these shouldn't exist after type legalization). This results in a small speedup of codegen and no new testsuite failures (x86-64 linux). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52044 91177308-0d34-0410-b5e6-96231b3b80d8 Duncan Sands 12 years ago
68 changed file(s) with 2899 addition(s) and 2882 deletion(s). Raw diff Collapse all Expand all
789789 edges are represented by instances of the SDOperand class, which is
790790 a <SDNode, unsigned> pair, indicating the node and result
791791 value being used, respectively. Each value produced by an SDNode has
792 an associated MVT::ValueType indicating what type the value is.

792 an associated MVT (Machine Value Type) indicating what the type of the
793 value is.

793794
794795

SelectionDAGs contain two different kinds of values: those that represent

795796 data flow and those that represent control flow dependencies. Data values are
4848 LocInfo HTP : 7;
4949
5050 /// ValVT - The type of the value being assigned.
51 MVT::ValueType ValVT;
51 MVT ValVT;
5252
5353 /// LocVT - The type of the location being assigned to.
54 MVT::ValueType LocVT;
54 MVT LocVT;
5555 public:
5656
57 static CCValAssign getReg(unsigned ValNo, MVT::ValueType ValVT,
58 unsigned RegNo, MVT::ValueType LocVT,
57 static CCValAssign getReg(unsigned ValNo, MVT ValVT,
58 unsigned RegNo, MVT LocVT,
5959 LocInfo HTP) {
6060 CCValAssign Ret;
6161 Ret.ValNo = ValNo;
6666 Ret.LocVT = LocVT;
6767 return Ret;
6868 }
69 static CCValAssign getMem(unsigned ValNo, MVT::ValueType ValVT,
70 unsigned Offset, MVT::ValueType LocVT,
69 static CCValAssign getMem(unsigned ValNo, MVT ValVT,
70 unsigned Offset, MVT LocVT,
7171 LocInfo HTP) {
7272 CCValAssign Ret;
7373 Ret.ValNo = ValNo;
8080 }
8181
8282 unsigned getValNo() const { return ValNo; }
83 MVT::ValueType getValVT() const { return ValVT; }
83 MVT getValVT() const { return ValVT; }
8484
8585 bool isRegLoc() const { return !isMem; }
8686 bool isMemLoc() const { return isMem; }
8787
8888 unsigned getLocReg() const { assert(isRegLoc()); return Loc; }
8989 unsigned getLocMemOffset() const { assert(isMemLoc()); return Loc; }
90 MVT::ValueType getLocVT() const { return LocVT; }
90 MVT getLocVT() const { return LocVT; }
9191
9292 LocInfo getLocInfo() const { return HTP; }
9393 };
9595
9696 /// CCAssignFn - This function assigns a location for Val, updating State to
9797 /// reflect the change.
98 typedef bool CCAssignFn(unsigned ValNo, MVT::ValueType ValVT,
99 MVT::ValueType LocVT, CCValAssign::LocInfo LocInfo,
98 typedef bool CCAssignFn(unsigned ValNo, MVT ValVT,
99 MVT LocVT, CCValAssign::LocInfo LocInfo,
100100 ISD::ArgFlagsTy ArgFlags, CCState &State);
101101
102102
216216 // HandleByVal - Allocate a stack slot large enough to pass an argument by
217217 // value. The size and alignment information of the argument is encoded in its
218218 // parameter attribute.
219 void HandleByVal(unsigned ValNo, MVT::ValueType ValVT,
220 MVT::ValueType LocVT, CCValAssign::LocInfo LocInfo,
219 void HandleByVal(unsigned ValNo, MVT ValVT,
220 MVT LocVT, CCValAssign::LocInfo LocInfo,
221221 int MinSize, int MinAlign, ISD::ArgFlagsTy ArgFlags);
222222
223223 private:
143143
144144 /// getVTList - Return an SDVTList that represents the list of values
145145 /// specified.
146 SDVTList getVTList(MVT::ValueType VT);
147 SDVTList getVTList(MVT::ValueType VT1, MVT::ValueType VT2);
148 SDVTList getVTList(MVT::ValueType VT1, MVT::ValueType VT2,MVT::ValueType VT3);
149 SDVTList getVTList(const MVT::ValueType *VTs, unsigned NumVTs);
146 SDVTList getVTList(MVT VT);
147 SDVTList getVTList(MVT VT1, MVT VT2);
148 SDVTList getVTList(MVT VT1, MVT VT2, MVT VT3);
149 SDVTList getVTList(const MVT *VTs, unsigned NumVTs);
150150
151151 /// getNodeValueTypes - These are obsolete, use getVTList instead.
152 const MVT::ValueType *getNodeValueTypes(MVT::ValueType VT) {
152 const MVT *getNodeValueTypes(MVT VT) {
153153 return getVTList(VT).VTs;
154154 }
155 const MVT::ValueType *getNodeValueTypes(MVT::ValueType VT1,
156 MVT::ValueType VT2) {
155 const MVT *getNodeValueTypes(MVT VT1, MVT VT2) {
157156 return getVTList(VT1, VT2).VTs;
158157 }
159 const MVT::ValueType *getNodeValueTypes(MVT::ValueType VT1,MVT::ValueType VT2,
160 MVT::ValueType VT3) {
158 const MVT *getNodeValueTypes(MVT VT1, MVT VT2, MVT VT3) {
161159 return getVTList(VT1, VT2, VT3).VTs;
162160 }
163 const MVT::ValueType *getNodeValueTypes(std::vector> &vtList) {
161 const MVT *getNodeValueTypes(std::vector> &vtList) {
164162 return getVTList(&vtList[0], (unsigned)vtList.size()).VTs;
165163 }
166164
169167 // Node creation methods.
170168 //
171169 SDOperand getString(const std::string &Val);
172 SDOperand getConstant(uint64_t Val, MVT::ValueType VT, bool isTarget = false);
173 SDOperand getConstant(const APInt &Val, MVT::ValueType VT, bool isTarget = false);
170 SDOperand getConstant(uint64_t Val, MVT VT, bool isTarget = false);
171 SDOperand getConstant(const APInt &Val, MVT VT, bool isTarget = false);
174172 SDOperand getIntPtrConstant(uint64_t Val, bool isTarget = false);
175 SDOperand getTargetConstant(uint64_t Val, MVT::ValueType VT) {
173 SDOperand getTargetConstant(uint64_t Val, MVT VT) {
176174 return getConstant(Val, VT, true);
177175 }
178 SDOperand getTargetConstant(const APInt &Val, MVT::ValueType VT) {
176 SDOperand getTargetConstant(const APInt &Val, MVT VT) {
179177 return getConstant(Val, VT, true);
180178 }
181 SDOperand getConstantFP(double Val, MVT::ValueType VT, bool isTarget = false);
182 SDOperand getConstantFP(const APFloat& Val, MVT::ValueType VT,
183 bool isTarget = false);
184 SDOperand getTargetConstantFP(double Val, MVT::ValueType VT) {
179 SDOperand getConstantFP(double Val, MVT VT, bool isTarget = false);
180 SDOperand getConstantFP(const APFloat& Val, MVT VT, bool isTarget = false);
181 SDOperand getTargetConstantFP(double Val, MVT VT) {
185182 return getConstantFP(Val, VT, true);
186183 }
187 SDOperand getTargetConstantFP(const APFloat& Val, MVT::ValueType VT) {
184 SDOperand getTargetConstantFP(const APFloat& Val, MVT VT) {
188185 return getConstantFP(Val, VT, true);
189186 }
190 SDOperand getGlobalAddress(const GlobalValue *GV, MVT::ValueType VT,
187 SDOperand getGlobalAddress(const GlobalValue *GV, MVT VT,
191188 int offset = 0, bool isTargetGA = false);
192 SDOperand getTargetGlobalAddress(const GlobalValue *GV, MVT::ValueType VT,
189 SDOperand getTargetGlobalAddress(const GlobalValue *GV, MVT VT,
193190 int offset = 0) {
194191 return getGlobalAddress(GV, VT, offset, true);
195192 }
196 SDOperand getFrameIndex(int FI, MVT::ValueType VT, bool isTarget = false);
197 SDOperand getTargetFrameIndex(int FI, MVT::ValueType VT) {
193 SDOperand getFrameIndex(int FI, MVT VT, bool isTarget = false);
194 SDOperand getTargetFrameIndex(int FI, MVT VT) {
198195 return getFrameIndex(FI, VT, true);
199196 }
200 SDOperand getJumpTable(int JTI, MVT::ValueType VT, bool isTarget = false);
201 SDOperand getTargetJumpTable(int JTI, MVT::ValueType VT) {
197 SDOperand getJumpTable(int JTI, MVT VT, bool isTarget = false);
198 SDOperand getTargetJumpTable(int JTI, MVT VT) {
202199 return getJumpTable(JTI, VT, true);
203200 }
204 SDOperand getConstantPool(Constant *C, MVT::ValueType VT,
201 SDOperand getConstantPool(Constant *C, MVT VT,
205202 unsigned Align = 0, int Offs = 0, bool isT=false);
206 SDOperand getTargetConstantPool(Constant *C, MVT::ValueType VT,
203 SDOperand getTargetConstantPool(Constant *C, MVT VT,
207204 unsigned Align = 0, int Offset = 0) {
208205 return getConstantPool(C, VT, Align, Offset, true);
209206 }
210 SDOperand getConstantPool(MachineConstantPoolValue *C, MVT::ValueType VT,
207 SDOperand getConstantPool(MachineConstantPoolValue *C, MVT VT,
211208 unsigned Align = 0, int Offs = 0, bool isT=false);
212209 SDOperand getTargetConstantPool(MachineConstantPoolValue *C,
213 MVT::ValueType VT, unsigned Align = 0,
210 MVT VT, unsigned Align = 0,
214211 int Offset = 0) {
215212 return getConstantPool(C, VT, Align, Offset, true);
216213 }
217214 SDOperand getBasicBlock(MachineBasicBlock *MBB);
218 SDOperand getExternalSymbol(const char *Sym, MVT::ValueType VT);
219 SDOperand getTargetExternalSymbol(const char *Sym, MVT::ValueType VT);
215 SDOperand getExternalSymbol(const char *Sym, MVT VT);
216 SDOperand getTargetExternalSymbol(const char *Sym, MVT VT);
220217 SDOperand getArgFlags(ISD::ArgFlagsTy Flags);
221 SDOperand getValueType(MVT::ValueType);
222 SDOperand getRegister(unsigned Reg, MVT::ValueType VT);
218 SDOperand getValueType(MVT);
219 SDOperand getRegister(unsigned Reg, MVT VT);
223220
224221 SDOperand getCopyToReg(SDOperand Chain, unsigned Reg, SDOperand N) {
225222 return getNode(ISD::CopyToReg, MVT::Other, Chain,
231228 // null) and that there should be a flag result.
232229 SDOperand getCopyToReg(SDOperand Chain, unsigned Reg, SDOperand N,
233230 SDOperand Flag) {
234 const MVT::ValueType *VTs = getNodeValueTypes(MVT::Other, MVT::Flag);
231 const MVT *VTs = getNodeValueTypes(MVT::Other, MVT::Flag);
235232 SDOperand Ops[] = { Chain, getRegister(Reg, N.getValueType()), N, Flag };
236233 return getNode(ISD::CopyToReg, VTs, 2, Ops, Flag.Val ? 4 : 3);
237234 }
239236 // Similar to last getCopyToReg() except parameter Reg is a SDOperand
240237 SDOperand getCopyToReg(SDOperand Chain, SDOperand Reg, SDOperand N,
241238 SDOperand Flag) {
242 const MVT::ValueType *VTs = getNodeValueTypes(MVT::Other, MVT::Flag);
239 const MVT *VTs = getNodeValueTypes(MVT::Other, MVT::Flag);
243240 SDOperand Ops[] = { Chain, Reg, N, Flag };
244241 return getNode(ISD::CopyToReg, VTs, 2, Ops, Flag.Val ? 4 : 3);
245242 }
246243
247 SDOperand getCopyFromReg(SDOperand Chain, unsigned Reg, MVT::ValueType VT) {
248 const MVT::ValueType *VTs = getNodeValueTypes(VT, MVT::Other);
244 SDOperand getCopyFromReg(SDOperand Chain, unsigned Reg, MVT VT) {
245 const MVT *VTs = getNodeValueTypes(VT, MVT::Other);
249246 SDOperand Ops[] = { Chain, getRegister(Reg, VT) };
250247 return getNode(ISD::CopyFromReg, VTs, 2, Ops, 2);
251248 }
253250 // This version of the getCopyFromReg method takes an extra operand, which
254251 // indicates that there is potentially an incoming flag value (if Flag is not
255252 // null) and that there should be a flag result.
256 SDOperand getCopyFromReg(SDOperand Chain, unsigned Reg, MVT::ValueType VT,
253 SDOperand getCopyFromReg(SDOperand Chain, unsigned Reg, MVT VT,
257254 SDOperand Flag) {
258 const MVT::ValueType *VTs = getNodeValueTypes(VT, MVT::Other, MVT::Flag);
255 const MVT *VTs = getNodeValueTypes(VT, MVT::Other, MVT::Flag);
259256 SDOperand Ops[] = { Chain, getRegister(Reg, VT), Flag };
260257 return getNode(ISD::CopyFromReg, VTs, 3, Ops, Flag.Val ? 3 : 2);
261258 }
264261
265262 /// getZeroExtendInReg - Return the expression required to zero extend the Op
266263 /// value assuming it was the smaller SrcTy value.
267 SDOperand getZeroExtendInReg(SDOperand Op, MVT::ValueType SrcTy);
264 SDOperand getZeroExtendInReg(SDOperand Op, MVT SrcTy);
268265
269266 /// getCALLSEQ_START - Return a new CALLSEQ_START node, which always must have
270267 /// a flag result (to ensure it's not CSE'd).
271268 SDOperand getCALLSEQ_START(SDOperand Chain, SDOperand Op) {
272 const MVT::ValueType *VTs = getNodeValueTypes(MVT::Other, MVT::Flag);
269 const MVT *VTs = getNodeValueTypes(MVT::Other, MVT::Flag);
273270 SDOperand Ops[] = { Chain, Op };
274271 return getNode(ISD::CALLSEQ_START, VTs, 2, Ops, 2);
275272 }
290287
291288 /// getNode - Gets or creates the specified node.
292289 ///
293 SDOperand getNode(unsigned Opcode, MVT::ValueType VT);
294 SDOperand getNode(unsigned Opcode, MVT::ValueType VT, SDOperand N);
295 SDOperand getNode(unsigned Opcode, MVT::ValueType VT,
296 SDOperand N1, SDOperand N2);
297 SDOperand getNode(unsigned Opcode, MVT::ValueType VT,
290 SDOperand getNode(unsigned Opcode, MVT VT);
291 SDOperand getNode(unsigned Opcode, MVT VT, SDOperand N);
292 SDOperand getNode(unsigned Opcode, MVT VT, SDOperand N1, SDOperand N2);
293 SDOperand getNode(unsigned Opcode, MVT VT,
298294 SDOperand N1, SDOperand N2, SDOperand N3);
299 SDOperand getNode(unsigned Opcode, MVT::ValueType VT,
295 SDOperand getNode(unsigned Opcode, MVT VT,
300296 SDOperand N1, SDOperand N2, SDOperand N3, SDOperand N4);
301 SDOperand getNode(unsigned Opcode, MVT::ValueType VT,
297 SDOperand getNode(unsigned Opcode, MVT VT,
302298 SDOperand N1, SDOperand N2, SDOperand N3, SDOperand N4,
303299 SDOperand N5);
304 SDOperand getNode(unsigned Opcode, MVT::ValueType VT,
300 SDOperand getNode(unsigned Opcode, MVT VT, SDOperandPtr Ops, unsigned NumOps);
301 SDOperand getNode(unsigned Opcode, std::vector &ResultTys,
305302 SDOperandPtr Ops, unsigned NumOps);
306 SDOperand getNode(unsigned Opcode, std::vector &ResultTys,
307 SDOperandPtr Ops, unsigned NumOps);
308 SDOperand getNode(unsigned Opcode, const MVT::ValueType *VTs, unsigned NumVTs,
303 SDOperand getNode(unsigned Opcode, const MVT *VTs, unsigned NumVTs,
309304 SDOperandPtr Ops, unsigned NumOps);
310305 SDOperand getNode(unsigned Opcode, SDVTList VTs);
311306 SDOperand getNode(unsigned Opcode, SDVTList VTs, SDOperand N);
312 SDOperand getNode(unsigned Opcode, SDVTList VTs,
313 SDOperand N1, SDOperand N2);
307 SDOperand getNode(unsigned Opcode, SDVTList VTs, SDOperand N1, SDOperand N2);
314308 SDOperand getNode(unsigned Opcode, SDVTList VTs,
315309 SDOperand N1, SDOperand N2, SDOperand N3);
316310 SDOperand getNode(unsigned Opcode, SDVTList VTs,
339333 /// getSetCC - Helper function to make it easier to build SetCC's if you just
340334 /// have an ISD::CondCode instead of an SDOperand.
341335 ///
342 SDOperand getSetCC(MVT::ValueType VT, SDOperand LHS, SDOperand RHS,
336 SDOperand getSetCC(MVT VT, SDOperand LHS, SDOperand RHS,
343337 ISD::CondCode Cond) {
344338 return getNode(ISD::SETCC, VT, LHS, RHS, getCondCode(Cond));
345339 }
347341 /// getVSetCC - Helper function to make it easier to build VSetCC's nodes
348342 /// if you just have an ISD::CondCode instead of an SDOperand.
349343 ///
350 SDOperand getVSetCC(MVT::ValueType VT, SDOperand LHS, SDOperand RHS,
344 SDOperand getVSetCC(MVT VT, SDOperand LHS, SDOperand RHS,
351345 ISD::CondCode Cond) {
352346 return getNode(ISD::VSETCC, VT, LHS, RHS, getCondCode(Cond));
353347 }
363357
364358 /// getVAArg - VAArg produces a result and token chain, and takes a pointer
365359 /// and a source value as input.
366 SDOperand getVAArg(MVT::ValueType VT, SDOperand Chain, SDOperand Ptr,
360 SDOperand getVAArg(MVT VT, SDOperand Chain, SDOperand Ptr,
367361 SDOperand SV);
368362
369363 /// getAtomic - Gets a node for an atomic op, produces result and chain, takes
370364 // 3 operands
371365 SDOperand getAtomic(unsigned Opcode, SDOperand Chain, SDOperand Ptr,
372 SDOperand Cmp, SDOperand Swp, MVT::ValueType VT);
366 SDOperand Cmp, SDOperand Swp, MVT VT);
373367
374368 /// getAtomic - Gets a node for an atomic op, produces result and chain, takes
375369 // 2 operands
376370 SDOperand getAtomic(unsigned Opcode, SDOperand Chain, SDOperand Ptr,
377 SDOperand Val, MVT::ValueType VT);
371 SDOperand Val, MVT VT);
378372
379373 /// getLoad - Loads are not normal binary operators: their result type is not
380374 /// determined by their operands, and they produce a value AND a token chain.
381375 ///
382 SDOperand getLoad(MVT::ValueType VT, SDOperand Chain, SDOperand Ptr,
376 SDOperand getLoad(MVT VT, SDOperand Chain, SDOperand Ptr,
383377 const Value *SV, int SVOffset, bool isVolatile=false,
384378 unsigned Alignment=0);
385 SDOperand getExtLoad(ISD::LoadExtType ExtType, MVT::ValueType VT,
379 SDOperand getExtLoad(ISD::LoadExtType ExtType, MVT VT,
386380 SDOperand Chain, SDOperand Ptr, const Value *SV,
387 int SVOffset, MVT::ValueType EVT, bool isVolatile=false,
381 int SVOffset, MVT EVT, bool isVolatile=false,
388382 unsigned Alignment=0);
389383 SDOperand getIndexedLoad(SDOperand OrigLoad, SDOperand Base,
390384 SDOperand Offset, ISD::MemIndexedMode AM);
391385 SDOperand getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType,
392 MVT::ValueType VT, SDOperand Chain,
386 MVT VT, SDOperand Chain,
393387 SDOperand Ptr, SDOperand Offset,
394 const Value *SV, int SVOffset, MVT::ValueType EVT,
388 const Value *SV, int SVOffset, MVT EVT,
395389 bool isVolatile=false, unsigned Alignment=0);
396390
397391 /// getStore - Helper function to build ISD::STORE nodes.
400394 const Value *SV, int SVOffset, bool isVolatile=false,
401395 unsigned Alignment=0);
402396 SDOperand getTruncStore(SDOperand Chain, SDOperand Val, SDOperand Ptr,
403 const Value *SV, int SVOffset, MVT::ValueType TVT,
397 const Value *SV, int SVOffset, MVT TVT,
404398 bool isVolatile=false, unsigned Alignment=0);
405399 SDOperand getIndexedStore(SDOperand OrigStoe, SDOperand Base,
406400 SDOperand Offset, ISD::MemIndexedMode AM);
433427 /// operands. Note that target opcodes are stored as
434428 /// ISD::BUILTIN_OP_END+TargetOpcode in the node opcode field. The 0th value
435429 /// of the resultant node is returned.
436 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT::ValueType VT);
437 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT::ValueType VT,
438 SDOperand Op1);
439 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT::ValueType VT,
430 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT);
431 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT, SDOperand Op1);
432 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT,
440433 SDOperand Op1, SDOperand Op2);
441 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT::ValueType VT,
434 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT,
442435 SDOperand Op1, SDOperand Op2, SDOperand Op3);
443 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT::ValueType VT,
436 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT,
444437 SDOperandPtr Ops, unsigned NumOps);
445 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT::ValueType VT1,
446 MVT::ValueType VT2, SDOperand Op1, SDOperand Op2);
447 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT::ValueType VT1,
448 MVT::ValueType VT2, SDOperand Op1, SDOperand Op2,
449 SDOperand Op3);
438 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT1,
439 MVT VT2, SDOperand Op1, SDOperand Op2);
440 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, MVT VT1,
441 MVT VT2, SDOperand Op1, SDOperand Op2, SDOperand Op3);
450442
451443
452444 /// getTargetNode - These are used for target selectors to create a new node
455447 /// Note that getTargetNode returns the resultant node. If there is already a
456448 /// node of the specified opcode and operands, it returns that node instead of
457449 /// the current one.
458 SDNode *getTargetNode(unsigned Opcode, MVT::ValueType VT);
459 SDNode *getTargetNode(unsigned Opcode, MVT::ValueType VT,
460 SDOperand Op1);
461 SDNode *getTargetNode(unsigned Opcode, MVT::ValueType VT,
450 SDNode *getTargetNode(unsigned Opcode, MVT VT);
451 SDNode *getTargetNode(unsigned Opcode, MVT VT, SDOperand Op1);
452 SDNode *getTargetNode(unsigned Opcode, MVT VT, SDOperand Op1, SDOperand Op2);
453 SDNode *getTargetNode(unsigned Opcode, MVT VT,
454 SDOperand Op1, SDOperand Op2, SDOperand Op3);
455 SDNode *getTargetNode(unsigned Opcode, MVT VT,
456 SDOperandPtr Ops, unsigned NumOps);
457 SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2);
458 SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, SDOperand Op1);
459 SDNode *getTargetNode(unsigned Opcode, MVT VT1,
460 MVT VT2, SDOperand Op1, SDOperand Op2);
461 SDNode *getTargetNode(unsigned Opcode, MVT VT1,
462 MVT VT2, SDOperand Op1, SDOperand Op2, SDOperand Op3);
463 SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2,
464 SDOperandPtr Ops, unsigned NumOps);
465 SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
462466 SDOperand Op1, SDOperand Op2);
463 SDNode *getTargetNode(unsigned Opcode, MVT::ValueType VT,
467 SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
464468 SDOperand Op1, SDOperand Op2, SDOperand Op3);
465 SDNode *getTargetNode(unsigned Opcode, MVT::ValueType VT,
469 SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3,
466470 SDOperandPtr Ops, unsigned NumOps);
467 SDNode *getTargetNode(unsigned Opcode, MVT::ValueType VT1,
468 MVT::ValueType VT2);
469 SDNode *getTargetNode(unsigned Opcode, MVT::ValueType VT1,
470 MVT::ValueType VT2, SDOperand Op1);
471 SDNode *getTargetNode(unsigned Opcode, MVT::ValueType VT1,
472 MVT::ValueType VT2, SDOperand Op1, SDOperand Op2);
473 SDNode *getTargetNode(unsigned Opcode, MVT::ValueType VT1,
474 MVT::ValueType VT2, SDOperand Op1, SDOperand Op2,
475 SDOperand Op3);
476 SDNode *getTargetNode(unsigned Opcode, MVT::ValueType VT1,
477 MVT::ValueType VT2,
471 SDNode *getTargetNode(unsigned Opcode, MVT VT1, MVT VT2, MVT VT3, MVT VT4,
478472 SDOperandPtr Ops, unsigned NumOps);
479 SDNode *getTargetNode(unsigned Opcode, MVT::ValueType VT1,
480 MVT::ValueType VT2, MVT::ValueType VT3,
481 SDOperand Op1, SDOperand Op2);
482 SDNode *getTargetNode(unsigned Opcode, MVT::ValueType VT1,
483 MVT::ValueType VT2, MVT::ValueType VT3,
484 SDOperand Op1, SDOperand Op2, SDOperand Op3);
485 SDNode *getTargetNode(unsigned Opcode, MVT::ValueType VT1,
486 MVT::ValueType VT2, MVT::ValueType VT3,
487 SDOperandPtr Ops, unsigned NumOps);
488 SDNode *getTargetNode(unsigned Opcode, MVT::ValueType VT1,
489 MVT::ValueType VT2, MVT::ValueType VT3,
490 MVT::ValueType VT4,
491 SDOperandPtr Ops, unsigned NumOps);
492 SDNode *getTargetNode(unsigned Opcode, std::vector::ValueType> &ResultTys,
473 SDNode *getTargetNode(unsigned Opcode, std::vector> &ResultTys,
493474 SDOperandPtr Ops, unsigned NumOps);
494475
495476 /// getNodeIfExists - Get the specified node if it's already available, or
569550
570551 /// CreateStackTemporary - Create a stack temporary, suitable for holding the
571552 /// specified value type.
572 SDOperand CreateStackTemporary(MVT::ValueType VT);
553 SDOperand CreateStackTemporary(MVT VT);
573554
574555 /// FoldSetCC - Constant fold a setcc to true or false.
575 SDOperand FoldSetCC(MVT::ValueType VT, SDOperand N1,
556 SDOperand FoldSetCC(MVT VT, SDOperand N1,
576557 SDOperand N2, ISD::CondCode Cond);
577558
578559 /// SignBitIsZero - Return true if the sign bit of Op is known to be zero. We
622603 void DeleteNodeNotInCSEMaps(SDNode *N);
623604
624605 // List of non-single value types.
625 std::list::ValueType> > VTList;
606 std::list> > VTList;
626607
627608 // Maps to auto-CSE operations.
628609 std::vector CondCodeNodes;
629610
630611 std::vector ValueTypeNodes;
631 std::map::ValueType, SDNode*> ExtendedValueTypeNodes;
612 std::map, SDNode*> ExtendedValueTypeNodes;
632613 std::map ExternalSymbols;
633614 std::map TargetExternalSymbols;
634615 std::map StringNodes;
5454
5555 virtual bool runOnFunction(Function &Fn);
5656
57 unsigned MakeReg(MVT::ValueType VT);
57 unsigned MakeReg(MVT VT);
5858
5959 virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {}
6060 virtual void InstructionSelectBasicBlock(SelectionDAG &SD) = 0;
4747 /// SelectionDAG::getVTList(...).
4848 ///
4949 struct SDVTList {
50 const MVT::ValueType *VTs;
50 const MVT *VTs;
5151 unsigned short NumVTs;
5252 };
5353
833833
834834 /// getValueType - Return the ValueType of the referenced return value.
835835 ///
836 inline MVT::ValueType getValueType() const;
837
838 /// getValueSizeInBits - Returns MVT::getSizeInBits(getValueType()).
836 inline MVT getValueType() const;
837
838 /// getValueSizeInBits - Returns the size of the value in bits.
839839 ///
840840 unsigned getValueSizeInBits() const {
841 return MVT::getSizeInBits(getValueType());
841 return getValueType().getSizeInBits();
842842 }
843843
844844 // Forwarding methods - These forward to the corresponding methods in SDNode.
10441044
10451045 /// ValueList - The types of the values this node defines. SDNode's may
10461046 /// define multiple values simultaneously.
1047 const MVT::ValueType *ValueList;
1047 const MVT *ValueList;
10481048
10491049 /// NumOperands/NumValues - The number of entries in the Operand/Value list.
10501050 unsigned short NumOperands, NumValues;
12151215
12161216 /// getValueType - Return the type of a specified result.
12171217 ///
1218 MVT::ValueType getValueType(unsigned ResNo) const {
1218 MVT getValueType(unsigned ResNo) const {
12191219 assert(ResNo < NumValues && "Illegal result number!");
12201220 return ValueList[ResNo];
12211221 }
12231223 /// getValueSizeInBits - Returns MVT::getSizeInBits(getValueType(ResNo)).
12241224 ///
12251225 unsigned getValueSizeInBits(unsigned ResNo) const {
1226 return MVT::getSizeInBits(getValueType(ResNo));
1227 }
1228
1229 typedef const MVT::ValueType* value_iterator;
1226 return getValueType(ResNo).getSizeInBits();
1227 }
1228
1229 typedef const MVT* value_iterator;
12301230 value_iterator value_begin() const { return ValueList; }
12311231 value_iterator value_end() const { return ValueList+NumValues; }
12321232
12481248
12491249 /// getValueTypeList - Return a pointer to the specified value type.
12501250 ///
1251 static const MVT::ValueType *getValueTypeList(MVT::ValueType VT);
1252 static SDVTList getSDVTList(MVT::ValueType VT) {
1251 static const MVT *getValueTypeList(MVT VT);
1252 static SDVTList getSDVTList(MVT VT) {
12531253 SDVTList Ret = { getValueTypeList(VT), 1 };
12541254 return Ret;
12551255 }
13431343 inline unsigned SDOperand::getOpcode() const {
13441344 return Val->getOpcode();
13451345 }
1346 inline MVT::ValueType SDOperand::getValueType() const {
1346 inline MVT SDOperand::getValueType() const {
13471347 return Val->getValueType(ResNo);
13481348 }
13491349 inline unsigned SDOperand::getNumOperands() const {
14381438 class AtomicSDNode : public SDNode {
14391439 virtual void ANCHOR(); // Out-of-line virtual method to give class a home.
14401440 SDUse Ops[4];
1441 MVT::ValueType OrigVT;
1441 MVT OrigVT;
14421442 public:
14431443 AtomicSDNode(unsigned Opc, SDVTList VTL, SDOperand Chain, SDOperand Ptr,
1444 SDOperand Cmp, SDOperand Swp, MVT::ValueType VT)
1444 SDOperand Cmp, SDOperand Swp, MVT VT)
14451445 : SDNode(Opc, VTL) {
14461446 Ops[0] = Chain;
14471447 Ops[1] = Ptr;
14511451 OrigVT=VT;
14521452 }
14531453 AtomicSDNode(unsigned Opc, SDVTList VTL, SDOperand Chain, SDOperand Ptr,
1454 SDOperand Val, MVT::ValueType VT)
1454 SDOperand Val, MVT VT)
14551455 : SDNode(Opc, VTL) {
14561456 Ops[0] = Chain;
14571457 Ops[1] = Ptr;
14591459 InitOperands(Ops, 3);
14601460 OrigVT=VT;
14611461 }
1462 MVT::ValueType getVT() const { return OrigVT; }
1462 MVT getVT() const { return OrigVT; }
14631463 bool isCompareAndSwap() const { return getOpcode() == ISD::ATOMIC_LCS; }
14641464 };
14651465
14841484 virtual void ANCHOR(); // Out-of-line virtual method to give class a home.
14851485 protected:
14861486 friend class SelectionDAG;
1487 ConstantSDNode(bool isTarget, const APInt &val, MVT::ValueType VT)
1487 ConstantSDNode(bool isTarget, const APInt &val, MVT VT)
14881488 : SDNode(isTarget ? ISD::TargetConstant : ISD::Constant, getSDVTList(VT)),
14891489 Value(val) {
14901490 }
14941494 uint64_t getValue() const { return Value.getZExtValue(); }
14951495
14961496 int64_t getSignExtended() const {
1497 unsigned Bits = MVT::getSizeInBits(getValueType(0));
1497 unsigned Bits = getValueType(0).getSizeInBits();
14981498 return ((int64_t)Value.getZExtValue() << (64-Bits)) >> (64-Bits);
14991499 }
15001500
15011501 bool isNullValue() const { return Value == 0; }
15021502 bool isAllOnesValue() const {
1503 return Value == MVT::getIntVTBitMask(getValueType(0));
1503 return Value == getValueType(0).getIntegerVTBitMask();
15041504 }
15051505
15061506 static bool classof(const ConstantSDNode *) { return true; }
15151515 virtual void ANCHOR(); // Out-of-line virtual method to give class a home.
15161516 protected:
15171517 friend class SelectionDAG;
1518 ConstantFPSDNode(bool isTarget, const APFloat& val, MVT::ValueType VT)
1518 ConstantFPSDNode(bool isTarget, const APFloat& val, MVT VT)
15191519 : SDNode(isTarget ? ISD::TargetConstantFP : ISD::ConstantFP,
15201520 getSDVTList(VT)), Value(val) {
15211521 }
15411541 }
15421542 bool isExactlyValue(const APFloat& V) const;
15431543
1544 bool isValueValidForType(MVT::ValueType VT, const APFloat& Val);
1544 bool isValueValidForType(MVT VT, const APFloat& Val);
15451545
15461546 static bool classof(const ConstantFPSDNode *) { return true; }
15471547 static bool classof(const SDNode *N) {
15561556 virtual void ANCHOR(); // Out-of-line virtual method to give class a home.
15571557 protected:
15581558 friend class SelectionDAG;
1559 GlobalAddressSDNode(bool isTarget, const GlobalValue *GA, MVT::ValueType VT,
1560 int o = 0);
1559 GlobalAddressSDNode(bool isTarget, const GlobalValue *GA, MVT VT, int o = 0);
15611560 public:
15621561
15631562 GlobalValue *getGlobal() const { return TheGlobal; }
15771576 virtual void ANCHOR(); // Out-of-line virtual method to give class a home.
15781577 protected:
15791578 friend class SelectionDAG;
1580 FrameIndexSDNode(int fi, MVT::ValueType VT, bool isTarg)
1579 FrameIndexSDNode(int fi, MVT VT, bool isTarg)
15811580 : SDNode(isTarg ? ISD::TargetFrameIndex : ISD::FrameIndex, getSDVTList(VT)),
15821581 FI(fi) {
15831582 }
15971596 virtual void ANCHOR(); // Out-of-line virtual method to give class a home.
15981597 protected:
15991598 friend class SelectionDAG;
1600 JumpTableSDNode(int jti, MVT::ValueType VT, bool isTarg)
1599 JumpTableSDNode(int jti, MVT VT, bool isTarg)
16011600 : SDNode(isTarg ? ISD::TargetJumpTable : ISD::JumpTable, getSDVTList(VT)),
16021601 JTI(jti) {
16031602 }
16221621 virtual void ANCHOR(); // Out-of-line virtual method to give class a home.
16231622 protected:
16241623 friend class SelectionDAG;
1625 ConstantPoolSDNode(bool isTarget, Constant *c, MVT::ValueType VT,
1626 int o=0)
1624 ConstantPoolSDNode(bool isTarget, Constant *c, MVT VT, int o=0)
16271625 : SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool,
16281626 getSDVTList(VT)), Offset(o), Alignment(0) {
16291627 assert((int)Offset >= 0 && "Offset is too large");
16301628 Val.ConstVal = c;
16311629 }
1632 ConstantPoolSDNode(bool isTarget, Constant *c, MVT::ValueType VT, int o,
1633 unsigned Align)
1630 ConstantPoolSDNode(bool isTarget, Constant *c, MVT VT, int o, unsigned Align)
16341631 : SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool,
16351632 getSDVTList(VT)), Offset(o), Alignment(Align) {
16361633 assert((int)Offset >= 0 && "Offset is too large");
16371634 Val.ConstVal = c;
16381635 }
16391636 ConstantPoolSDNode(bool isTarget, MachineConstantPoolValue *v,
1640 MVT::ValueType VT, int o=0)
1637 MVT VT, int o=0)
16411638 : SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool,
16421639 getSDVTList(VT)), Offset(o), Alignment(0) {
16431640 assert((int)Offset >= 0 && "Offset is too large");
16451642 Offset |= 1 << (sizeof(unsigned)*8-1);
16461643 }
16471644 ConstantPoolSDNode(bool isTarget, MachineConstantPoolValue *v,
1648 MVT::ValueType VT, int o, unsigned Align)
1645 MVT VT, int o, unsigned Align)
16491646 : SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool,
16501647 getSDVTList(VT)), Offset(o), Alignment(Align) {
16511648 assert((int)Offset >= 0 && "Offset is too large");
17591756 virtual void ANCHOR(); // Out-of-line virtual method to give class a home.
17601757 protected:
17611758 friend class SelectionDAG;
1762 RegisterSDNode(unsigned reg, MVT::ValueType VT)
1759 RegisterSDNode(unsigned reg, MVT VT)
17631760 : SDNode(ISD::Register, getSDVTList(VT)), Reg(reg) {
17641761 }
17651762 public:
17771774 virtual void ANCHOR(); // Out-of-line virtual method to give class a home.
17781775 protected:
17791776 friend class SelectionDAG;
1780 ExternalSymbolSDNode(bool isTarget, const char *Sym, MVT::ValueType VT)
1777 ExternalSymbolSDNode(bool isTarget, const char *Sym, MVT VT)
17811778 : SDNode(isTarget ? ISD::TargetExternalSymbol : ISD::ExternalSymbol,
17821779 getSDVTList(VT)), Symbol(Sym) {
17831780 }
19131910 }
19141911 };
19151912
1916 /// VTSDNode - This class is used to represent MVT::ValueType's, which are used
1913 /// VTSDNode - This class is used to represent MVT's, which are used
19171914 /// to parameterize some operations.
19181915 class VTSDNode : public SDNode {
1919 MVT::ValueType ValueType;
1916 MVT ValueType;
19201917 virtual void ANCHOR(); // Out-of-line virtual method to give class a home.
19211918 protected:
19221919 friend class SelectionDAG;
1923 explicit VTSDNode(MVT::ValueType VT)
1920 explicit VTSDNode(MVT VT)
19241921 : SDNode(ISD::VALUETYPE, getSDVTList(MVT::Other)), ValueType(VT) {
19251922 }
19261923 public:
19271924
1928 MVT::ValueType getVT() const { return ValueType; }
1925 MVT getVT() const { return ValueType; }
19291926
19301927 static bool classof(const VTSDNode *) { return true; }
19311928 static bool classof(const SDNode *N) {
19411938 ISD::MemIndexedMode AddrMode;
19421939
19431940 // MemoryVT - VT of in-memory value.
1944 MVT::ValueType MemoryVT;
1941 MVT MemoryVT;
19451942
19461943 //! SrcValue - Memory location for alias analysis.
19471944 const Value *SrcValue;
19641961 SDUse Ops[4];
19651962 public:
19661963 LSBaseSDNode(ISD::NodeType NodeTy, SDOperand *Operands, unsigned numOperands,
1967 SDVTList VTs, ISD::MemIndexedMode AM, MVT::ValueType VT,
1964 SDVTList VTs, ISD::MemIndexedMode AM, MVT VT,
19681965 const Value *SV, int SVO, unsigned Align, bool Vol)
19691966 : SDNode(NodeTy, VTs),
19701967 AddrMode(AM), MemoryVT(VT),
19881985 const Value *getSrcValue() const { return SrcValue; }
19891986 int getSrcValueOffset() const { return SVOffset; }
19901987 unsigned getAlignment() const { return Alignment; }
1991 MVT::ValueType getMemoryVT() const { return MemoryVT; }
1988 MVT getMemoryVT() const { return MemoryVT; }
19921989 bool isVolatile() const { return IsVolatile; }
19931990
19941991 ISD::MemIndexedMode getAddressingMode() const { return AddrMode; }
20212018 protected:
20222019 friend class SelectionDAG;
20232020 LoadSDNode(SDOperand *ChainPtrOff, SDVTList VTs,
2024 ISD::MemIndexedMode AM, ISD::LoadExtType ETy, MVT::ValueType LVT,
2021 ISD::MemIndexedMode AM, ISD::LoadExtType ETy, MVT LVT,
20252022 const Value *SV, int O=0, unsigned Align=0, bool Vol=false)
20262023 : LSBaseSDNode(ISD::LOAD, ChainPtrOff, 3,
20272024 VTs, AM, LVT, SV, O, Align, Vol),
20482045 protected:
20492046 friend class SelectionDAG;
20502047 StoreSDNode(SDOperand *ChainValuePtrOff, SDVTList VTs,
2051 ISD::MemIndexedMode AM, bool isTrunc, MVT::ValueType SVT,
2048 ISD::MemIndexedMode AM, bool isTrunc, MVT SVT,
20522049 const Value *SV, int O=0, unsigned Align=0, bool Vol=false)
20532050 : LSBaseSDNode(ISD::STORE, ChainValuePtrOff, 4,
20542051 VTs, AM, SVT, SV, O, Align, Vol),
2323 namespace llvm {
2424 class Type;
2525
26 /// MVT namespace - This namespace defines the SimpleValueType enum, which
27 /// contains the various low-level value types, and the ValueType typedef.
28 ///
29 namespace MVT { // MVT = Machine Value Types
30 enum SimpleValueType {
31 // If you change this numbering, you must change the values in ValueTypes.td
32 // well!
33 Other = 0, // This is a non-standard value
34 i1 = 1, // This is a 1 bit integer value
35 i8 = 2, // This is an 8 bit integer value
36 i16 = 3, // This is a 16 bit integer value
37 i32 = 4, // This is a 32 bit integer value
38 i64 = 5, // This is a 64 bit integer value
39 i128 = 6, // This is a 128 bit integer value
40
41 FIRST_INTEGER_VALUETYPE = i1,
42 LAST_INTEGER_VALUETYPE = i128,
43
44 f32 = 7, // This is a 32 bit floating point value
45 f64 = 8, // This is a 64 bit floating point value
46 f80 = 9, // This is a 80 bit floating point value
47 f128 = 10, // This is a 128 bit floating point value
48 ppcf128 = 11, // This is a PPC 128-bit floating point value
49 Flag = 12, // This is a condition code or machine flag.
50
51 isVoid = 13, // This has no value
52
53 v8i8 = 14, // 8 x i8
54 v4i16 = 15, // 4 x i16
55 v2i32 = 16, // 2 x i32
56 v1i64 = 17, // 1 x i64
57 v16i8 = 18, // 16 x i8
58 v8i16 = 19, // 8 x i16
59 v3i32 = 20, // 3 x i32
60 v4i32 = 21, // 4 x i32
61 v2i64 = 22, // 2 x i64
62
63 v2f32 = 23, // 2 x f32
64 v3f32 = 24, // 3 x f32
65 v4f32 = 25, // 4 x f32
66 v2f64 = 26, // 2 x f64
67
68 FIRST_VECTOR_VALUETYPE = v8i8,
69 LAST_VECTOR_VALUETYPE = v2f64,
70
71 LAST_VALUETYPE = 27, // This always remains at the end of the list.
72
73 // fAny - Any floating-point or vector floating-point value. This is used
74 // for intrinsics that have overloadings based on floating-point types.
75 // This is only for tblgen's consumption!
76 fAny = 253,
77
78 // iAny - An integer or vector integer value of any bit width. This is
79 // used for intrinsics that have overloadings based on integer bit widths.
80 // This is only for tblgen's consumption!
81 iAny = 254,
82
83 // iPTR - An int value the size of the pointer of the current
84 // target. This should only be used internal to tblgen!
85 iPTR = 255
26 struct MVT { // MVT = Machine Value Type
27
28 enum SimpleValueType {
29 // If you change this numbering, you must change the values in
30 // ValueTypes.td well!
31 Other = 0, // This is a non-standard value
32 i1 = 1, // This is a 1 bit integer value
33 i8 = 2, // This is an 8 bit integer value
34 i16 = 3, // This is a 16 bit integer value
35 i32 = 4, // This is a 32 bit integer value
36 i64 = 5, // This is a 64 bit integer value
37 i128 = 6, // This is a 128 bit integer value
38
39 FIRST_INTEGER_VALUETYPE = i1,
40 LAST_INTEGER_VALUETYPE = i128,
41
42 f32 = 7, // This is a 32 bit floating point value
43 f64 = 8, // This is a 64 bit floating point value
44 f80 = 9, // This is a 80 bit floating point value
45 f128 = 10, // This is a 128 bit floating point value
46 ppcf128 = 11, // This is a PPC 128-bit floating point value
47 Flag = 12, // This is a condition code or machine flag.
48
49 isVoid = 13, // This has no value
50
51 v8i8 = 14, // 8 x i8
52 v4i16 = 15, // 4 x i16
53 v2i32 = 16, // 2 x i32
54 v1i64 = 17, // 1 x i64
55 v16i8 = 18, // 16 x i8
56 v8i16 = 19, // 8 x i16
57 v3i32 = 20, // 3 x i32
58 v4i32 = 21, // 4 x i32
59 v2i64 = 22, // 2 x i64
60
61 v2f32 = 23, // 2 x f32
62 v3f32 = 24, // 3 x f32
63 v4f32 = 25, // 4 x f32
64 v2f64 = 26, // 2 x f64
65
66 FIRST_VECTOR_VALUETYPE = v8i8,
67 LAST_VECTOR_VALUETYPE = v2f64,
68
69 LAST_VALUETYPE = 27, // This always remains at the end of the list.
70
71 // fAny - Any floating-point or vector floating-point value. This is used
72 // for intrinsics that have overloadings based on floating-point types.
73 // This is only for tblgen's consumption!
74 fAny = 253,
75
76 // iAny - An integer or vector integer value of any bit width. This is
77 // used for intrinsics that have overloadings based on integer bit widths.
78 // This is only for tblgen's consumption!
79 iAny = 254,
80
81 // iPTR - An int value the size of the pointer of the current
82 // target. This should only be used internal to tblgen!
83 iPTR = 255
84 };
85
86 /// MVT - This type holds low-level value types. Valid values include any of
87 /// the values in the SimpleValueType enum, or any value returned from one
88 /// of the MVT methods. Any value type equal to one of the SimpleValueType
89 /// enum values is a "simple" value type. All others are "extended".
90 ///
91 /// Note that simple doesn't necessary mean legal for the target machine.
92 /// All legal value types must be simple, but often there are some simple
93 /// value types that are not legal.
94 ///
95 /// @internal
96 /// Extended types are either vector types or arbitrary precision integers.
97 /// Arbitrary precision integers have iAny in the first SimpleTypeBits bits,
98 /// and the bit-width in the next PrecisionBits bits, offset by minus one.
99 /// Vector types are encoded by having the first SimpleTypeBits+PrecisionBits
100 /// bits encode the vector element type (which must be a scalar type, possibly
101 /// an arbitrary precision integer) and the remaining VectorBits upper bits
102 /// encode the vector length, offset by one.
103 ///
104 /// 31--------------16-----------8-------------0
105 /// | Vector length | Precision | Simple type |
106 /// | | Vector element |
107 ///
108
109 static const int SimpleTypeBits = 8;
110 static const int PrecisionBits = 8;
111 static const int VectorBits = 32 - SimpleTypeBits - PrecisionBits;
112
113 static const uint32_t SimpleTypeMask =
114 (~uint32_t(0) << (32 - SimpleTypeBits)) >> (32 - SimpleTypeBits);
115
116 static const uint32_t PrecisionMask =
117 ((~uint32_t(0) << VectorBits) >> (32 - PrecisionBits)) << SimpleTypeBits;
118
119 static const uint32_t VectorMask =
120 (~uint32_t(0) >> (32 - VectorBits)) << (32 - VectorBits);
121
122 static const uint32_t ElementMask =
123 (~uint32_t(0) << VectorBits) >> VectorBits;
124
125 uint32_t V;
126
127 MVT() {}
128 MVT(SimpleValueType S) { V = S; }
129 inline bool operator== (const MVT VT) const { return V == VT.V; }
130 inline bool operator!= (const MVT VT) const { return V != VT.V; }
131
132 /// FIXME: The following comparison methods are bogus - they are only here
133 /// to ease the transition to a struct type.
134 inline bool operator< (const MVT VT) const { return V < VT.V; }
135 inline bool operator<= (const MVT VT) const { return V <= VT.V; }
136 inline bool operator> (const MVT VT) const { return V > VT.V; }
137 inline bool operator>= (const MVT VT) const { return V >= VT.V; }
138
139 /// getIntegerVT - Returns the MVT that represents an integer with the given
140 /// number of bits.
141 static inline MVT getIntegerVT(unsigned BitWidth) {
142 switch (BitWidth) {
143 default:
144 break;
145 case 1:
146 return i1;
147 case 8:
148 return i8;
149 case 16:
150 return i16;
151 case 32:
152 return i32;
153 case 64:
154 return i64;
155 case 128:
156 return i128;
157 }
158 MVT VT;
159 VT.V = iAny | (((BitWidth - 1) << SimpleTypeBits) & PrecisionMask);
160 assert(VT.getSizeInBits() == BitWidth && "Bad bit width!");
161 return VT;
162 }
163
164 /// getVectorVT - Returns the MVT that represents a vector NumElements in
165 /// length, where each element is of type VT.
166 static inline MVT getVectorVT(MVT VT, unsigned NumElements) {
167 switch (VT.V) {
168 default:
169 break;
170 case i8:
171 if (NumElements == 8) return v8i8;
172 if (NumElements == 16) return v16i8;
173 break;
174 case i16:
175 if (NumElements == 4) return v4i16;
176 if (NumElements == 8) return v8i16;
177 break;
178 case i32:
179 if (NumElements == 2) return v2i32;
180 if (NumElements == 3) return v3i32;
181 if (NumElements == 4) return v4i32;
182 break;
183 case i64:
184 if (NumElements == 1) return v1i64;
185 if (NumElements == 2) return v2i64;
186 break;
187 case f32:
188 if (NumElements == 2) return v2f32;
189 if (NumElements == 3) return v3f32;
190 if (NumElements == 4) return v4f32;
191 break;
192 case f64:
193 if (NumElements == 2) return v2f64;
194 break;
195 }
196 // Set the length with the top bit forced to zero (needed by the verifier).
197 MVT Result;
198 Result.V = VT.V | (((NumElements + 1) << (33 - VectorBits)) >> 1);
199 assert(Result.getVectorElementType() == VT &&
200 "Bad vector element type!");
201 assert(Result.getVectorNumElements() == NumElements &&
202 "Bad vector length!");
203 return Result;
204 }
205
206 /// getIntVectorWithNumElements - Return any integer vector type that has
207 /// the specified number of elements.
208 static inline MVT getIntVectorWithNumElements(unsigned NumElts) {
209 switch (NumElts) {
210 default: return getVectorVT(i8, NumElts);
211 case 1: return v1i64;
212 case 2: return v2i32;
213 case 3: return v3i32;
214 case 4: return v4i16;
215 case 8: return v8i8;
216 case 16: return v16i8;
217 }
218 }
219
220
221 /// isSimple - Test if the given MVT is simple (as opposed to being
222 /// extended).
223 inline bool isSimple() const {
224 return V <= SimpleTypeMask;
225 }
226
227 /// isExtended - Test if the given MVT is extended (as opposed to
228 /// being simple).
229 inline bool isExtended() const {
230 return !isSimple();
231 }
232
233 /// isFloatingPoint - Return true if this is a FP, or a vector FP type.
234 inline bool isFloatingPoint() const {
235 uint32_t SVT = V & SimpleTypeMask;
236 return (SVT >= f32 && SVT <= ppcf128) || (SVT >= v2f32 && SVT <= v2f64);
237 }
238
239 /// isInteger - Return true if this is an integer, or a vector integer type.
240 inline bool isInteger() const {
241 uint32_t SVT = V & SimpleTypeMask;
242 return (SVT >= FIRST_INTEGER_VALUETYPE && SVT <= LAST_INTEGER_VALUETYPE) ||
243 (SVT >= v8i8 && SVT <= v2i64) || (SVT == iAny && (V & PrecisionMask));
244 }
245
246 /// isVector - Return true if this is a vector value type.
247 inline bool isVector() const {
248 return (V >= FIRST_VECTOR_VALUETYPE && V <= LAST_VECTOR_VALUETYPE) ||
249 (V & VectorMask);
250 }
251
252 /// is64BitVector - Return true if this is a 64-bit vector type.
253 inline bool is64BitVector() const {
254 return (V==v8i8 || V==v4i16 || V==v2i32 || V==v1i64 || V==v2f32 ||
255 (isExtended() && isVector() && getSizeInBits()==64));
256 }
257
258 /// is128BitVector - Return true if this is a 128-bit vector type.
259 inline bool is128BitVector() const {
260 return (V==v16i8 || V==v8i16 || V==v4i32 || V==v2i64 ||
261 V==v4f32 || V==v2f64 ||
262 (isExtended() && isVector() && getSizeInBits()==128));
263 }
264
265
266 /// getSimpleVT - Return the SimpleValueType held in the specified
267 /// simple MVT.
268 inline SimpleValueType getSimpleVT() const {
269 assert(isSimple() && "Expected a SimpleValueType!");
270 return (SimpleValueType)V;
271 }
272
273 /// getVectorElementType - Given a vector type, return the type of
274 /// each element.
275 inline MVT getVectorElementType() const {
276 assert(isVector() && "Invalid vector type!");
277 switch (V) {
278 default: {
279 assert(isExtended() && "Unknown simple vector type!");
280 MVT VT;
281 VT.V = V & ElementMask;
282 return VT;
283 }
284 case v8i8 :
285 case v16i8: return i8;
286 case v4i16:
287 case v8i16: return i16;
288 case v2i32:
289 case v3i32:
290 case v4i32: return i32;
291 case v1i64:
292 case v2i64: return i64;
293 case v2f32:
294 case v3f32:
295 case v4f32: return f32;
296 case v2f64: return f64;
297 }
298 }
299
300 /// getVectorNumElements - Given a vector type, return the number of
301 /// elements it contains.
302 inline unsigned getVectorNumElements() const {
303 assert(isVector() && "Invalid vector type!");
304 switch (V) {
305 default:
306 assert(isExtended() && "Unknown simple vector type!");
307 return ((V & VectorMask) >> (32 - VectorBits)) - 1;
308 case v16i8: return 16;
309 case v8i8 :
310 case v8i16: return 8;
311 case v4i16:
312 case v4i32:
313 case v4f32: return 4;
314 case v3i32:
315 case v3f32: return 3;
316 case v2i32:
317 case v2i64:
318 case v2f32:
319 case v2f64: return 2;
320 case v1i64: return 1;
321 }
322 }
323
324 /// getSizeInBits - Return the size of the specified value type in bits.
325 inline unsigned getSizeInBits() const {
326 switch (V) {
327 default:
328 assert(isExtended() && "MVT has no known size!");
329 if (isVector())
330 return getVectorElementType().getSizeInBits()*getVectorNumElements();
331 if (isInteger())
332 return ((V & PrecisionMask) >> SimpleTypeBits) + 1;
333 assert(false && "Unknown value type!");
334 return 0;
335 case i1 : return 1;
336 case i8 : return 8;
337 case i16 : return 16;
338 case f32 :
339 case i32 : return 32;
340 case f64 :
341 case i64 :
342 case v8i8:
343 case v4i16:
344 case v2i32:
345 case v1i64:
346 case v2f32: return 64;
347 case f80 : return 80;
348 case v3i32:
349 case v3f32: return 96;
350 case f128:
351 case ppcf128:
352 case i128:
353 case v16i8:
354 case v8i16:
355 case v4i32:
356 case v2i64:
357 case v4f32:
358 case v2f64: return 128;
359 }
360 }
361
362 /// getStoreSizeInBits - Return the number of bits overwritten by a store
363 /// of the specified value type.
364 inline unsigned getStoreSizeInBits() const {
365 return (getSizeInBits() + 7)/8*8;
366 }
367
368 /// getRoundIntegerType - Rounds the bit-width of the given integer MVT up
369 /// to the nearest power of two (and at least to eight), and returns the
370 /// integer MVT with that number of bits.
371 inline MVT getRoundIntegerType() const {
372 assert(isInteger() && !isVector() && "Invalid integer type!");
373 unsigned BitWidth = getSizeInBits();
374 if (BitWidth <= 8)
375 return i8;
376 else
377 return getIntegerVT(1 << Log2_32_Ceil(BitWidth));
378 }
379
380 /// getIntegerVTBitMask - Return an integer with 1's every place there are
381 /// bits in the specified integer value type. FIXME: Should return an apint.
382 inline uint64_t getIntegerVTBitMask() const {
383 assert(isInteger() && !isVector() && "Only applies to int scalars!");
384 return ~uint64_t(0UL) >> (64-getSizeInBits());
385 }
386
387 /// getIntegerVTSignBit - Return an integer with a 1 in the position of the
388 /// sign bit for the specified integer value type. FIXME: Should return an
389 /// apint.
390 inline uint64_t getIntegerVTSignBit() const {
391 assert(isInteger() && !isVector() && "Only applies to int scalars!");
392 return uint64_t(1UL) << (getSizeInBits()-1);
393 }
394
395 /// getMVTString - This function returns value type as a string,
396 /// e.g. "i32".
397 std::string getMVTString() const;
398
399 /// getTypeForMVT - This method returns an LLVM type corresponding to the
400 /// specified MVT. For integer types, this returns an unsigned type. Note
401 /// that this will abort for types that cannot be represented.
402 const Type *getTypeForMVT() const;
403
404 /// getMVT - Return the value type corresponding to the specified type.
405 /// This returns all pointers as iPTR. If HandleUnknown is true, unknown
406 /// types are returned as Other, otherwise they are invalid.
407 static MVT getMVT(const Type *Ty, bool HandleUnknown = false);
86408 };
87409
88 /// MVT::ValueType - This type holds low-level value types. Valid values
89 /// include any of the values in the SimpleValueType enum, or any value
90 /// returned from a function in the MVT namespace that has a ValueType
91 /// return type. Any value type equal to one of the SimpleValueType enum
92 /// values is a "simple" value type. All other value types are "extended".
93 ///
94 /// Note that simple doesn't necessary mean legal for the target machine.
95 /// All legal value types must be simple, but often there are some simple
96 /// value types that are not legal.
97 ///
98 /// @internal
99 /// Extended types are either vector types or arbitrary precision integers.
100 /// Arbitrary precision integers have iAny in the first SimpleTypeBits bits,
101 /// and the bit-width in the next PrecisionBits bits, offset by minus one.
102 /// Vector types are encoded by having the first SimpleTypeBits+PrecisionBits
103 /// bits encode the vector element type (which must be a scalar type, possibly
104 /// an arbitrary precision integer) and the remaining VectorBits upper bits
105 /// encode the vector length, offset by one.
106 ///
107 /// 31--------------16-----------8-------------0
108 /// | Vector length | Precision | Simple type |
109 /// | | Vector element |
110 ///
111 /// Note that the verifier currently requires the top bit to be zero.
112
113 typedef uint32_t ValueType;
114
115 static const int SimpleTypeBits = 8;
116 static const int PrecisionBits = 8;
117 static const int VectorBits = 32 - SimpleTypeBits - PrecisionBits;
118
119 static const uint32_t SimpleTypeMask =
120 (~uint32_t(0) << (32 - SimpleTypeBits)) >> (32 - SimpleTypeBits);
121
122 static const uint32_t PrecisionMask =
123 ((~uint32_t(0) << VectorBits) >> (32 - PrecisionBits)) << SimpleTypeBits;
124
125 static const uint32_t VectorMask =
126 (~uint32_t(0) >> (32 - VectorBits)) << (32 - VectorBits);
127
128 static const uint32_t ElementMask =
129 (~uint32_t(0) << VectorBits) >> VectorBits;
130
131 /// MVT::isExtendedVT - Test if the given ValueType is extended
132 /// (as opposed to being simple).
133 static inline bool isExtendedVT(ValueType VT) {
134 return VT > SimpleTypeMask;
135 }
136
137 /// MVT::isInteger - Return true if this is an integer, or a vector integer
138 /// type.
139 static inline bool isInteger(ValueType VT) {
140 ValueType SVT = VT & SimpleTypeMask;
141 return (SVT >= FIRST_INTEGER_VALUETYPE && SVT <= LAST_INTEGER_VALUETYPE) ||
142 (SVT >= v8i8 && SVT <= v2i64) || (SVT == iAny && (VT & PrecisionMask));
143 }
144
145 /// MVT::isFloatingPoint - Return true if this is an FP, or a vector FP type.
146 static inline bool isFloatingPoint(ValueType VT) {
147 ValueType SVT = VT & SimpleTypeMask;
148 return (SVT >= f32 && SVT <= ppcf128) || (SVT >= v2f32 && SVT <= v2f64);
149 }
150
151 /// MVT::isVector - Return true if this is a vector value type.
152 static inline bool isVector(ValueType VT) {
153 return (VT >= FIRST_VECTOR_VALUETYPE && VT <= LAST_VECTOR_VALUETYPE) ||
154 (VT & VectorMask);
155 }
156
157 /// MVT::getVectorElementType - Given a vector type, return the type of
158 /// each element.
159 static inline ValueType getVectorElementType(ValueType VT) {
160 assert(isVector(VT) && "Invalid vector type!");
161 switch (VT) {
162 default:
163 assert(isExtendedVT(VT) && "Unknown simple vector type!");
164 return VT & ElementMask;
165 case v8i8 :
166 case v16i8: return i8;
167 case v4i16:
168 case v8i16: return i16;
169 case v2i32:
170 case v3i32:
171 case v4i32: return i32;
172 case v1i64:
173 case v2i64: return i64;
174 case v2f32:
175 case v3f32:
176 case v4f32: return f32;
177 case v2f64: return f64;
178 }
179 }
180
181 /// MVT::getVectorNumElements - Given a vector type, return the
182 /// number of elements it contains.
183 static inline unsigned getVectorNumElements(ValueType VT) {
184 assert(isVector(VT) && "Invalid vector type!");
185 switch (VT) {
186 default:
187 assert(isExtendedVT(VT) && "Unknown simple vector type!");
188 return ((VT & VectorMask) >> (32 - VectorBits)) - 1;
189 case v16i8: return 16;
190 case v8i8 :
191 case v8i16: return 8;
192 case v4i16:
193 case v4i32:
194 case v4f32: return 4;
195 case v3i32:
196 case v3f32: return 3;
197 case v2i32:
198 case v2i64:
199 case v2f32:
200 case v2f64: return 2;
201 case v1i64: return 1;
202 }
203 }
204
205 /// MVT::getSizeInBits - Return the size of the specified value type
206 /// in bits.
207 ///
208 static inline unsigned getSizeInBits(ValueType VT) {
209 switch (VT) {
210 default:
211 assert(isExtendedVT(VT) && "ValueType has no known size!");
212 if (isVector(VT))
213 return getSizeInBits(getVectorElementType(VT)) *
214 getVectorNumElements(VT);
215 if (isInteger(VT))
216 return ((VT & PrecisionMask) >> SimpleTypeBits) + 1;
217 assert(0 && "Unknown value type!");
218 case MVT::i1 : return 1;
219 case MVT::i8 : return 8;
220 case MVT::i16 : return 16;
221 case MVT::f32 :
222 case MVT::i32 : return 32;
223 case MVT::f64 :
224 case MVT::i64 :
225 case MVT::v8i8:
226 case MVT::v4i16:
227 case MVT::v2i32:
228 case MVT::v1i64:
229 case MVT::v2f32: return 64;
230 case MVT::f80 : return 80;
231 case MVT::v3i32:
232 case MVT::v3f32: return 96;
233 case MVT::f128:
234 case MVT::ppcf128:
235 case MVT::i128:
236 case MVT::v16i8:
237 case MVT::v8i16:
238 case MVT::v4i32:
239 case MVT::v2i64:
240 case MVT::v4f32:
241 case MVT::v2f64: return 128;
242 }
243 }
244
245 /// MVT::getStoreSizeInBits - Return the number of bits overwritten by a
246 /// store of the specified value type.
247 ///
248 static inline unsigned getStoreSizeInBits(ValueType VT) {
249 return (getSizeInBits(VT) + 7)/8*8;
250 }
251
252 /// MVT::is64BitVector - Return true if this is a 64-bit vector type.
253 static inline bool is64BitVector(ValueType VT) {
254 return (VT==v8i8 || VT==v4i16 || VT==v2i32 || VT==v1i64 || VT==v2f32 ||
255 (isExtendedVT(VT) && isVector(VT) && getSizeInBits(VT)==64));
256 }
257
258 /// MVT::is128BitVector - Return true if this is a 128-bit vector type.
259 static inline bool is128BitVector(ValueType VT) {
260 return (VT==v16i8 || VT==v8i16 || VT==v4i32 || VT==v2i64 ||
261 VT==v4f32 || VT==v2f64 ||
262 (isExtendedVT(VT) && isVector(VT) && getSizeInBits(VT)==128));
263 }
264
265 /// MVT::getIntegerType - Returns the ValueType that represents an integer
266 /// with the given number of bits.
267 ///
268 static inline ValueType getIntegerType(unsigned BitWidth) {
269 switch (BitWidth) {
270 default:
271 break;
272 case 1:
273 return MVT::i1;
274 case 8:
275 return MVT::i8;
276 case 16:
277 return MVT::i16;
278 case 32:
279 return MVT::i32;
280 case 64:
281 return MVT::i64;
282 case 128:
283 return MVT::i128;
284 }
285 ValueType Result = iAny |
286 (((BitWidth - 1) << SimpleTypeBits) & PrecisionMask);
287 assert(getSizeInBits(Result) == BitWidth && "Bad bit width!");
288 return Result;
289 }
290
291 /// MVT::RoundIntegerType - Rounds the bit-width of the given integer
292 /// ValueType up to the nearest power of two (and at least to eight),
293 /// and returns the integer ValueType with that number of bits.
294 ///
295 static inline ValueType RoundIntegerType(ValueType VT) {
296 assert(isInteger(VT) && !isVector(VT) && "Invalid integer type!");
297 unsigned BitWidth = getSizeInBits(VT);
298 if (BitWidth <= 8)
299 return MVT::i8;
300 else
301 return getIntegerType(1 << Log2_32_Ceil(BitWidth));
302 }
303
304 /// MVT::getVectorType - Returns the ValueType that represents a vector
305 /// NumElements in length, where each element is of type VT.
306 ///
307 static inline ValueType getVectorType(ValueType VT, unsigned NumElements) {
308 switch (VT) {
309 default:
310 break;
311 case MVT::i8:
312 if (NumElements == 8) return MVT::v8i8;
313 if (NumElements == 16) return MVT::v16i8;
314 break;
315 case MVT::i16:
316 if (NumElements == 4) return MVT::v4i16;
317 if (NumElements == 8) return MVT::v8i16;
318 break;
319 case MVT::i32:
320 if (NumElements == 2) return MVT::v2i32;
321 if (NumElements == 3) return MVT::v3i32;
322 if (NumElements == 4) return MVT::v4i32;
323 break;
324 case MVT::i64:
325 if (NumElements == 1) return MVT::v1i64;
326 if (NumElements == 2) return MVT::v2i64;
327 break;
328 case MVT::f32:
329 if (NumElements == 2) return MVT::v2f32;
330 if (NumElements == 3) return MVT::v3f32;
331 if (NumElements == 4) return MVT::v4f32;
332 break;
333 case MVT::f64:
334 if (NumElements == 2) return MVT::v2f64;
335 break;
336 }
337 // Set the length with the top bit forced to zero (needed by the verifier).
338 ValueType Result = VT | (((NumElements + 1) << (33 - VectorBits)) >> 1);
339 assert(getVectorElementType(Result) == VT &&
340 "Bad vector element type!");
341 assert(getVectorNumElements(Result) == NumElements &&
342 "Bad vector length!");
343 return Result;
344 }
345
346 /// MVT::getIntVectorWithNumElements - Return any integer vector type that has
347 /// the specified number of elements.
348 static inline ValueType getIntVectorWithNumElements(unsigned NumElts) {
349 switch (NumElts) {
350 default: return getVectorType(i8, NumElts);
351 case 1: return v1i64;
352 case 2: return v2i32;
353 case 3: return v3i32;
354 case 4: return v4i16;
355 case 8: return v8i8;
356 case 16: return v16i8;
357 }
358 }
359
360
361 /// MVT::getIntVTBitMask - Return an integer with 1's every place there are
362 /// bits in the specified integer value type.
363 static inline uint64_t getIntVTBitMask(ValueType VT) {
364 assert(isInteger(VT) && !isVector(VT) && "Only applies to int scalars!");
365 return ~uint64_t(0UL) >> (64-getSizeInBits(VT));
366 }
367 /// MVT::getIntVTSignBit - Return an integer with a 1 in the position of the
368 /// sign bit for the specified integer value type.
369 static inline uint64_t getIntVTSignBit(ValueType VT) {
370 assert(isInteger(VT) && !isVector(VT) && "Only applies to int scalars!");
371 return uint64_t(1UL) << (getSizeInBits(VT)-1);
372 }
373
374 /// MVT::getValueTypeString - This function returns value type as a string,
375 /// e.g. "i32".
376 std::string getValueTypeString(ValueType VT);
377
378 /// MVT::getTypeForValueType - This method returns an LLVM type corresponding
379 /// to the specified ValueType. For integer types, this returns an unsigned
380 /// type. Note that this will abort for types that cannot be represented.
381 const Type *getTypeForValueType(ValueType VT);
382
383 /// MVT::getValueType - Return the value type corresponding to the specified
384 /// type. This returns all pointers as MVT::iPTR. If HandleUnknown is true,
385 /// unknown types are returned as Other, otherwise they are invalid.
386 ValueType getValueType(const Type *Ty, bool HandleUnknown = false);
387 }
388
389410 } // End llvm namespace
390411
391412 #endif
8989
9090 bool isBigEndian() const { return !IsLittleEndian; }
9191 bool isLittleEndian() const { return IsLittleEndian; }
92 MVT::ValueType getPointerTy() const { return PointerTy; }
93 MVT::ValueType getShiftAmountTy() const { return ShiftAmountTy; }
92 MVT getPointerTy() const { return PointerTy; }
93 MVT getShiftAmountTy() const { return ShiftAmountTy; }
9494 OutOfRangeShiftAmount getShiftAmountFlavor() const {return ShiftAmtHandling; }
9595
9696 /// usesGlobalOffsetTable - Return true if this target uses a GOT for PIC
111111
112112 /// getSetCCResultType - Return the ValueType of the result of setcc
113113 /// operations.
114 virtual MVT::ValueType getSetCCResultType(const SDOperand &) const;
114 virtual MVT getSetCCResultType(const SDOperand &) const;
115115
116116 /// getSetCCResultContents - For targets without boolean registers, this flag
117117 /// returns information about the contents of the high-bits in the setcc
125125
126126 /// getRegClassFor - Return the register class that should be used for the
127127 /// specified value type. This may only be called on legal types.
128 TargetRegisterClass *getRegClassFor(MVT::ValueType VT) const {
129 assert(VT < array_lengthof(RegClassForVT));
130 TargetRegisterClass *RC = RegClassForVT[VT];
128 TargetRegisterClass *getRegClassFor(MVT VT) const {
129 assert((unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT));
130 TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT()];
131131 assert(RC && "This value type is not natively supported!");
132132 return RC;
133133 }
135135 /// isTypeLegal - Return true if the target has native support for the
136136 /// specified value type. This means that it has a register that directly
137137 /// holds it without promotions or expansions.
138 bool isTypeLegal(MVT::ValueType VT) const {
139 assert(MVT::isExtendedVT(VT) || VT < array_lengthof(RegClassForVT));
140 return !MVT::isExtendedVT(VT) && RegClassForVT[VT] != 0;
138 bool isTypeLegal(MVT VT) const {
139 assert(!VT.isSimple() ||
140 (unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT));
141 return VT.isSimple() && RegClassForVT[VT.getSimpleVT()] != 0;
141142 }
142143
143144 class ValueTypeActionImpl {
154155 ValueTypeActions[1] = RHS.ValueTypeActions[1];
155156 }
156157
157 LegalizeAction getTypeAction(MVT::ValueType VT) const {
158 if (MVT::isExtendedVT(VT)) {
159 if (MVT::isVector(VT)) return Expand;
160 if (MVT::isInteger(VT))
158 LegalizeAction getTypeAction(MVT VT) const {
159 if (VT.isExtended()) {
160 if (VT.isVector()) return Expand;
161 if (VT.isInteger())
161162 // First promote to a power-of-two size, then expand if necessary.
162 return VT == MVT::RoundIntegerType(VT) ? Expand : Promote;
163 return VT == VT.getRoundIntegerType() ? Expand : Promote;
163164 assert(0 && "Unsupported extended type!");
165 return Legal;
164166 }
165 assert(VT<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0]));
166 return (LegalizeAction)((ValueTypeActions[VT>>4] >> ((2*VT) & 31)) & 3);
167 }
168 void setTypeAction(MVT::ValueType VT, LegalizeAction Action) {
169 assert(VT<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0]));
170 ValueTypeActions[VT>>4] |= Action << ((VT*2) & 31);
167 unsigned I = VT.getSimpleVT();
168 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0]));
169 return (LegalizeAction)((ValueTypeActions[I>>4] >> ((2*I) & 31)) & 3);
170 }
171 void setTypeAction(MVT VT, LegalizeAction Action) {
172 unsigned I = VT.getSimpleVT();
173 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0]));
174 ValueTypeActions[I>>4] |= Action << ((I*2) & 31);
171175 }
172176 };
173177
179183 /// it is already legal (return 'Legal') or we need to promote it to a larger
180184 /// type (return 'Promote'), or we need to expand it into multiple registers
181185 /// of smaller integer type (return 'Expand'). 'Custom' is not an option.
182 LegalizeAction getTypeAction(MVT::ValueType VT) const {
186 LegalizeAction getTypeAction(MVT VT) const {
183187 return ValueTypeActions.getTypeAction(VT);
184188 }
185189
189193 /// than the largest integer register, this contains one step in the expansion
190194 /// to get to the smaller register. For illegal floating point types, this
191195 /// returns the integer type to transform to.
192 MVT::ValueType getTypeToTransformTo(MVT::ValueType VT) const {
193 if (!MVT::isExtendedVT(VT)) {
194 assert(VT < array_lengthof(TransformToType));
195 MVT::ValueType NVT = TransformToType[VT];
196 MVT getTypeToTransformTo(MVT VT) const {
197 if (VT.isSimple()) {
198 assert((unsigned)VT.getSimpleVT() < array_lengthof(TransformToType));
199 MVT NVT = TransformToType[VT.getSimpleVT()];
196200 assert(getTypeAction(NVT) != Promote &&
197201 "Promote may not follow Expand or Promote");
198202 return NVT;
199203 }
200204
201 if (MVT::isVector(VT))
202 return MVT::getVectorType(MVT::getVectorElementType(VT),
203 MVT::getVectorNumElements(VT) / 2);
204 if (MVT::isInteger(VT)) {
205 MVT::ValueType NVT = MVT::RoundIntegerType(VT);
205 if (VT.isVector())
206 return MVT::getVectorVT(VT.getVectorElementType(),
207 VT.getVectorNumElements() / 2);
208 if (VT.isInteger()) {
209 MVT NVT = VT.getRoundIntegerType();
206210 if (NVT == VT)
207211 // Size is a power of two - expand to half the size.
208 return MVT::getIntegerType(MVT::getSizeInBits(VT) / 2);
212 return MVT::getIntegerVT(VT.getSizeInBits() / 2);
209213 else
210214 // Promote to a power of two size, avoiding multi-step promotion.
211215 return getTypeAction(NVT) == Promote ? getTypeToTransformTo(NVT) : NVT;
212216 }
213217 assert(0 && "Unsupported extended type!");
214 return MVT::ValueType(); // Not reached
218 return MVT(); // Not reached
215219 }
216220
217221 /// getTypeToExpandTo - For types supported by the target, this is an
218222 /// identity function. For types that must be expanded (i.e. integer types
219223 /// that are larger than the largest integer register or illegal floating
220224 /// point types), this returns the largest legal type it will be expanded to.
221 MVT::ValueType getTypeToExpandTo(MVT::ValueType VT) const {
222 assert(!MVT::isVector(VT));
225 MVT getTypeToExpandTo(MVT VT) const {
226 assert(!VT.isVector());
223227 while (true) {
224228 switch (getTypeAction(VT)) {
225229 case Legal:
244248 /// register. It also returns the VT and quantity of the intermediate values
245249 /// before they are promoted/expanded.
246250 ///
247 unsigned getVectorTypeBreakdown(MVT::ValueType VT,
248 MVT::ValueType &IntermediateVT,
251 unsigned getVectorTypeBreakdown(MVT VT,
252 MVT &IntermediateVT,
249253 unsigned &NumIntermediates,
250 MVT::ValueType &RegisterVT) const;
254 MVT &RegisterVT) const;
251255
252256 typedef std::vector::const_iterator legal_fpimm_iterator;
253257 legal_fpimm_iterator legal_fpimm_begin() const {
261265 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
262266 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
263267 /// are assumed to be legal.
264 virtual bool isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const {
268 virtual bool isShuffleMaskLegal(SDOperand Mask, MVT VT) const {
265269 return true;
266270 }
267271
270274 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
271275 /// pool entry.
272276 virtual bool isVectorClearMaskLegal(const std::vector &BVOps,
273 MVT::ValueType EVT,
277 MVT EVT,
274278 SelectionDAG &DAG) const {
275279 return false;
276280 }
279283 /// it is legal, needs to be promoted to a larger size, needs to be
280284 /// expanded to some other code sequence, or the target has a custom expander
281285 /// for it.
282 LegalizeAction getOperationAction(unsigned Op, MVT::ValueType VT) const {
283 if (MVT::isExtendedVT(VT)) return Expand;
286 LegalizeAction getOperationAction(unsigned Op, MVT VT) const {
287 if (VT.isExtended()) return Expand;
284288 assert(Op < array_lengthof(OpActions) &&
285 VT < sizeof(OpActions[0])*4 && "Table isn't big enough!");
286 return (LegalizeAction)((OpActions[Op] >> (2*VT)) & 3);
289 (unsigned)VT.getSimpleVT() < sizeof(OpActions[0])*4 &&
290 "Table isn't big enough!");
291 return (LegalizeAction)((OpActions[Op] >> (2*VT.getSimpleVT())) & 3);
287292 }
288293
289294 /// isOperationLegal - Return true if the specified operation is legal on this
290295 /// target.
291 bool isOperationLegal(unsigned Op, MVT::ValueType VT) const {
296 bool isOperationLegal(unsigned Op, MVT VT) const {
292297 return getOperationAction(Op, VT) == Legal ||
293298 getOperationAction(Op, VT) == Custom;
294299 }
297302 /// either it is legal, needs to be promoted to a larger size, needs to be
298303 /// expanded to some other code sequence, or the target has a custom expander
299304 /// for it.
300 LegalizeAction getLoadXAction(unsigned LType, MVT::ValueType VT) const {
305 LegalizeAction getLoadXAction(unsigned LType, MVT VT) const {
301306 assert(LType < array_lengthof(LoadXActions) &&
302 VT < sizeof(LoadXActions[0])*4 && "Table isn't big enough!");
303 return (LegalizeAction)((LoadXActions[LType] >> (2*VT)) & 3);
307 (unsigned)VT.getSimpleVT() < sizeof(LoadXActions[0])*4 &&
308 "Table isn't big enough!");
309 return (LegalizeAction)((LoadXActions[LType] >> (2*VT.getSimpleVT())) & 3);
304310 }
305311
306312 /// isLoadXLegal - Return true if the specified load with extension is legal
307313 /// on this target.
308 bool isLoadXLegal(unsigned LType, MVT::ValueType VT) const {
309 return !MVT::isExtendedVT(VT) &&
314 bool isLoadXLegal(unsigned LType, MVT VT) const {
315 return VT.isSimple() &&
310316 (getLoadXAction(LType, VT) == Legal ||
311317 getLoadXAction(LType, VT) == Custom);
312318 }
315321 /// treated: either it is legal, needs to be promoted to a larger size, needs
316322 /// to be expanded to some other code sequence, or the target has a custom
317323 /// expander for it.
318 LegalizeAction getTruncStoreAction(MVT::ValueType ValVT,
319 MVT::ValueType MemVT) const {
320 assert(ValVT < array_lengthof(TruncStoreActions) &&
321 MemVT < sizeof(TruncStoreActions[0])*4 && "Table isn't big enough!");
322 return (LegalizeAction)((TruncStoreActions[ValVT] >> (2*MemVT)) & 3);
324 LegalizeAction getTruncStoreAction(MVT ValVT,
325 MVT MemVT) const {
326 assert((unsigned)ValVT.getSimpleVT() < array_lengthof(TruncStoreActions) &&
327 (unsigned)MemVT.getSimpleVT() < sizeof(TruncStoreActions[0])*4 &&
328 "Table isn't big enough!");
329 return (LegalizeAction)((TruncStoreActions[ValVT.getSimpleVT()] >>
330 (2*MemVT.getSimpleVT())) & 3);
323331 }
324332
325333 /// isTruncStoreLegal - Return true if the specified store with truncation is
326334 /// legal on this target.
327 bool isTruncStoreLegal(MVT::ValueType ValVT, MVT::ValueType MemVT) const {
328 return !MVT::isExtendedVT(MemVT) &&
335 bool isTruncStoreLegal(MVT ValVT, MVT MemVT) const {
336 return MemVT.isSimple() &&
329337 (getTruncStoreAction(ValVT, MemVT) == Legal ||
330338 getTruncStoreAction(ValVT, MemVT) == Custom);
331339 }
335343 /// expanded to some other code sequence, or the target has a custom expander
336344 /// for it.
337345 LegalizeAction
338 getIndexedLoadAction(unsigned IdxMode, MVT::ValueType VT) const {
346 getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
339347 assert(IdxMode < array_lengthof(IndexedModeActions[0]) &&
340 VT < sizeof(IndexedModeActions[0][0])*4 &&
348 (unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[0][0])*4 &&
341349 "Table isn't big enough!");
342 return (LegalizeAction)((IndexedModeActions[0][IdxMode] >> (2*VT)) & 3);
350 return (LegalizeAction)((IndexedModeActions[0][IdxMode] >>
351 (2*VT.getSimpleVT())) & 3);
343352 }
344353
345354 /// isIndexedLoadLegal - Return true if the specified indexed load is legal
346355 /// on this target.
347 bool isIndexedLoadLegal(unsigned IdxMode, MVT::ValueType VT) const {
356 bool isIndexedLoadLegal(unsigned IdxMode, MVT VT) const {
348357 return getIndexedLoadAction(IdxMode, VT) == Legal ||
349358 getIndexedLoadAction(IdxMode, VT) == Custom;
350359 }
354363 /// expanded to some other code sequence, or the target has a custom expander
355364 /// for it.
356365 LegalizeAction
357 getIndexedStoreAction(unsigned IdxMode, MVT::ValueType VT) const {
366 getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
358367 assert(IdxMode < array_lengthof(IndexedModeActions[1]) &&
359 VT < sizeof(IndexedModeActions[1][0])*4 &&
368 (unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[1][0])*4 &&
360369 "Table isn't big enough!");
361 return (LegalizeAction)((IndexedModeActions[1][IdxMode] >> (2*VT)) & 3);
370 return (LegalizeAction)((IndexedModeActions[1][IdxMode] >>
371 (2*VT.getSimpleVT())) & 3);
362372 }
363373
364374 /// isIndexedStoreLegal - Return true if the specified indexed load is legal
365375 /// on this target.
366 bool isIndexedStoreLegal(unsigned IdxMode, MVT::ValueType VT) const {
376 bool isIndexedStoreLegal(unsigned IdxMode, MVT VT) const {
367377 return getIndexedStoreAction(IdxMode, VT) == Legal ||
368378 getIndexedStoreAction(IdxMode, VT) == Custom;
369379 }
373383 /// expanded to some other code sequence, or the target has a custom expander
374384 /// for it.
375385 LegalizeAction
376 getConvertAction(MVT::ValueType FromVT, MVT::ValueType ToVT) const {
377 assert(FromVT < array_lengthof(ConvertActions) &&
378 ToVT < sizeof(ConvertActions[0])*4 && "Table isn't big enough!");
379 return (LegalizeAction)((ConvertActions[FromVT] >> (2*ToVT)) & 3);
386 getConvertAction(MVT FromVT, MVT ToVT) const {
387 assert((unsigned)FromVT.getSimpleVT() < array_lengthof(ConvertActions) &&
388 (unsigned)ToVT.getSimpleVT() < sizeof(ConvertActions[0])*4 &&
389 "Table isn't big enough!");
390 return (LegalizeAction)((ConvertActions[FromVT.getSimpleVT()] >>
391 (2*ToVT.getSimpleVT())) & 3);
380392 }
381393
382394 /// isConvertLegal - Return true if the specified conversion is legal
383395 /// on this target.
384 bool isConvertLegal(MVT::ValueType FromVT, MVT::ValueType ToVT) const {
396 bool isConvertLegal(MVT FromVT, MVT ToVT) const {
385397 return getConvertAction(FromVT, ToVT) == Legal ||
386398 getConvertAction(FromVT, ToVT) == Custom;
387399 }
388400
389401 /// getTypeToPromoteTo - If the action for this operation is to promote, this
390402 /// method returns the ValueType to promote to.
391 MVT::ValueType getTypeToPromoteTo(unsigned Op, MVT::ValueType VT) const {
403 MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
392404 assert(getOperationAction(Op, VT) == Promote &&
393405 "This operation isn't promoted!");
394406
395407 // See if this has an explicit type specified.
396 std::map,
397 MVT::ValueType>::const_iterator PTTI =
408 std::map,
409 MVT>::const_iterator PTTI =
398410 PromoteToType.find(std::make_pair(Op, VT));
399411 if (PTTI != PromoteToType.end()) return PTTI->second;
400
401 assert((MVT::isInteger(VT) || MVT::isFloatingPoint(VT)) &&
412
413 assert((VT.isInteger() || VT.isFloatingPoint()) &&
402414 "Cannot autopromote this type, add it with AddPromotedToType.");
403415
404 MVT::ValueType NVT = VT;
416 MVT NVT = VT;
405417 do {
406 NVT = (MVT::ValueType)(NVT+1);
407 assert(MVT::isInteger(NVT) == MVT::isInteger(VT) && NVT != MVT::isVoid &&
418 NVT = (MVT::SimpleValueType)(NVT.getSimpleVT()+1);
419 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
408420 "Didn't find type to promote to!");
409421 } while (!isTypeLegal(NVT) ||
410422 getOperationAction(Op, NVT) == Promote);
411423 return NVT;
412424 }
413425
414 /// getValueType - Return the MVT::ValueType corresponding to this LLVM type.
426 /// getValueType - Return the MVT corresponding to this LLVM type.
415427 /// This is fixed by the LLVM operations except for the pointer size. If
416428 /// AllowUnknown is true, this will return MVT::Other for types with no MVT
417429 /// counterpart (e.g. structs), otherwise it will assert.
418 MVT::ValueType getValueType(const Type *Ty, bool AllowUnknown = false) const {
419 MVT::ValueType VT = MVT::getValueType(Ty, AllowUnknown);
430 MVT getValueType(const Type *Ty, bool AllowUnknown = false) const {
431 MVT VT = MVT::getMVT(Ty, AllowUnknown);
420432 return VT == MVT::iPTR ? PointerTy : VT;
421433 }
422434
427439
428440 /// getRegisterType - Return the type of registers that this ValueType will
429441 /// eventually require.
430 MVT::ValueType getRegisterType(MVT::ValueType VT) const {
431 if (!MVT::isExtendedVT(VT)) {
432 assert(VT < array_lengthof(RegisterTypeForVT));
433 return RegisterTypeForVT[VT];
434 }
435 if (MVT::isVector(VT)) {
436 MVT::ValueType VT1, RegisterVT;
442 MVT getRegisterType(MVT VT) const {
443 if (VT.isSimple()) {
444 assert((unsigned)VT.getSimpleVT() < array_lengthof(RegisterTypeForVT));
445 return RegisterTypeForVT[VT.getSimpleVT()];
446 }
447 if (VT.isVector()) {
448 MVT VT1, RegisterVT;
437449 unsigned NumIntermediates;
438450 (void)getVectorTypeBreakdown(VT, VT1, NumIntermediates, RegisterVT);
439451 return RegisterVT;
440452 }
441 if (MVT::isInteger(VT)) {
453 if (VT.isInteger()) {
442454 return getRegisterType(getTypeToTransformTo(VT));
443455 }
444456 assert(0 && "Unsupported extended type!");
445 return MVT::ValueType(); // Not reached
457 return MVT(); // Not reached
446458 }
447459
448460 /// getNumRegisters - Return the number of registers that this ValueType will
451463 /// into pieces. For types like i140, which are first promoted then expanded,
452464 /// it is the number of registers needed to hold all the bits of the original
453465 /// type. For an i140 on a 32 bit machine this means 5 registers.
454 unsigned getNumRegisters(MVT::ValueType VT) const {
455 if (!MVT::isExtendedVT(VT)) {
456 assert(VT < array_lengthof(NumRegistersForVT));
457 return NumRegistersForVT[VT];
458 }
459 if (MVT::isVector(VT)) {
460 MVT::ValueType VT1, VT2;
466 unsigned getNumRegisters(MVT VT) const {
467 if (VT.isSimple()) {
468 assert((unsigned)VT.getSimpleVT() < array_lengthof(NumRegistersForVT));
469 return NumRegistersForVT[VT.getSimpleVT()];
470 }
471 if (VT.isVector()) {
472 MVT VT1, VT2;
461473 unsigned NumIntermediates;
462474 return getVectorTypeBreakdown(VT, VT1, NumIntermediates, VT2);
463475 }
464 if (MVT::isInteger(VT)) {
465 unsigned BitWidth = MVT::getSizeInBits(VT);
466 unsigned RegWidth = MVT::getSizeInBits(getRegisterType(VT));
476 if (VT.isInteger()) {
477 unsigned BitWidth = VT.getSizeInBits();
478 unsigned RegWidth = getRegisterType(VT).getSizeInBits();
467479 return (BitWidth + RegWidth - 1) / RegWidth;
468480 }
469481 assert(0 && "Unsupported extended type!");
473485 /// ShouldShrinkFPConstant - If true, then instruction selection should
474486 /// seek to shrink the FP constant of the specified type to a smaller type
475487 /// in order to save space and / or reduce runtime.
476 virtual bool ShouldShrinkFPConstant(MVT::ValueType VT) const { return true; }
488 virtual bool ShouldShrinkFPConstant(MVT VT) const { return true; }
477489
478490 /// hasTargetDAGCombine - If true, the target has custom DAG combine
479491 /// transformations that it can perform for the specified node.
514526 /// and store operations as a result of memset, memcpy, and memmove lowering.
515527 /// It returns MVT::iAny if SelectionDAG should be responsible for
516528 /// determining it.
517 virtual MVT::ValueType getOptimalMemOpType(uint64_t Size, unsigned Align,
518 bool isSrcConst, bool isSrcStr) const {
529 virtual MVT getOptimalMemOpType(uint64_t Size, unsigned Align,
530 bool isSrcConst, bool isSrcStr) const {
519531 return MVT::iAny;
520532 }
521533
686698
687699 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
688700 /// and cc. If it is unable to simplify it, return a null SDOperand.
689 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
701 SDOperand SimplifySetCC(MVT VT, SDOperand N0, SDOperand N1,
690702 ISD::CondCode Cond, bool foldBooleans,
691703 DAGCombinerInfo &DCI) const;
692704
728740
729741 /// setShiftAmountType - Describe the type that should be used for shift
730742 /// amounts. This type defaults to the pointer type.
731 void setShiftAmountType(MVT::ValueType VT) { ShiftAmountTy = VT; }
743 void setShiftAmountType(MVT VT) { ShiftAmountTy = VT; }
732744
733745 /// setSetCCResultContents - Specify how the target extends the result of a
734746 /// setcc operation in a register.
797809 /// addRegisterClass - Add the specified register class as an available
798810 /// regclass for the specified value type. This indicates the selector can
799811 /// handle values of that class natively.
800 void addRegisterClass(MVT::ValueType VT, TargetRegisterClass *RC) {
801 assert(VT < array_lengthof(RegClassForVT));
812 void addRegisterClass(MVT VT, TargetRegisterClass *RC) {
813 assert((unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT));
802814 AvailableRegClasses.push_back(std::make_pair(VT, RC));
803 RegClassForVT[VT] = RC;
815 RegClassForVT[VT.getSimpleVT()] = RC;
804816 }
805817
806818 /// computeRegisterProperties - Once all of the register classes are added,
809821
810822 /// setOperationAction - Indicate that the specified operation does not work
811823 /// with the specified type and indicate what to do about it.
812 void setOperationAction(unsigned Op, MVT::ValueType VT,
824 void setOperationAction(unsigned Op, MVT VT,
813825 LegalizeAction Action) {
814 assert(VT < sizeof(OpActions[0])*4 && Op < array_lengthof(OpActions) &&
815 "Table isn't big enough!");
816 OpActions[Op] &= ~(uint64_t(3UL) << VT*2);
817 OpActions[Op] |= (uint64_t)Action << VT*2;
826 assert((unsigned)VT.getSimpleVT() < sizeof(OpActions[0])*4 &&
827 Op < array_lengthof(OpActions) && "Table isn't big enough!");
828 OpActions[Op] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2);
829 OpActions[Op] |= (uint64_t)Action << VT.getSimpleVT()*2;
818830 }
819831
820832 /// setLoadXAction - Indicate that the specified load with extension does not
821833 /// work with the with specified type and indicate what to do about it.
822 void setLoadXAction(unsigned ExtType, MVT::ValueType VT,
834 void setLoadXAction(unsigned ExtType, MVT VT,
823835 LegalizeAction Action) {
824 assert(VT < sizeof(LoadXActions[0])*4 &&
836 assert((unsigned)VT.getSimpleVT() < sizeof(LoadXActions[0])*4 &&
825837 ExtType < array_lengthof(LoadXActions) &&
826838 "Table isn't big enough!");
827 LoadXActions[ExtType] &= ~(uint64_t(3UL) << VT*2);
828 LoadXActions[ExtType] |= (uint64_t)Action << VT*2;
839 LoadXActions[ExtType] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2);
840 LoadXActions[ExtType] |= (uint64_t)Action << VT.getSimpleVT()*2;
829841 }
830842
831843 /// setTruncStoreAction - Indicate that the specified truncating store does
832844 /// not work with the with specified type and indicate what to do about it.
833 void setTruncStoreAction(MVT::ValueType ValVT, MVT::ValueType MemVT,
845 void setTruncStoreAction(MVT ValVT, MVT MemVT,
834846 LegalizeAction Action) {
835 assert(ValVT < array_lengthof(TruncStoreActions) &&
836 MemVT < sizeof(TruncStoreActions[0])*4 && "Table isn't big enough!");
837 TruncStoreActions[ValVT] &= ~(uint64_t(3UL) << MemVT*2);
838 TruncStoreActions[ValVT] |= (uint64_t)Action << MemVT*2;
847 assert((unsigned)ValVT.getSimpleVT() < array_lengthof(TruncStoreActions) &&
848 (unsigned)MemVT.getSimpleVT() < sizeof(TruncStoreActions[0])*4 &&
849 "Table isn't big enough!");
850 TruncStoreActions[ValVT.getSimpleVT()] &= ~(uint64_t(3UL) <<
851 MemVT.getSimpleVT()*2);
852 TruncStoreActions[ValVT.getSimpleVT()] |= (uint64_t)Action <<
853 MemVT.getSimpleVT()*2;
839854 }
840855
841856 /// setIndexedLoadAction - Indicate that the specified indexed load does or
842857 /// does not work with the with specified type and indicate what to do abort
843858 /// it. NOTE: All indexed mode loads are initialized to Expand in
844859 /// TargetLowering.cpp
845 void setIndexedLoadAction(unsigned IdxMode, MVT::ValueType VT,
860 void setIndexedLoadAction(unsigned IdxMode, MVT VT,
846861 LegalizeAction Action) {
847 assert(VT < sizeof(IndexedModeActions[0])*4 && IdxMode <
848 array_lengthof(IndexedModeActions[0]) &&
862 assert((unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[0])*4 &&
863 IdxMode < array_lengthof(IndexedModeActions[0]) &&
849864 "Table isn't big enough!");
850 IndexedModeActions[0][IdxMode] &= ~(uint64_t(3UL) << VT*2);
851 IndexedModeActions[0][IdxMode] |= (uint64_t)Action << VT*2;
865 IndexedModeActions[0][IdxMode] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2);
866 IndexedModeActions[0][IdxMode] |= (uint64_t)Action << VT.getSimpleVT()*2;
852867 }
853868
854869 /// setIndexedStoreAction - Indicate that the specified indexed store does or
855870 /// does not work with the with specified type and indicate what to do about
856871 /// it. NOTE: All indexed mode stores are initialized to Expand in
857872 /// TargetLowering.cpp
858 void setIndexedStoreAction(unsigned IdxMode, MVT::ValueType VT,
873 void setIndexedStoreAction(unsigned IdxMode, MVT VT,
859874 LegalizeAction Action) {
860 assert(VT < sizeof(IndexedModeActions[1][0])*4 &&
875 assert((unsigned)VT.getSimpleVT() < sizeof(IndexedModeActions[1][0])*4 &&
861876 IdxMode < array_lengthof(IndexedModeActions[1]) &&
862877 "Table isn't big enough!");
863 IndexedModeActions[1][IdxMode] &= ~(uint64_t(3UL) << VT*2);
864 IndexedModeActions[1][IdxMode] |= (uint64_t)Action << VT*2;
878 IndexedModeActions[1][IdxMode] &= ~(uint64_t(3UL) << VT.getSimpleVT()*2);
879 IndexedModeActions[1][IdxMode] |= (uint64_t)Action << VT.getSimpleVT()*2;
865880 }
866881
867882 /// setConvertAction - Indicate that the specified conversion does or does
868883 /// not work with the with specified type and indicate what to do about it.
869 void setConvertAction(MVT::ValueType FromVT, MVT::ValueType ToVT,
884 void setConvertAction(MVT FromVT, MVT ToVT,
870885 LegalizeAction Action) {
871 assert(FromVT < array_lengthof(ConvertActions) &&
872 ToVT < sizeof(ConvertActions[0])*4 && "Table isn't big enough!");
873 ConvertActions[FromVT] &= ~(uint64_t(3UL) << ToVT*2);
874 ConvertActions[FromVT] |= (uint64_t)Action << ToVT*2;
886 assert((unsigned)FromVT.getSimpleVT() < array_lengthof(ConvertActions) &&
887 (unsigned)ToVT.getSimpleVT() < sizeof(ConvertActions[0])*4 &&
888 "Table isn't big enough!");
889 ConvertActions[FromVT.getSimpleVT()] &= ~(uint64_t(3UL) <<
890 ToVT.getSimpleVT()*2);
891 ConvertActions[FromVT.getSimpleVT()] |= (uint64_t)Action <<
892 ToVT.getSimpleVT()*2;
875893 }
876894
877895 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the
878896 /// promotion code defaults to trying a larger integer/fp until it can find
879897 /// one that works. If that default is insufficient, this method can be used
880898 /// by the target to override the default.
881 void AddPromotedToType(unsigned Opc, MVT::ValueType OrigVT,
882 MVT::ValueType DestVT) {
899 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
883900 PromoteToType[std::make_pair(Opc, OrigVT)] = DestVT;
884901 }
885902
11201137 Value *CallOperandVal;
11211138
11221139 /// ConstraintVT - The ValueType for the operand value.
1123 MVT::ValueType ConstraintVT;
1140 MVT ConstraintVT;
11241141
11251142 AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
11261143 : InlineAsm::ConstraintInfo(info),
11471164 /// This should only be used for C_RegisterClass constraints.
11481165 virtual std::vector
11491166 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1150 MVT::ValueType VT) const;
1167 MVT VT) const;
11511168
11521169 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g.
11531170 /// {edx}), return the register number and the register class for the
11611178 /// this returns a register number of 0 and a null register class pointer..
11621179 virtual std::pair
11631180 getRegForInlineAsmConstraint(const std::string &Constraint,
1164 MVT::ValueType VT) const;
1181 MVT VT) const;
11651182
11661183 /// LowerXConstraint - try to replace an X constraint, which matches anything,
11671184 /// with another that has more specific requirements based on the type of the
11681185 /// corresponding operand. This returns null if there is no replacement to
11691186 /// make.
1170 virtual const char *LowerXConstraint(MVT::ValueType ConstraintVT) const;
1187 virtual const char *LowerXConstraint(MVT ConstraintVT) const;
11711188
11721189 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
11731190 /// vector. If it is invalid, don't add anything to Ops.
12191236 return false;
12201237 }
12211238
1222 virtual bool isTruncateFree(MVT::ValueType VT1, MVT::ValueType VT2) const {
1239 virtual bool isTruncateFree(MVT VT1, MVT VT2) const {
12231240 return false;
12241241 }
12251242
12701287
12711288 /// PointerTy - The type to use for pointers, usually i32 or i64.
12721289 ///
1273 MVT::ValueType PointerTy;
1290 MVT PointerTy;
12741291
12751292 /// UsesGlobalOffsetTable - True if this target uses a GOT for PIC codegen.
12761293 ///
12781295
12791296 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever
12801297 /// PointerTy is.
1281 MVT::ValueType ShiftAmountTy;
1298 MVT ShiftAmountTy;
12821299
12831300 OutOfRangeShiftAmount ShiftAmtHandling;
12841301
13511368 /// each ValueType the target supports natively.
13521369 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
13531370 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1354 MVT::ValueType RegisterTypeForVT[MVT::LAST_VALUETYPE];
1371 MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
13551372
13561373 /// TransformToType - For any value types we are promoting or expanding, this
13571374 /// contains the value type that we are changing to. For Expanded types, this
13581375 /// contains one step of the expand (e.g. i64 -> i32), even if there are
13591376 /// multiple steps required (e.g. i64 -> i16). For types natively supported
13601377 /// by the system, this holds the same type (e.g. i32 -> i32).
1361 MVT::ValueType TransformToType[MVT::LAST_VALUETYPE];
1378 MVT TransformToType[MVT::LAST_VALUETYPE];
13621379
13631380 // Defines the capacity of the TargetLowering::OpActions table
13641381 static const int OpActionsCapacity = 176;
13951412
13961413 std::vector LegalFPImmediates;
13971414
1398 std::vector
1399 TargetRegisterClass*> > AvailableRegClasses;
1415 std::vector TargetRegisterClass*> > AvailableRegClasses;
14001416
14011417 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would
14021418 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(),
14101426 ///
14111427 /// Targets add entries to this map with AddPromotedToType(..), clients access
14121428 /// this with getTypeToPromoteTo(..).
1413 std::map::ValueType>, MVT::ValueType> PromoteToType;
1429 std::map>, MVT> PromoteToType;
14141430
14151431 /// LibcallRoutineNames - Stores the name each libcall.
14161432 ///
6060 typedef const unsigned* iterator;
6161 typedef const unsigned* const_iterator;
6262
63 typedef const MVT::ValueType* vt_iterator;
63 typedef const MVT* vt_iterator;
6464 typedef const TargetRegisterClass* const * sc_iterator;
6565 private:
6666 unsigned ID;
7575 const iterator RegsBegin, RegsEnd;
7676 public:
7777 TargetRegisterClass(unsigned id,
78 const MVT::ValueType *vts,
78 const MVT *vts,
7979 const TargetRegisterClass * const *subcs,
8080 const TargetRegisterClass * const *supcs,
8181 const TargetRegisterClass * const *subregcs,
117117
118118 /// hasType - return true if this TargetRegisterClass has the ValueType vt.
119119 ///
120 bool hasType(MVT::ValueType vt) const {
120 bool hasType(MVT vt) const {
121121 for(int i = 0; VTs[i] != MVT::Other; ++i)
122122 if (VTs[i] == vt)
123123 return true;
323323 /// register of the given type. If type is MVT::Other, then just return any
324324 /// register class the register belongs to.
325325 const TargetRegisterClass *getPhysicalRegisterRegClass(unsigned Reg,
326 MVT::ValueType VT = MVT::Other) const;
326 MVT VT = MVT::Other) const;
327327
328328 /// getAllocatableSet - Returns a bitset indexed by register number
329329 /// indicating if a register is allocatable or not. If a register class is
3131 // HandleByVal - Allocate a stack slot large enough to pass an argument by
3232 // value. The size and alignment information of the argument is encoded in its
3333 // parameter attribute.
34 void CCState::HandleByVal(unsigned ValNo, MVT::ValueType ValVT,
35 MVT::ValueType LocVT, CCValAssign::LocInfo LocInfo,
34 void CCState::HandleByVal(unsigned ValNo, MVT ValVT,
35 MVT LocVT, CCValAssign::LocInfo LocInfo,
3636 int MinSize, int MinAlign,
3737 ISD::ArgFlagsTy ArgFlags) {
3838 unsigned Align = ArgFlags.getByValAlign();
6161 unsigned NumArgs = TheArgs->getNumValues()-1;
6262
6363 for (unsigned i = 0; i != NumArgs; ++i) {
64 MVT::ValueType ArgVT = TheArgs->getValueType(i);
64 MVT ArgVT = TheArgs->getValueType(i);
6565 ISD::ArgFlagsTy ArgFlags =
6666 cast(TheArgs->getOperand(3+i))->getArgFlags();
6767 if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) {
6868 cerr << "Formal argument #" << i << " has unhandled type "
69 << MVT::getValueTypeString(ArgVT) << "\n";
69 << ArgVT.getMVTString() << "\n";
7070 abort();
7171 }
7272 }
7777 void CCState::AnalyzeReturn(SDNode *TheRet, CCAssignFn Fn) {
7878 // Determine which register each value should be copied into.
7979 for (unsigned i = 0, e = TheRet->getNumOperands() / 2; i != e; ++i) {
80 MVT::ValueType VT = TheRet->getOperand(i*2+1).getValueType();
80 MVT VT = TheRet->getOperand(i*2+1).getValueType();
8181 ISD::ArgFlagsTy ArgFlags =
8282 cast(TheRet->getOperand(i*2+2))->getArgFlags();
8383 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)){
8484 cerr << "Return operand #" << i << " has unhandled type "
85 << MVT::getValueTypeString(VT) << "\n";
85 << VT.getMVTString() << "\n";
8686 abort();
8787 }
8888 }
9494 void CCState::AnalyzeCallOperands(SDNode *TheCall, CCAssignFn Fn) {
9595 unsigned NumOps = (TheCall->getNumOperands() - 5) / 2;
9696 for (unsigned i = 0; i != NumOps; ++i) {
97 MVT::ValueType ArgVT = TheCall->getOperand(5+2*i).getValueType();
97 MVT ArgVT = TheCall->getOperand(5+2*i).getValueType();
9898 ISD::ArgFlagsTy ArgFlags =
9999 cast(TheCall->getOperand(5+2*i+1))->getArgFlags();
100100 if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) {
101101 cerr << "Call operand #" << i << " has unhandled type "
102 << MVT::getValueTypeString(ArgVT) << "\n";
102 << ArgVT.getMVTString() << "\n";
103103 abort();
104104 }
105105 }
109109 /// incorporating info about the passed values into this state.
110110 void CCState::AnalyzeCallResult(SDNode *TheCall, CCAssignFn Fn) {
111111 for (unsigned i = 0, e = TheCall->getNumValues() - 1; i != e; ++i) {
112 MVT::ValueType VT = TheCall->getValueType(i);
112 MVT VT = TheCall->getValueType(i);
113113 if (Fn(i, VT, VT, CCValAssign::Full, ISD::ArgFlagsTy(), *this)) {
114114 cerr << "Call result #" << i << " has unhandled type "
115 << MVT::getValueTypeString(VT) << "\n";
115 << VT.getMVTString() << "\n";
116116 abort();
117117 }
118118 }
214214 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2,
215215 SDOperand N3, ISD::CondCode CC,
216216 bool NotExtCompare = false);
217 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
217 SDOperand SimplifySetCC(MVT VT, SDOperand N0, SDOperand N1,
218218 ISD::CondCode Cond, bool foldBooleans = true);
219219 SDOperand SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
220220 unsigned HiOp);
221 SDOperand CombineConsecutiveLoads(SDNode *N, MVT::ValueType VT);
222 SDOperand ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT::ValueType);
221 SDOperand CombineConsecutiveLoads(SDNode *N, MVT VT);
222 SDOperand ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT);
223223 SDOperand BuildSDIV(SDNode *N);
224224 SDOperand BuildUDIV(SDNode *N);
225225 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS);
481481 }
482482
483483 SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){
484 MVT::ValueType VT = N0.getValueType();
484 MVT VT = N0.getValueType();
485485 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use
486486 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
487487 if (N0.getOpcode() == Opc && isa(N0.getOperand(1))) {
886886
887887 static
888888 SDOperand combineShlAddConstant(SDOperand N0, SDOperand N1, SelectionDAG &DAG) {
889 MVT::ValueType VT = N0.getValueType();
889 MVT VT = N0.getValueType();
890890 SDOperand N00 = N0.getOperand(0);
891891 SDOperand N01 = N0.getOperand(1);
892892 ConstantSDNode *N01C = dyn_cast(N01);
903903 static
904904 SDOperand combineSelectAndUse(SDNode *N, SDOperand Slct, SDOperand OtherOp,
905905 SelectionDAG &DAG) {
906 MVT::ValueType VT = N->getValueType(0);
906 MVT VT = N->getValueType(0);
907907 unsigned Opc = N->getOpcode();
908908 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
909909 SDOperand LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
929929 cast(RHS)->isNullValue()) {
930930 std::swap(LHS, RHS);
931931 SDOperand Op0 = Slct.getOperand(0);
932 bool isInt = MVT::isInteger(isSlctCC ? Op0.getValueType()
933 : Op0.getOperand(0).getValueType());
932 bool isInt = (isSlctCC ? Op0.getValueType() :
933 Op0.getOperand(0).getValueType()).isInteger();
934934 CC = ISD::getSetCCInverse(CC, isInt);
935935 DoXform = true;
936936 InvCC = true;
955955 SDOperand N1 = N->getOperand(1);
956956 ConstantSDNode *N0C = dyn_cast(N0);
957957 ConstantSDNode *N1C = dyn_cast(N1);
958 MVT::ValueType VT = N0.getValueType();
958 MVT VT = N0.getValueType();
959959
960960 // fold vector ops
961 if (MVT::isVector(VT)) {
961 if (VT.isVector()) {
962962 SDOperand FoldedVOp = SimplifyVBinOp(N);
963963 if (FoldedVOp.Val) return FoldedVOp;
964964 }
10001000 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
10011001 return N1.getOperand(0);
10021002
1003 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0)))
1003 if (!VT.isVector() && SimplifyDemandedBits(SDOperand(N, 0)))
10041004 return SDOperand(N, 0);
10051005
10061006 // fold (a+b) -> (a|b) iff a and b share no bits.
1007 if (MVT::isInteger(VT) && !MVT::isVector(VT)) {
1007 if (VT.isInteger() && !VT.isVector()) {
10081008 APInt LHSZero, LHSOne;
10091009 APInt RHSZero, RHSOne;
1010 APInt Mask = APInt::getAllOnesValue(MVT::getSizeInBits(VT));
1010 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits());
10111011 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
10121012 if (LHSZero.getBoolValue()) {
10131013 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
10481048 SDOperand N1 = N->getOperand(1);
10491049 ConstantSDNode *N0C = dyn_cast(N0);
10501050 ConstantSDNode *N1C = dyn_cast(N1);
1051 MVT::ValueType VT = N0.getValueType();
1051 MVT VT = N0.getValueType();
10521052
10531053 // If the flag result is dead, turn this into an ADD.
10541054 if (N->hasNUsesOfValue(0, 1))
10681068 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
10691069 APInt LHSZero, LHSOne;
10701070 APInt RHSZero, RHSOne;
1071 APInt Mask = APInt::getAllOnesValue(MVT::getSizeInBits(VT));
1071 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits());
10721072 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
10731073 if (LHSZero.getBoolValue()) {
10741074 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
10901090 SDOperand CarryIn = N->getOperand(2);
10911091 ConstantSDNode *N0C = dyn_cast(N0);
10921092 ConstantSDNode *N1C = dyn_cast(N1);
1093 //MVT::ValueType VT = N0.getValueType();
1093 //MVT VT = N0.getValueType();
10941094
10951095 // canonicalize constant to RHS
10961096 if (N0C && !N1C) {
11141114 SDOperand N1 = N->getOperand(1);
11151115 ConstantSDNode *N0C = dyn_cast(N0.Val);
11161116 ConstantSDNode *N1C = dyn_cast(N1.Val);
1117 MVT::ValueType VT = N0.getValueType();
1117 MVT VT = N0.getValueType();
11181118
11191119 // fold vector ops
1120 if (MVT::isVector(VT)) {
1120 if (VT.isVector()) {
11211121 SDOperand FoldedVOp = SimplifyVBinOp(N);
11221122 if (FoldedVOp.Val) return FoldedVOp;
11231123 }
11571157 SDOperand N1 = N->getOperand(1);
11581158 ConstantSDNode *N0C = dyn_cast(N0);
11591159 ConstantSDNode *N1C = dyn_cast(N1);
1160 MVT::ValueType VT = N0.getValueType();
1160 MVT VT = N0.getValueType();
11611161
11621162 // fold vector ops
1163 if (MVT::isVector(VT)) {
1163 if (VT.isVector()) {
11641164 SDOperand FoldedVOp = SimplifyVBinOp(N);
11651165 if (FoldedVOp.Val) return FoldedVOp;
11661166 }
12411241 SDOperand N1 = N->getOperand(1);
12421242 ConstantSDNode *N0C = dyn_cast(N0.Val);
12431243 ConstantSDNode *N1C = dyn_cast(N1.Val);
1244 MVT::ValueType VT = N->getValueType(0);
1244 MVT VT = N->getValueType(0);
12451245
12461246 // fold vector ops
1247 if (MVT::isVector(VT)) {
1247 if (VT.isVector()) {
12481248 SDOperand FoldedVOp = SimplifyVBinOp(N);
12491249 if (FoldedVOp.Val) return FoldedVOp;
12501250 }
12601260 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0);
12611261 // If we know the sign bits of both operands are zero, strength reduce to a
12621262 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2
1263 if (!MVT::isVector(VT)) {
1263 if (!VT.isVector()) {
12641264 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
12651265 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
12661266 }
12771277 unsigned lg2 = Log2_64(abs2);
12781278 // Splat the sign bit into the register
12791279 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0,
1280 DAG.getConstant(MVT::getSizeInBits(VT)-1,
1280 DAG.getConstant(VT.getSizeInBits()-1,
12811281 TLI.getShiftAmountTy()));
12821282 AddToWorkList(SGN.Val);
12831283 // Add (N0 < 0) ? abs2 - 1 : 0;
12841284 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN,
1285 DAG.getConstant(MVT::getSizeInBits(VT)-lg2,
1285 DAG.getConstant(VT.getSizeInBits()-lg2,
12861286 TLI.getShiftAmountTy()));
12871287 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL);
12881288 AddToWorkList(SRL.Val);
13191319 SDOperand N1 = N->getOperand(1);
13201320 ConstantSDNode *N0C = dyn_cast(N0.Val);
13211321 ConstantSDNode *N1C = dyn_cast(N1.Val);
1322 MVT::ValueType VT = N->getValueType(0);
1322 MVT VT = N->getValueType(0);
13231323
13241324 // fold vector ops
1325 if (MVT::isVector(VT)) {
1325 if (VT.isVector()) {
13261326 SDOperand FoldedVOp = SimplifyVBinOp(N);
13271327 if (FoldedVOp.Val) return FoldedVOp;
13281328 }
13391339 if (N1.getOpcode() == ISD::SHL) {
13401340 if (ConstantSDNode *SHC = dyn_cast(N1.getOperand(0))) {
13411341 if (SHC->getAPIntValue().isPowerOf2()) {
1342 MVT::ValueType ADDVT = N1.getOperand(1).getValueType();
1342 MVT ADDVT = N1.getOperand(1).getValueType();
13431343 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1),
13441344 DAG.getConstant(SHC->getAPIntValue()
13451345 .logBase2(),
13701370 SDOperand N1 = N->getOperand(1);
13711371 ConstantSDNode *N0C = dyn_cast(N0);
13721372 ConstantSDNode *N1C = dyn_cast(N1);
1373 MVT::ValueType VT = N->getValueType(0);
1373 MVT VT = N->getValueType(0);
13741374
13751375 // fold (srem c1, c2) -> c1%c2
13761376 if (N0C && N1C && !N1C->isNullValue())
13771377 return DAG.getNode(ISD::SREM, VT, N0, N1);
13781378 // If we know the sign bits of both operands are zero, strength reduce to a
13791379 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15
1380 if (!MVT::isVector(VT)) {
1380 if (!VT.isVector()) {
13811381 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0))
13821382 return DAG.getNode(ISD::UREM, VT, N0, N1);
13831383 }
14111411 SDOperand N1 = N->getOperand(1);
14121412 ConstantSDNode *N0C = dyn_cast(N0);
14131413 ConstantSDNode *N1C = dyn_cast(N1);
1414 MVT::ValueType VT = N->getValueType(0);
1414 MVT VT = N->getValueType(0);
14151415
14161416 // fold (urem c1, c2) -> c1%c2
14171417 if (N0C && N1C && !N1C->isNullValue())
14261426 if (SHC->getAPIntValue().isPowerOf2()) {
14271427 SDOperand Add =
14281428 DAG.getNode(ISD::ADD, VT, N1,
1429 DAG.getConstant(APInt::getAllOnesValue(MVT::getSizeInBits(VT)),
1429 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()),
14301430 VT));
14311431 AddToWorkList(Add.Val);
14321432 return DAG.getNode(ISD::AND, VT, N0, Add);
14611461 SDOperand N0 = N->getOperand(0);
14621462 SDOperand N1 = N->getOperand(1);
14631463 ConstantSDNode *N1C = dyn_cast(N1);
1464 MVT::ValueType VT = N->getValueType(0);
1464 MVT VT = N->getValueType(0);
14651465
14661466 // fold (mulhs x, 0) -> 0
14671467 if (N1C && N1C->isNullValue())
14691469 // fold (mulhs x, 1) -> (sra x, size(x)-1)
14701470 if (N1C && N1C->getAPIntValue() == 1)
14711471 return DAG.getNode(ISD::SRA, N0.getValueType(), N0,
1472 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1,
1472 DAG.getConstant(N0.getValueType().getSizeInBits()-1,
14731473 TLI.getShiftAmountTy()));
14741474 // fold (mulhs x, undef) -> 0
14751475 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
14821482 SDOperand N0 = N->getOperand(0);
14831483 SDOperand N1 = N->getOperand(1);
14841484 ConstantSDNode *N1C = dyn_cast(N1);
1485 MVT::ValueType VT = N->getValueType(0);
1485 MVT VT = N->getValueType(0);
14861486
14871487 // fold (mulhu x, 0) -> 0
14881488 if (N1C && N1C->isNullValue())
15821582 /// two operands of the same opcode, try to simplify it.
15831583 SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
15841584 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1);
1585 MVT::ValueType VT = N0.getValueType();
1585 MVT VT = N0.getValueType();
15861586 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
15871587
15881588 // For each of OP in AND/OR/XOR:
16231623 SDOperand LL, LR, RL, RR, CC0, CC1;
16241624 ConstantSDNode *N0C = dyn_cast(N0);
16251625 ConstantSDNode *N1C = dyn_cast(N1);
1626 MVT::ValueType VT = N1.getValueType();
1627 unsigned BitWidth = MVT::getSizeInBits(VT);
1626 MVT VT = N1.getValueType();
1627 unsigned BitWidth = VT.getSizeInBits();
16281628
16291629 // fold vector ops
1630 if (MVT::isVector(VT)) {
1630 if (VT.isVector()) {
16311631 SDOperand FoldedVOp = SimplifyVBinOp(N);
16321632 if (FoldedVOp.Val) return FoldedVOp;
16331633 }
16821682 ISD::CondCode Op1 = cast(CC1)->get();
16831683
16841684 if (LR == RR && isa(LR) && Op0 == Op1 &&
1685 MVT::isInteger(LL.getValueType())) {
1685 LL.getValueType().isInteger()) {
16861686 // fold (X == 0) & (Y == 0) -> (X|Y == 0)
16871687 if (cast(LR)->isNullValue() && Op1 == ISD::SETEQ) {
16881688 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
17081708 std::swap(RL, RR);
17091709 }
17101710 if (LL == RL && LR == RR) {
1711 bool isInteger = MVT::isInteger(LL.getValueType());
1711 bool isInteger = LL.getValueType().isInteger();
17121712 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
17131713 if (Result != ISD::SETCC_INVALID)
17141714 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
17231723
17241724 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
17251725 // fold (and (sra)) -> (and (srl)) when possible.
1726 if (!MVT::isVector(VT) &&
1726 if (!VT.isVector() &&
17271727 SimplifyDemandedBits(SDOperand(N, 0)))
17281728 return SDOperand(N, 0);
17291729 // fold (zext_inreg (extload x)) -> (zextload x)
17301730 if (ISD::isEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val)) {
17311731 LoadSDNode *LN0 = cast(N0);
1732 MVT::ValueType EVT = LN0->getMemoryVT();
1732 MVT EVT = LN0->getMemoryVT();
17331733 // If we zero all the possible extended bits, then we can turn this into
17341734 // a zextload if we are running before legalize or the operation is legal.
17351735 unsigned BitWidth = N1.getValueSizeInBits();
17361736 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
1737 BitWidth - MVT::getSizeInBits(EVT))) &&
1737 BitWidth - EVT.getSizeInBits())) &&
17381738 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
17391739 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
17401740 LN0->getBasePtr(), LN0->getSrcValue(),
17501750 if (ISD::isSEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
17511751 N0.hasOneUse()) {
17521752 LoadSDNode *LN0 = cast(N0);
1753 MVT::ValueType EVT = LN0->getMemoryVT();
1753 MVT EVT = LN0->getMemoryVT();
17541754 // If we zero all the possible extended bits, then we can turn this into
17551755 // a zextload if we are running before legalize or the operation is legal.
17561756 unsigned BitWidth = N1.getValueSizeInBits();
17571757 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth,
1758 BitWidth - MVT::getSizeInBits(EVT))) &&
1758 BitWidth - EVT.getSizeInBits())) &&
17591759 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
17601760 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
17611761 LN0->getBasePtr(), LN0->getSrcValue(),
17741774 LoadSDNode *LN0 = cast(N0);
17751775 if (LN0->getExtensionType() != ISD::SEXTLOAD &&
17761776 LN0->isUnindexed() && N0.hasOneUse()) {
1777 MVT::ValueType EVT, LoadedVT;
1777 MVT EVT, LoadedVT;
17781778 if (N1C->getAPIntValue() == 255)
17791779 EVT = MVT::i8;
17801780 else if (N1C->getAPIntValue() == 65535)
17871787 LoadedVT = LN0->getMemoryVT();
17881788 if (EVT != MVT::Other && LoadedVT > EVT &&
17891789 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
1790 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
1790 MVT PtrType = N0.getOperand(1).getValueType();
17911791 // For big endian targets, we need to add an offset to the pointer to
17921792 // load the correct bytes. For little endian systems, we merely need to
17931793 // read fewer bytes from the same pointer.
1794 unsigned LVTStoreBytes = MVT::getStoreSizeInBits(LoadedVT)/8;
1795 unsigned EVTStoreBytes = MVT::getStoreSizeInBits(EVT)/8;
1794 unsigned LVTStoreBytes = LoadedVT.getStoreSizeInBits()/8;
1795 unsigned EVTStoreBytes = EVT.getStoreSizeInBits()/8;
17961796 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
17971797 unsigned Alignment = LN0->getAlignment();
17981798 SDOperand NewPtr = LN0->getBasePtr();
18221822 SDOperand LL, LR, RL, RR, CC0, CC1;
18231823 ConstantSDNode *N0C = dyn_cast(N0);
18241824 ConstantSDNode *N1C = dyn_cast(N1);
1825 MVT::ValueType VT = N1.getValueType();
1825 MVT VT = N1.getValueType();
18261826
18271827 // fold vector ops
1828 if (MVT::isVector(VT)) {
1828 if (VT.isVector()) {
18291829 SDOperand FoldedVOp = SimplifyVBinOp(N);
18301830 if (FoldedVOp.Val) return FoldedVOp;
18311831 }
18671867 ISD::CondCode Op1 = cast(CC1)->get();
18681868
18691869 if (LR == RR && isa(LR) && Op0 == Op1 &&
1870 MVT::isInteger(LL.getValueType())) {
1870 LL.getValueType().isInteger()) {
18711871 // fold (X != 0) | (Y != 0) -> (X|Y != 0)
18721872 // fold (X < 0) | (Y < 0) -> (X|Y < 0)
18731873 if (cast(LR)->isNullValue() &&
18911891 std::swap(RL, RR);
18921892 }
18931893 if (LL == RL && LR == RR) {
1894 bool isInteger = MVT::isInteger(LL.getValueType());
1894 bool isInteger = LL.getValueType().isInteger();
18951895 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
18961896 if (Result != ISD::SETCC_INVALID)
18971897 return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
19581958 // a rot[lr].
19591959 SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) {
19601960 // Must be a legal type. Expanded an promoted things won't work with rotates.
1961 MVT::ValueType VT = LHS.getValueType();
1961 MVT VT = LHS.getValueType();
19621962 if (!TLI.isTypeLegal(VT)) return 0;
19631963
19641964 // The target must have at least one rotate flavor.
19901990 std::swap(LHSMask , RHSMask );
19911991 }
19921992
1993 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1993 unsigned OpSizeInBits = VT.getSizeInBits();
19941994 SDOperand LHSShiftArg = LHSShift.getOperand(0);
19951995 SDOperand LHSShiftAmt = LHSShift.getOperand(1);
19961996 SDOperand RHSShiftAmt = RHSShift.getOperand(1);
21142114 SDOperand LHS, RHS, CC;
21152115 ConstantSDNode *N0C = dyn_cast(N0);
21162116 ConstantSDNode *N1C = dyn_cast(N1);
2117 MVT::ValueType VT = N0.getValueType();
2117 MVT VT = N0.getValueType();
21182118
21192119 // fold vector ops
2120 if (MVT::isVector(VT)) {
2120 if (VT.isVector()) {
21212121 SDOperand FoldedVOp = SimplifyVBinOp(N);
21222122 if (FoldedVOp.Val) return FoldedVOp;
21232123 }
21452145 return RXOR;
21462146 // fold !(x cc y) -> (x !cc y)
21472147 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
2148 bool isInt = MVT::isInteger(LHS.getValueType());
2148 bool isInt = LHS.getValueType().isInteger();
21492149 ISD::CondCode NotCC = ISD::getSetCCInverse(cast(CC)->get(),
21502150 isInt);
21512151 if (N0.getOpcode() == ISD::SETCC)
22042204 }
22052205 // fold (xor x, x) -> 0
22062206 if (N0 == N1) {
2207 if (!MVT::isVector(VT)) {
2207 if (!VT.isVector()) {
22082208 return DAG.getConstant(0, VT);
22092209 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
22102210 // Produce a vector of zeros.
2211 SDOperand El = DAG.getConstant(0, MVT::getVectorElementType(VT));
2212 std::vector Ops(MVT::getVectorNumElements(VT), El);
2211 SDOperand El = DAG.getConstant(0, VT.getVectorElementType());
2212 std::vector Ops(VT.getVectorNumElements(), El);
22132213 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
22142214 }
22152215 }
22212221 }
22222222
22232223 // Simplify the expression using non-local knowledge.
2224 if (!MVT::isVector(VT) &&
2224 if (!VT.isVector() &&
22252225 SimplifyDemandedBits(SDOperand(N, 0)))
22262226 return SDOperand(N, 0);
22272227
22732273 !isa(BinOpLHSVal->getOperand(1)))
22742274 return SDOperand();
22752275
2276 MVT::ValueType VT = N->getValueType(0);
2276 MVT VT = N->getValueType(0);
22772277
22782278 // If this is a signed shift right, and the high bit is modified
22792279 // by the logical operation, do not perform the transformation.
23042304 SDOperand N1 = N->getOperand(1);
23052305 ConstantSDNode *N0C = dyn_cast(N0);
23062306 ConstantSDNode *N1C = dyn_cast(N1);
2307 MVT::ValueType VT = N0.getValueType();
2308 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
2307 MVT VT = N0.getValueType();
2308 unsigned OpSizeInBits = VT.getSizeInBits();
23092309
23102310 // fold (shl c1, c2) -> c1<
23112311 if (N0C && N1C)
23212321 return N0;
23222322 // if (shl x, c) is known to be zero, return 0
23232323 if (DAG.MaskedValueIsZero(SDOperand(N, 0),
2324 APInt::getAllOnesValue(MVT::getSizeInBits(VT))))
2324 APInt::getAllOnesValue(VT.getSizeInBits())))
23252325 return DAG.getConstant(0, VT);
23262326 if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
23272327 return SDOperand(N, 0);
23632363 SDOperand N1 = N->getOperand(1);
23642364 ConstantSDNode *N0C = dyn_cast(N0);
23652365 ConstantSDNode *N1C = dyn_cast(N1);
2366 MVT::ValueType VT = N0.getValueType();
2366 MVT VT = N0.getValueType();
23672367
23682368 // fold (sra c1, c2) -> c1>>c2
23692369 if (N0C && N1C)
23752375 if (N0C && N0C->isAllOnesValue())
23762376 return N0;
23772377 // fold (sra x, c >= size(x)) -> undef
2378 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT))
2378 if (N1C && N1C->getValue() >= VT.getSizeInBits())
23792379 return DAG.getNode(ISD::UNDEF, VT);
23802380 // fold (sra x, 0) -> x
23812381 if (N1C && N1C->isNullValue())
23832383 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports
23842384 // sext_inreg.
23852385 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
2386 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue();
2387 MVT::ValueType EVT;
2386 unsigned LowBits = VT.getSizeInBits() - (unsigned)N1C->getValue();
2387 MVT EVT;
23882388 switch (LowBits) {
23892389 default: EVT = MVT::Other; break;
23902390 case 1: EVT = MVT::i1; break;
24012401 if (N1C && N0.getOpcode() == ISD::SRA) {
24022402 if (ConstantSDNode *C1 = dyn_cast(N0.getOperand(1))) {
24032403 unsigned Sum = N1C->getValue() + C1->getValue();
2404 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1;
2404 if (Sum >= VT.getSizeInBits()) Sum = VT.getSizeInBits()-1;
24052405 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0),
24062406 DAG.getConstant(Sum, N1C->getValueType(0)));
24072407 }
24172417 const ConstantSDNode *N01C = dyn_cast(N0.getOperand(1));
24182418 if (N01C && N1C) {
24192419 // Determine what the truncate's result bitsize and type would be.
2420 unsigned VTValSize = MVT::getSizeInBits(VT);
2421 MVT::ValueType TruncVT = MVT::getIntegerType(VTValSize - N1C->getValue());
2420 unsigned VTValSize = VT.getSizeInBits();
2421 MVT TruncVT =
2422 MVT::getIntegerVT(VTValSize - N1C->getValue());
24222423 // Determine the residual right-shift amount.
24232424 unsigned ShiftAmt = N1C->getValue() - N01C->getValue();
24242425
24572458 SDOperand N1 = N->getOperand(1);
24582459 ConstantSDNode *N0C = dyn_cast(N0);
24592460 ConstantSDNode *N1C = dyn_cast(N1);
2460 MVT::ValueType VT = N0.getValueType();
2461 unsigned OpSizeInBits = MVT::getSizeInBits(VT);
2461 MVT VT = N0.getValueType();
2462 unsigned OpSizeInBits = VT.getSizeInBits();
24622463
24632464 // fold (srl c1, c2) -> c1 >>u c2
24642465 if (N0C && N1C)
24912492 // fold (srl (anyextend x), c) -> (anyextend (srl x, c))
24922493 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
24932494 // Shifting in all undef bits?
2494 MVT::ValueType SmallVT = N0.getOperand(0).getValueType();
2495 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT))
2495 MVT SmallVT = N0.getOperand(0).getValueType();
2496 if (N1C->getValue() >= SmallVT.getSizeInBits())
24962497 return DAG.getNode(ISD::UNDEF, VT);
24972498
24982499 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1);
25022503
25032504 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
25042505 // bit, which is unmodified by sra.
2505 if (N1C && N1C->getValue()+1 == MVT::getSizeInBits(VT)) {
2506 if (N1C && N1C->getValue()+1 == VT.getSizeInBits()) {
25062507 if (N0.getOpcode() == ISD::SRA)
25072508 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1);
25082509 }
25092510
25102511 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit).
25112512 if (N1C && N0.getOpcode() == ISD::CTLZ &&
2512 N1C->getAPIntValue() == Log2_32(MVT::getSizeInBits(VT))) {
2513 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) {
25132514 APInt KnownZero, KnownOne;
2514 APInt Mask = APInt::getAllOnesValue(MVT::getSizeInBits(VT));
2515 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits());
25152516 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne);
25162517
25172518 // If any of the input bits are KnownOne, then the input couldn't be all
25502551
25512552 SDOperand DAGCombiner::visitCTLZ(SDNode *N) {
25522553 SDOperand N0 = N->getOperand(0);
2553 MVT::ValueType VT = N->getValueType(0);
2554 MVT VT = N->getValueType(0);
25542555
25552556 // fold (ctlz c1) -> c2
25562557 if (isa(N0))
25602561
25612562 SDOperand DAGCombiner::visitCTTZ(SDNode *N) {
25622563 SDOperand N0 = N->getOperand(0);
2563 MVT::ValueType VT = N->getValueType(0);
2564 MVT VT = N->getValueType(0);
25642565
25652566 // fold (cttz c1) -> c2
25662567 if (isa(N0))
25702571
25712572 SDOperand DAGCombiner::visitCTPOP(SDNode *N) {
25722573 SDOperand N0 = N->getOperand(0);
2573 MVT::ValueType VT = N->getValueType(0);
2574 MVT VT = N->getValueType(0);
25742575
25752576 // fold (ctpop c1) -> c2
25762577 if (isa(N0))
25852586 ConstantSDNode *N0C = dyn_cast(N0);
25862587 ConstantSDNode *N1C = dyn_cast(N1);
25872588 ConstantSDNode *N2C = dyn_cast(N2);
2588 MVT::ValueType VT = N->getValueType(0);
2589 MVT::ValueType VT0 = N0.getValueType();
2589 MVT VT = N->getValueType(0);
2590 MVT VT0 = N0.getValueType();
25902591
25912592 // fold select C, X, X -> X
25922593 if (N1 == N2)
25982599 if (N0C && N0C->isNullValue())
25992600 return N2;
26002601 // fold select C, 1, X -> C | X
2601 if (MVT::i1 == VT && N1C && N1C->getAPIntValue() == 1)
2602 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1)
26022603 return DAG.getNode(ISD::OR, VT, N0, N2);
26032604 // fold select C, 0, 1 -> ~C
2604 if (MVT::isInteger(VT) && MVT::isInteger(VT0) &&
2605 if (VT.isInteger() && VT0.isInteger() &&
26052606 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) {
26062607 SDOperand XORNode = DAG.getNode(ISD::XOR, VT0, N0, DAG.getConstant(1, VT0));
26072608 if (VT == VT0)
26082609 return XORNode;
26092610 AddToWorkList(XORNode.Val);
2610 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(VT0))
2611 if (VT.getSizeInBits() > VT0.getSizeInBits())
26112612 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode);
26122613 return DAG.getNode(ISD::TRUNCATE, VT, XORNode);
26132614 }
26252626 }
26262627 // fold select C, X, 0 -> C & X
26272628 // FIXME: this should check for C type == X type, not i1?
2628 if (MVT::i1 == VT && N2C && N2C->isNullValue())
2629 if (VT == MVT::i1 && N2C && N2C->isNullValue())
26292630 return DAG.getNode(ISD::AND, VT, N0, N1);
26302631 // fold X ? X : Y --> X ? 1 : Y --> X | Y
2631 if (MVT::i1 == VT && N0 == N1)
2632 if (VT == MVT::i1 && N0 == N1)
26322633 return DAG.getNode(ISD::OR, VT, N0, N2);
26332634 // fold X ? Y : X --> X ? Y : 0 --> X & Y
2634 if (MVT::i1 == VT && N0 == N2)
2635 if (VT == MVT::i1 && N0 == N2)
26352636 return DAG.getNode(ISD::AND, VT, N0, N1);
26362637
26372638 // If we can fold this based on the true/false value, do so.
27652766
27662767 SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
27672768 SDOperand N0 = N->getOperand(0);
2768 MVT::ValueType VT = N->getValueType(0);
2769 MVT VT = N->getValueType(0);
27692770
27702771 // fold (sext c1) -> c1
27712772 if (isa(N0))
27892790 // See if the value being truncated is already sign extended. If so, just
27902791 // eliminate the trunc/sext pair.
27912792 SDOperand Op = N0.getOperand(0);
2792 unsigned OpBits = MVT::getSizeInBits(Op.getValueType());
2793 unsigned MidBits = MVT::getSizeInBits(N0.getValueType());
2794 unsigned DestBits = MVT::getSizeInBits(VT);
2793 unsigned OpBits = Op.getValueType().getSizeInBits();
2794 unsigned MidBits = N0.getValueType().getSizeInBits();
2795 unsigned DestBits = VT.getSizeInBits();
27952796 unsigned NumSignBits = DAG.ComputeNumSignBits(Op);
27962797
27972798 if (OpBits == DestBits) {
28652866 if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) &&
28662867 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) {
28672868 LoadSDNode *LN0 = cast(N0);
2868 MVT::ValueType EVT = LN0->getMemoryVT();
2869 MVT EVT = LN0->getMemoryVT();
28692870 if (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) {
28702871 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
28712872 LN0->getBasePtr(), LN0->getSrcValue(),
28982899
28992900 SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
29002901 SDOperand N0 = N->getOperand(0);
2901 MVT::ValueType VT = N->getValueType(0);
2902 MVT VT = N->getValueType(0);
29022903
29032904 // fold (zext c1) -> c1
29042905 if (isa(N0))
29422943 X = DAG.getNode(ISD::TRUNCATE, VT, X);
29432944 }
29442945 APInt Mask = cast(N0.getOperand(1))->getAPIntValue();
2945 Mask.zext(MVT::getSizeInBits(VT));
2946 Mask.zext(VT.getSizeInBits());
29462947 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
29472948 }
29482949
29882989 if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) &&
29892990 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) {
29902991 LoadSDNode *LN0 = cast(N0);
2991 MVT::ValueType EVT = LN0->getMemoryVT();
2992 MVT EVT = LN0->getMemoryVT();
29922993 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
29932994 LN0->getBasePtr(), LN0->getSrcValue(),
29942995 LN0->getSrcValueOffset(), EVT,
30143015
30153016 SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) {
30163017 SDOperand N0 = N->getOperand(0);
3017 MVT::ValueType VT = N->getValueType(0);
3018 MVT VT = N->getValueType(0);
30183019
30193020 // fold (aext c1) -> c1
30203021 if (isa(N0))
30593060 X = DAG.getNode(ISD::TRUNCATE, VT, X);
30603061 }
30613062 APInt Mask = cast(N0.getOperand(1))->getAPIntValue();
3062 Mask.zext(MVT::getSizeInBits(VT));
3063 Mask.zext(VT.getSizeInBits());
30633064 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT));
30643065 }
30653066
30863087 !ISD::isNON_EXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
30873088 N0.hasOneUse()) {
30883089 LoadSDNode *LN0 = cast(N0);
3089 MVT::ValueType EVT = LN0->getMemoryVT();
3090 MVT EVT = LN0->getMemoryVT();
30903091 SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT,
30913092 LN0->getChain(), LN0->getBasePtr(),
30923093 LN0->getSrcValue(),
31533154 unsigned Opc = N->getOpcode();
31543155 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
31553156 SDOperand N0 = N->getOperand(0);
3156 MVT::ValueType VT = N->getValueType(0);
3157 MVT::ValueType EVT = N->getValueType(0);
3157 MVT VT = N->getValueType(0);
3158 MVT EVT = N->getValueType(0);
31583159
31593160 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then
31603161 // extended to VT.
31653166 return SDOperand();
31663167 }
31673168
3168 unsigned EVTBits = MVT::getSizeInBits(EVT);
3169 unsigned EVTBits = EVT.getSizeInBits();
31693170 unsigned ShAmt = 0;
31703171 bool CombineSRL = false;
31713172 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
31743175 // Is the shift amount a multiple of size of VT?
31753176 if ((ShAmt & (EVTBits-1)) == 0) {
31763177 N0 = N0.getOperand(0);
3177 if (MVT::getSizeInBits(N0.getValueType()) <= EVTBits)
3178 if (N0.getValueType().getSizeInBits() <= EVTBits)
31783179 return SDOperand();
31793180 CombineSRL = true;
31803181 }
31873188 // that it is already zero extended.
31883189 // FIXME: This should be reevaluated.
31893190 VT != MVT::i1) {
3190 assert(MVT::getSizeInBits(N0.getValueType()) > EVTBits &&
3191 assert(N0.getValueType().getSizeInBits() > EVTBits &&
31913192 "Cannot truncate to larger type!");
31923193 LoadSDNode *LN0 = cast(N0);
3193 MVT::ValueType PtrType = N0.getOperand(1).getValueType();
3194 MVT PtrType = N0.getOperand(1).getValueType();
31943195 // For big endian targets, we need to adjust the offset to the pointer to
31953196 // load the correct bytes.
31963197 if (TLI.isBigEndian()) {
3197 unsigned LVTStoreBits = MVT::getStoreSizeInBits(N0.getValueType());
3198 unsigned EVTStoreBits = MVT::getStoreSizeInBits(EVT);
3198 unsigned LVTStoreBits = N0.getValueType().getStoreSizeInBits();
3199 unsigned EVTStoreBits = EVT.getStoreSizeInBits();
31993200 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
32003201 }
32013202 uint64_t PtrOff = ShAmt / 8;
32343235 SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
32353236 SDOperand N0 = N->getOperand(0);
32363237 SDOperand N1 = N->getOperand(1);
3237 MVT::ValueType VT = N->getValueType(0);
3238 MVT::ValueType EVT = cast(N1)->getVT();
3239 unsigned VTBits = MVT::getSizeInBits(VT);
3240 unsigned EVTBits = MVT::getSizeInBits(EVT);
3238 MVT VT = N->getValueType(0);
3239 MVT EVT = cast(N1)->getVT();
3240 unsigned VTBits = VT.getSizeInBits();
3241 unsigned EVTBits = EVT.getSizeInBits();
32413242
32423243 // fold (sext_in_reg c1) -> c1
32433244 if (isa(N0) || N0.getOpcode() == ISD::UNDEF)
32443245 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1);
32453246
32463247 // If the input is already sign extended, just drop the extension.
3247 if (DAG.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1)
3248 if (DAG.ComputeNumSignBits(N0) >= VT.getSizeInBits()-EVTBits+1)
32483249 return N0;
32493250
32503251 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
32733274 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
32743275 if (N0.getOpcode() == ISD::SRL) {
32753276 if (ConstantSDNode *ShAmt = dyn_cast(N0.getOperand(1)))
3276 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) {
3277 if (ShAmt->getValue()+EVTBits <= VT.getSizeInBits()) {
32773278 // We can turn this into an SRA iff the input to the SRL is already sign
32783279 // extended enough.
32793280 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
3280 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits)
3281 if (VT.getSizeInBits()-(ShAmt->getValue()+EVTBits) < InSignBits)
32813282 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1));
32823283 }
32833284 }
33173318
33183319 SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) {
33193320 SDOperand N0 = N->getOperand(0);
3320 MVT::ValueType VT = N->getValueType(0);
3321 MVT VT = N->getValueType(0);
33213322
33223323 // noop truncate
33233324 if (N0.getValueType() == N->getValueType(0))
33483349 // -> trunc y
33493350 SDOperand Shorter =
33503351 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(),
3351 MVT::getSizeInBits(VT)));
3352 VT.getSizeInBits()));
33523353 if (Shorter.Val)
33533354 return DAG.getNode(ISD::TRUNCATE, VT, Shorter);
33543355
33663367
33673368 /// CombineConsecutiveLoads - build_pair (load, load) -> load
33683369 /// if load locations are consecutive.
3369 SDOperand DAGCombiner::CombineConsecutiveLoads(SDNode *N, MVT::ValueType VT) {
3370 SDOperand DAGCombiner::CombineConsecutiveLoads(SDNode *N, MVT VT) {
33703371 assert(N->getOpcode() == ISD::BUILD_PAIR);
33713372
33723373 SDNode *LD1 = getBuildPairElt(N, 0);
33733374 if (!ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse())
33743375 return SDOperand();
3375 MVT::ValueType LD1VT = LD1->getValueType(0);
3376 MVT LD1VT = LD1->getValueType(0);
33763377 SDNode *LD2 = getBuildPairElt(N, 1);
33773378 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
33783379 if (ISD::isNON_EXTLoad(LD2) &&
33793380 LD2->hasOneUse() &&
3380 TLI.isConsecutiveLoad(LD2, LD1, MVT::getSizeInBits(LD1VT)/8, 1, MFI)) {
3381 TLI.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1, MFI)) {
33813382 LoadSDNode *LD = cast(LD1);
33823383 unsigned Align = LD->getAlignment();
33833384 unsigned NewAlign = TLI.getTargetMachine().getTargetData()->
3384 getABITypeAlignment(MVT::getTypeForValueType(VT));
3385 getABITypeAlignment(VT.getTypeForMVT());
33853386 if ((!AfterLegalize || TLI.isTypeLegal(VT)) &&
33863387 TLI.isOperationLegal(ISD::LOAD, VT) && NewAlign <= Align)
33873388 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(),
33933394
33943395 SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) {
33953396 SDOperand N0 = N->getOperand(0);
3396 MVT::ValueType VT = N->getValueType(0);
3397 MVT VT = N->getValueType(0);
33973398
33983399 // If the input is a BUILD_VECTOR with all constant elements, fold this now.
33993400 // Only do this before legalize, since afterward the target may be depending
34013402 // First check to see if this is all constant.
34023403 if (!AfterLegalize &&
34033404 N0.getOpcode() == ISD::BUILD_VECTOR && N0.Val->hasOneUse() &&
3404 MVT::isVector(VT)) {
3405 VT.isVector()) {
34053406 bool isSimple = true;
34063407 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i)
34073408 if (N0.getOperand(i).getOpcode() != ISD::UNDEF &&
34113412 break;
34123413 }
34133414
3414 MVT::ValueType DestEltVT = MVT::getVectorElementType(N->getValueType(0));
3415 assert(!MVT::isVector(DestEltVT) &&
3415 MVT DestEltVT = N->getValueType(0).getVectorElementType();
3416 assert(!DestEltVT.isVector() &&
34163417 "Element type of vector ValueType must not be vector!");
34173418 if (isSimple) {
34183419 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.Val, DestEltVT);
34343435 TLI.isOperationLegal(ISD::LOAD, VT)) {
34353436 LoadSDNode *LN0 = cast(N0);
34363437 unsigned Align = TLI.getTargetMachine().getTargetData()->
3437 getABITypeAlignment(MVT::getTypeForValueType(VT));
3438 getABITypeAlignment(VT.getTypeForMVT());
34383439 unsigned OrigAlign = LN0->getAlignment();
34393440 if (Align <= OrigAlign) {
34403441 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(),
34513452 // Fold bitconvert(fabs(x)) -> and(bitconvert(x), ~signbit)
34523453 // This often reduces constant pool loads.
34533454 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) &&
3454 N0.Val->hasOneUse() && MVT::isInteger(VT) && !MVT::isVector(VT)) {
3455 N0.Val->hasOneUse() && VT.isInteger() && !VT.isVector()) {
34553456 SDOperand NewConv = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
34563457 AddToWorkList(NewConv.Val);
34573458
3458 APInt SignBit = APInt::getSignBit(MVT::getSizeInBits(VT));
3459 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
34593460 if (N0.getOpcode() == ISD::FNEG)
34603461 return DAG.getNode(ISD::XOR, VT, NewConv, DAG.getConstant(SignBit, VT));
34613462 assert(N0.getOpcode() == ISD::FABS);
34673468 // to an fneg or fabs.
34683469 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse() &&
34693470 isa(N0.getOperand(0)) &&
3470 MVT::isInteger(VT) && !MVT::isVector(VT)) {
3471 unsigned OrigXWidth = MVT::getSizeInBits(N0.getOperand(1).getValueType());
3472 SDOperand X = DAG.getNode(ISD::BIT_CONVERT, MVT::getIntegerType(OrigXWidth),
3471 VT.isInteger() && !VT.isVector()) {
3472 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
3473 SDOperand X = DAG.getNode(ISD::BIT_CONVERT,
3474 MVT::getIntegerVT(OrigXWidth),
34733475 N0.getOperand(1));
34743476 AddToWorkList(X.Val);
34753477
34763478 // If X has a different width than the result/lhs, sext it or truncate it.
3477 unsigned VTWidth = MVT::getSizeInBits(VT);
3479 unsigned VTWidth = VT.getSizeInBits();
34783480 if (OrigXWidth < VTWidth) {
34793481 X = DAG.getNode(ISD::SIGN_EXTEND, VT, X);
34803482 AddToWorkList(X.Val);
34883490 AddToWorkList(X.Val);
34893491 }
34903492
3491 APInt SignBit = APInt::getSignBit(MVT::getSizeInBits(VT));
3493 APInt SignBit = APInt::getSignBit(VT.getSizeInBits());
34923494 X = DAG.getNode(ISD::AND, VT, X, DAG.getConstant(SignBit, VT));
34933495 AddToWorkList(X.Val);
34943496
35103512 }
35113513
35123514 SDOperand DAGCombiner::visitBUILD_PAIR(SDNode *N) {
3513 MVT::ValueType VT = N->getValueType(0);
3515 MVT VT = N->getValueType(0);
35143516 return CombineConsecutiveLoads(N, VT);
35153517 }
35163518
35183520 /// node with Con