llvm.org GIT mirror llvm / 83c2d8b
[mips] Mark the `lwupc` instruction as MIPS64 R6 only The "The MIPS64 Instruction Set Reference Manual" [1] states that the `lwupc` is MIPS64 Release 6 only. It should not be supported for 32-bit CPUs. [1] https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00087-2B-MIPS64BIS-AFP-6.06.pdf git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363886 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Atanasyan 2 months ago
7 changed file(s) with 4 addition(s) and 11 deletion(s). Raw diff Collapse all Expand all
148148 class SELNEZ_ENC : SPECIAL_3R_FM<0b00000, 0b110111>;
149149
150150 class LWPC_ENC : PCREL19_FM;
151 class LWUPC_ENC : PCREL19_FM;
152151
153152 class MAX_S_ENC : COP1_3R_FM<0b011101, FIELD_FMT_S>;
154153 class MAX_D_ENC : COP1_3R_FM<0b011101, FIELD_FMT_D>;
324323 class ADDIUPC_DESC : PCREL_DESC_BASE<"addiupc", GPR32Opnd, simm19_lsl2,
325324 II_ADDIUPC>;
326325 class LWPC_DESC: PCREL_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2, II_LWPC>;
327 class LWUPC_DESC: PCREL_DESC_BASE<"lwupc", GPR32Opnd, simm19_lsl2, II_LWUPC>;
328326
329327 class ALIGN_DESC_BASE
330328 Operand ImmOpnd, InstrItinClass itin>
925923 }
926924 def LWPC : R6MMR6Rel, LWPC_ENC, LWPC_DESC, ISA_MIPS32R6;
927925 let AdditionalPredicates = [NotInMicroMips] in {
928 def LWUPC : R6MMR6Rel, LWUPC_ENC, LWUPC_DESC, ISA_MIPS32R6;
929926 def MADDF_S : MADDF_S_ENC, MADDF_S_DESC, ISA_MIPS32R6, HARDFLOAT;
930927 def MADDF_D : MADDF_D_ENC, MADDF_D_DESC, ISA_MIPS32R6, HARDFLOAT;
931928 def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6, HARDFLOAT;
3535 class DMUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011100>;
3636 class DMULU_ENC : SPECIAL_3R_FM<0b00010, 0b011101>;
3737 class LDPC_ENC : PCREL18_FM;
38 class LWUPC_ENC : PCREL19_FM;
3839 class LLD_R6_ENC : SPECIAL3_LL_SC_FM;
3940 class SCD_R6_ENC : SPECIAL3_LL_SC_FM;
4041 class CRC32D_ENC : SPECIAL3_2R_SZ_CRC<3,0>;
7172 class DMUL_R6_DESC : MUL_R6_DESC_BASE<"dmul", GPR64Opnd, II_DMUL, mul>;
7273 class DMULU_DESC : MUL_R6_DESC_BASE<"dmulu", GPR64Opnd, II_DMUL>;
7374 class LDPC_DESC : PCREL_DESC_BASE<"ldpc", GPR64Opnd, simm18_lsl3, II_LDPC>;
75 class LWUPC_DESC : PCREL_DESC_BASE<"lwupc", GPR32Opnd, simm19_lsl2, II_LWUPC>;
7476 class LLD_R6_DESC : LL_R6_DESC_BASE<"lld", GPR64Opnd, mem_simmptr, II_LLD>;
7577 class SCD_R6_DESC : SC_R6_DESC_BASE<"scd", GPR64Opnd, II_SCD>;
7678 class SELEQZ64_DESC : SELEQNE_Z_DESC_BASE<"seleqz", GPR64Opnd>;
146148 def LLD_R6 : LLD_R6_ENC, LLD_R6_DESC, ISA_MIPS64R6;
147149 }
148150 def LDPC: LDPC_ENC, LDPC_DESC, ISA_MIPS64R6;
151 def LWUPC : LWUPC_ENC, LWUPC_DESC, ISA_MIPS64R6;
149152 def SCD_R6 : SCD_R6_ENC, SCD_R6_DESC, ISA_MIPS32R6;
150153 let DecoderNamespace = "Mips32r6_64r6_GP64" in {
151154 def SELEQZ64 : SELEQZ_ENC, SELEQZ64_DESC, ISA_MIPS32R6, GPR_64;
9999 0x04 0x00 0x60 0x41 # CHECK: evp $zero
100100 0xc5 0x10 0x64 0x00 # CHECK: lsa $2, $3, $4, 4
101101 0x43 0x00 0x48 0xec # CHECK: lwpc $2, 268
102 0x43 0x00 0x50 0xec # CHECK: lwupc $2, 268
103102 0x01 0x78 0x08 0x40 # CHECK: mfc0 $8, $15, 1
104103 0xda 0x10 0x64 0x00 # CHECK: mod $2, $3, $4
105104 0xdb 0x10 0x64 0x00 # CHECK: modu $2, $3, $4
191191 0xd8 0x5f 0xff 0xfa # CHECK: beqzc $2, -20
192192 0xe8 0x37 0x96 0xb8 # CHECK: balc 14572260
193193 0xec 0x48 0x00 0x43 # CHECK: lwpc $2, 268
194 0xec 0x50 0x00 0x43 # CHECK: lwupc $2, 268
195194 0xec 0x7e 0xff 0xff # CHECK: auipc $3, -1
196195 0xec 0x7f 0x00 0x38 # CHECK: aluipc $3, 56
197196 0xec 0x80 0x00 0x19 # CHECK: lapc $4, 100
44 # RUN: FileCheck %s < %t1
55
66 .set noat
7 lwupc $2,268 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
78 madd.d $f18,$f19,$f26,$f20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
89 madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
910 msub.d $f10,$f1,$f31,$f18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
3939 # CHECK-FIXUP: lwpc $2, bar # encoding: [0xec,0b01001AAA,A,A]
4040 # CHECK-FIXUP: # fixup A - offset: 0,
4141 # CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC19_S2
42 # CHECK-FIXUP: lwupc $2, bar # encoding: [0xec,0b01010AAA,A,A]
43 # CHECK-FIXUP: # fixup A - offset: 0,
44 # CHECK-FIXUP: value: bar, kind: fixup_MIPS_PC19_S2
4542 #------------------------------------------------------------------------------
4643 # Check that the appropriate relocations were created.
4744 #------------------------------------------------------------------------------
5754 # CHECK-ELF: 0x20 R_MIPS_PCLO16 bar 0x0
5855 # CHECK-ELF: 0x24 R_MIPS_PC19_S2 bar 0x0
5956 # CHECK-ELF: 0x28 R_MIPS_PC19_S2 bar 0x0
60 # CHECK-ELF: 0x2C R_MIPS_PC19_S2 bar 0x0
6157 # CHECK-ELF: ]
6258
6359 addiupc $2,bar
7167 addiu $2, $2, %pcrel_lo(bar)
7268 lapc $2,bar
7369 lwpc $2,bar
74 lwupc $2,bar
125125 lapc $4, 100 # CHECK: lapc $4, 100 # encoding: [0xec,0x80,0x00,0x19]
126126 lsa $2, $3, $4, 3 # CHECK: lsa $2, $3, $4, 3 # encoding: [0x00,0x64,0x10,0x85]
127127 lwpc $2,268 # CHECK: lwpc $2, 268 # encoding: [0xec,0x48,0x00,0x43]
128 lwupc $2,268 # CHECK: lwupc $2, 268 # encoding: [0xec,0x50,0x00,0x43]
129128 mfc0 $8,$15,1 # CHECK: mfc0 $8, $15, 1 # encoding: [0x40,0x08,0x78,0x01]
130129 mod $2,$3,$4 # CHECK: mod $2, $3, $4 # encoding: [0x00,0x64,0x10,0xda]
131130 modu $2,$3,$4 # CHECK: modu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xdb]