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rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45667 91177308-0d34-0410-b5e6-96231b3b80d8 Chris Lattner 11 years ago
26 changed file(s) with 72 addition(s) and 61 deletion(s). Raw diff Collapse all Expand all
4747 const unsigned M_RET_FLAG = 1 << 2;
4848 const unsigned M_BARRIER_FLAG = 1 << 3;
4949 const unsigned M_DELAY_SLOT_FLAG = 1 << 4;
50 const unsigned M_LOAD_FLAG = 1 << 5;
50
51 /// M_SIMPLE_LOAD_FLAG - This flag is set for instructions that are simple loads
52 /// from memory. This should only be set on instructions that load a value from
53 /// memory and return it in their only virtual register definition.
54 const unsigned M_SIMPLE_LOAD_FLAG = 1 << 5;
5155
5256 /// M_MAY_STORE_FLAG - This flag is set to any instruction that could possibly
5357 /// modify memory. Instructions with this flag set are not necessarily simple
183187 /// findTiedToSrcOperand - Returns the operand that is tied to the specified
184188 /// dest operand. Returns -1 if there isn't one.
185189 int findTiedToSrcOperand(unsigned OpNum) const;
190
191
192 /// isSimpleLoad - Return true for instructions that are simple loads from
193 /// memory. This should only be set on instructions that load a value from
194 /// memory and return it in their only virtual register definition.
195 /// Instructions that return a value loaded from memory and then modified in
196 /// some way should not return true for this.
197 bool isSimpleLoad() const {
198 return Flags & M_SIMPLE_LOAD_FLAG;
199 }
200
186201 };
187202
188203
277292
278293 bool isCall(MachineOpCode Opcode) const {
279294 return get(Opcode).Flags & M_CALL_FLAG;
280 }
281 bool isLoad(MachineOpCode Opcode) const {
282 return get(Opcode).Flags & M_LOAD_FLAG;
283295 }
284296
285297 /// mayStore - Return true if this instruction could possibly modify memory.
352352 const TargetInstrDescriptor &TID = TII->get(I->getOpcode());
353353 if (TID.Flags & M_CALL_FLAG)
354354 Time += 10;
355 else if (TID.Flags & (M_LOAD_FLAG|M_MAY_STORE_FLAG))
355 else if (TID.isSimpleLoad() || (TID.Flags & M_MAY_STORE_FLAG))
356356 Time += 2;
357357 else
358358 ++Time;
617617 const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
618618 if ((TID->Flags & M_IMPLICIT_DEF_FLAG) ||
619619 tii_->isTriviallyReMaterializable(MI)) {
620 isLoad = TID->Flags & M_LOAD_FLAG;
620 isLoad = TID->isSimpleLoad();
621621 return true;
622622 }
623623
12251225 int LdSlot = 0;
12261226 bool isLoadSS = DefIsReMat && tii_->isLoadFromStackSlot(ReMatDefMI, LdSlot);
12271227 bool isLoad = isLoadSS ||
1228 (DefIsReMat && (ReMatDefMI->getInstrDescriptor()->Flags & M_LOAD_FLAG));
1228 (DefIsReMat && (ReMatDefMI->getInstrDescriptor()->isSimpleLoad()));
12291229 bool IsFirstRange = true;
12301230 for (LiveInterval::Ranges::const_iterator
12311231 I = li.ranges.begin(), E = li.ranges.end(); I != E; ++I) {
13071307 int LdSlot = 0;
13081308 bool isLoadSS = DefIsReMat && tii_->isLoadFromStackSlot(ReMatDefMI, LdSlot);
13091309 bool isLoad = isLoadSS ||
1310 (DefIsReMat && (ReMatDefMI->getInstrDescriptor()->Flags & M_LOAD_FLAG));
1310 (DefIsReMat && ReMatDefMI->getInstrDescriptor()->isSimpleLoad());
13111311 rewriteInstructionsForSpills(li, TrySplit, I, ReMatOrigDefMI, ReMatDefMI,
13121312 Slot, LdSlot, isLoad, isLoadSS, DefIsReMat,
13131313 CanDelete, vrm, RegInfo, rc, ReMatIds, loopInfo,
14221422 int LdSlot = 0;
14231423 bool isLoadSS = tii_->isLoadFromStackSlot(ReMatDefMI, LdSlot);
14241424 // If the rematerializable def is a load, also try to fold it.
1425 if (isLoadSS ||
1426 (ReMatDefMI->getInstrDescriptor()->Flags & M_LOAD_FLAG))
1425 if (isLoadSS || ReMatDefMI->getInstrDescriptor()->isSimpleLoad())
14271426 Folded = tryFoldMemoryOperand(MI, vrm, ReMatDefMI, index,
14281427 Ops, isLoadSS, LdSlot, VReg);
14291428 }
201201 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
202202 const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
203203 unsigned NumOps = TID->numOperands;
204 bool isLoad = (TID->Flags & M_LOAD_FLAG) != 0;
204 bool isLoad = TID->isSimpleLoad();
205205 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
206206 const MachineOperand &Base = MI->getOperand(2);
207207 const MachineOperand &Offset = MI->getOperand(NumOps-3);
683683 Pseudo, "$cp:\n\tadd$p $dst, pc, $a",
684684 [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
685685
686 let isLoad = 1, AddedComplexity = 10 in {
686 let isSimpleLoad = 1, AddedComplexity = 10 in {
687687 def PICLD : AXI2<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
688688 Pseudo, "${addr:label}:\n\tldr$p $dst, $addr",
689689 [(set GPR:$dst, (load addrmodepc:$addr))]>;
737737 // FIXME: remove when we have a way to marking a MI with these properties.
738738 // FIXME: $dst1 should be a def. But the extra ops must be in the end of the
739739 // operand list.
740 let isLoad = 1, isReturn = 1, isTerminator = 1 in
740 let isSimpleLoad = 1, isReturn = 1, isTerminator = 1 in
741741 def LDM_RET : AXI4<0x0, (outs),
742742 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
743743 LdFrm, "ldm${p}${addr:submode} $addr, $dst1",
801801 //
802802
803803 // Load
804 let isLoad = 1 in {
804 let isSimpleLoad = 1 in {
805805 def LDR : AI2<0x0, (outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
806806 "ldr", " $dst, $addr",
807807 [(set GPR:$dst, (load addrmode2:$addr))]>;
874874 def LDRSB_POST: AI3po<0xD, (outs GPR:$dst, GPR:$base_wb),
875875 (ins GPR:$base,am3offset:$offset), LdFrm,
876876 "ldr", "sb $dst, [$base], $offset", "$base = $base_wb", []>;
877 } // isLoad
877 } // isSimpleLoad
878878
879879 // Store
880880 def STR : AI2<0x0, (outs), (ins GPR:$src, addrmode2:$addr), StFrm,
938938 //
939939
940940 // FIXME: $dst1 should be a def.
941 let isLoad = 1 in
941 let isSimpleLoad = 1 in
942942 def LDM : AXI4<0x0, (outs),
943943 (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
944944 LdFrm, "ldm${p}${addr:submode} $addr, $dst1",
187187 }
188188
189189 // FIXME: remove when we have a way to marking a MI with these properties.
190 let isLoad = 1, isReturn = 1, isTerminator = 1 in
190 let isSimpleLoad = 1, isReturn = 1, isTerminator = 1 in
191191 def tPOP_RET : TI<(outs reglist:$dst1, variable_ops), (ins),
192192 "pop $dst1", []>;
193193
236236 // Load Store Instructions.
237237 //
238238
239 let isLoad = 1 in {
239 let isSimpleLoad = 1 in {
240240 def tLDR : TI4<(outs GPR:$dst), (ins t_addrmode_s4:$addr),
241241 "ldr $dst, $addr",
242242 [(set GPR:$dst, (load t_addrmode_s4:$addr))]>;
275275 let isReMaterializable = 1 in
276276 def tLDRcp : TIs<(outs GPR:$dst), (ins i32imm:$addr),
277277 "ldr $dst, $addr", []>;
278 } // isLoad
278 } // isSimpleLoad
279279
280280 def tSTR : TI4<(outs), (ins GPR:$src, t_addrmode_s4:$addr),
281281 "str $src, $addr",
306306
307307 // TODO: A7-44: LDMIA - load multiple
308308
309 let isLoad = 1 in
309 let isSimpleLoad = 1 in
310310 def tPOP : TI<(outs reglist:$dst1, variable_ops), (ins),
311311 "pop $dst1", []>;
312312
8787 // Load / store Instructions.
8888 //
8989
90 let isLoad = 1 in {
90 let isSimpleLoad = 1 in {
9191 def FLDD : ADI5<(outs DPR:$dst), (ins addrmode5:$addr),
9292 "fldd", " $dst, $addr",
9393 [(set DPR:$dst, (load addrmode5:$addr))]>;
9595 def FLDS : ASI5<(outs SPR:$dst), (ins addrmode5:$addr),
9696 "flds", " $dst, $addr",
9797 [(set SPR:$dst, (load addrmode5:$addr))]>;
98 } // isLoad
98 } // isSimpleLoad
9999
100100 def FSTD : ADI5<(outs), (ins DPR:$src, addrmode5:$addr),
101101 "fstd", " $src, $addr",
109109 // Load / store multiple Instructions.
110110 //
111111
112 let isLoad = 1 in {
112 let isSimpleLoad = 1 in {
113113 def FLDMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$dst1,
114114 variable_ops),
115115 "fldm${addr:submode}d${p} ${addr:base}, $dst1",
119119 variable_ops),
120120 "fldm${addr:submode}s${p} ${addr:base}, $dst1",
121121 []>;
122 } // isLoad
122 } // isSimpleLoad
123123
124124 let mayStore = 1 in {
125125 def FSTMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$src1,
689689 }
690690
691691 unsigned Opcode = MI.getOpcode();
692 const TargetInstrDescriptor &Desc = TII.get(Opcode);
692 const TargetInstrDescriptor &Desc = *MI.getInstrDescriptor();
693693 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
694694 bool isSub = false;
695695
884884 assert(Offset && "This code isn't needed if offset already handled!");
885885
886886 if (isThumb) {
887 if (TII.isLoad(Opcode)) {
887 if (Desc.isSimpleLoad()) {
888888 // Use the destination register to materialize sp + offset.
889889 unsigned TmpReg = MI.getOperand(0).getReg();
890890 bool UseRR = false;
4040 class MForm opcode, bit load, string asmstr, list pattern, InstrItinClass itin>
4141 : InstAlpha {
4242 let Pattern = pattern;
43 let isLoad = load;
43 let isSimpleLoad = load;
4444 let Defs = [R28]; //We may use this for frame index calculations, so reserve it here
4545
4646 bits<5> Ra;
151151
152152 def WTF : PseudoInstAlpha<(outs), (ins variable_ops), "#wtf", [], s_pseudo>;
153153
154 let isLoad = 1, hasCtrlDep = 1, Defs = [R30], Uses = [R30] in {
154 let hasCtrlDep = 1, Defs = [R30], Uses = [R30] in {
155155 def ADJUSTSTACKUP : PseudoInstAlpha<(outs), (ins s64imm:$amt),
156156 "; ADJUP $amt",
157157 [(callseq_start imm:$amt)], s_pseudo>;
4646 // finally the X-form with the register-register.
4747 //===----------------------------------------------------------------------===//
4848
49 let isLoad = 1 in {
49 let isSimpleLoad = 1 in {
5050 def LQDv16i8:
5151 RI10Form<0b00101100, (outs VECREG:$rT), (ins memri10:$src),
5252 "lqd\t$rT, $src", LoadStore,
557557 "stf.spill [$dstPtr] = $value">, isM;
558558 }
559559
560 let isLoad = 1 in {
560 let isSimpleLoad = 1 in {
561561 def LD1 : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$srcPtr),
562562 "ld1 $dst = [$srcPtr]">, isM;
563563 def LD2 : AForm<0x03, 0x0b, (outs GR:$dst), (ins GR:$srcPtr),
204204 [], IIAlu>;
205205
206206 // Memory Load/Store
207 let isLoad = 1, hasDelaySlot = 1 in
207 let isSimpleLoad = 1, hasDelaySlot = 1 in
208208 class LoadM op, string instr_asm, PatFrag OpNode>:
209209 FI< op,
210210 (outs CPURegs:$dst),
7171
7272 const TargetInstrDescriptor &TID = TII.get(Opcode);
7373
74 isLoad = TID.Flags & M_LOAD_FLAG;
74 isLoad = TID.isSimpleLoad();
7575 isStore = TID.Flags & M_MAY_STORE_FLAG;
7676
7777 unsigned TSFlags = TID.TSFlags;
364364
365365
366366 // Sign extending loads.
367 let isLoad = 1, PPC970_Unit = 2 in {
367 let isSimpleLoad = 1, PPC970_Unit = 2 in {
368368 def LHA8: DForm_1<42, (outs G8RC:$rD), (ins memri:$src),
369369 "lha $rD, $src", LdStLHA,
370370 [(set G8RC:$rD, (sextloadi16 iaddr:$src))]>,
393393 }
394394
395395 // Zero extending loads.
396 let isLoad = 1, PPC970_Unit = 2 in {
396 let isSimpleLoad = 1, PPC970_Unit = 2 in {
397397 def LBZ8 : DForm_1<34, (outs G8RC:$rD), (ins memri:$src),
398398 "lbz $rD, $src", LdStGeneral,
399399 [(set G8RC:$rD, (zextloadi8 iaddr:$src))]>;
432432
433433
434434 // Full 8-byte loads.
435 let isLoad = 1, PPC970_Unit = 2 in {
435 let isSimpleLoad = 1, PPC970_Unit = 2 in {
436436 def LD : DSForm_1<58, 0, (outs G8RC:$rD), (ins memrix:$src),
437437 "ld $rD, $src", LdStLD,
438438 [(set G8RC:$rD, (load ixaddr:$src))]>, isPPC64;
201201 "mtvscr $vB", LdStGeneral,
202202 [(int_ppc_altivec_mtvscr VRRC:$vB)]>;
203203
204 let isLoad = 1, PPC970_Unit = 2 in { // Loads.
204 let isSimpleLoad = 1, PPC970_Unit = 2 in { // Loads.
205205 def LVEBX: XForm_1<31, 7, (outs VRRC:$vD), (ins memrr:$src),
206206 "lvebx $vD, $src", LdStGeneral,
207207 [(set VRRC:$vD, (int_ppc_altivec_lvebx xoaddr:$src))]>;
473473 //
474474
475475 // Unindexed (r+i) Loads.
476 let isLoad = 1, PPC970_Unit = 2 in {
476 let isSimpleLoad = 1, PPC970_Unit = 2 in {
477477 def LBZ : DForm_1<34, (outs GPRC:$rD), (ins memri:$src),
478478 "lbz $rD, $src", LdStGeneral,
479479 [(set GPRC:$rD, (zextloadi8 iaddr:$src))]>;
530530
531531 // Indexed (r+r) Loads.
532532 //
533 let isLoad = 1, PPC970_Unit = 2 in {
533 let isSimpleLoad = 1, PPC970_Unit = 2 in {
534534 def LBZX : XForm_1<31, 87, (outs GPRC:$rD), (ins memrr:$src),
535535 "lbzx $rD, $src", LdStGeneral,
536536 [(set GPRC:$rD, (zextloadi8 xaddr:$src))]>;
189189 bit isIndirectBranch = 0; // Is this instruction an indirect branch?
190190 bit isBarrier = 0; // Can control flow fall through this instruction?
191191 bit isCall = 0; // Is this instruction a call instruction?
192 bit isLoad = 0; // Is this instruction a load instruction?
192 bit isSimpleLoad = 0; // Is this just a load instruction?
193193 bit mayStore = 0; // Can this instruction modify memory?
194194 bit isImplicitDef = 0; // Is this instruction an implicit def instruction?
195195 bit isTwoAddress = 0; // Is this a two address instruction?
345345 "fcmovnu\t{$op, %st(0)|%ST(0), $op}">, DB;
346346
347347 // Floating point loads & stores.
348 let isLoad = 1 in {
348 let isSimpleLoad = 1 in {
349349 def LD_Fp32m : FpIf32<(outs RFP32:$dst), (ins f32mem:$src), ZeroArgFP,
350350 [(set RFP32:$dst, (loadf32 addr:$src))]>;
351351 let isReMaterializable = 1, mayHaveSideEffects = 1 in
585585 "mov{l}\t{$src, $dst|$dst, $src}",
586586 [(store (i32 imm:$src), addr:$dst)]>;
587587
588 let isLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
588 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
589589 def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
590590 "mov{b}\t{$src, $dst|$dst, $src}",
591591 [(set GR8:$dst, (load addr:$src))]>;
24872487 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
24882488 def MOV32_rr : I<0x89, MRMDestReg, (outs GR32_:$dst), (ins GR32_:$src),
24892489 "mov{l}\t{$src, $dst|$dst, $src}", []>;
2490 let isLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
2490 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
24912491 def MOV16_rm : I<0x8B, MRMSrcMem, (outs GR16_:$dst), (ins i16mem:$src),
24922492 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
24932493 def MOV32_rm : I<0x8B, MRMSrcMem, (outs GR32_:$dst), (ins i32mem:$src),
157157 // Data Transfer Instructions
158158 def MMX_MOVD64rr : MMXI<0x6E, MRMSrcReg, (outs VR64:$dst), (ins GR32:$src),
159159 "movd\t{$src, $dst|$dst, $src}", []>;
160 let isLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
160 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
161161 def MMX_MOVD64rm : MMXI<0x6E, MRMSrcMem, (outs VR64:$dst), (ins i32mem:$src),
162162 "movd\t{$src, $dst|$dst, $src}", []>;
163163 def MMX_MOVD64mr : MMXI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR64:$src),
168168
169169 def MMX_MOVQ64rr : MMXI<0x6F, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
170170 "movq\t{$src, $dst|$dst, $src}", []>;
171 let isLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
171 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
172172 def MMX_MOVQ64rm : MMXI<0x6F, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
173173 "movq\t{$src, $dst|$dst, $src}",
174174 [(set VR64:$dst, (load_mmx addr:$src))]>;
300300 // Move Instructions
301301 def MOVSSrr : SSI<0x10, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
302302 "movss\t{$src, $dst|$dst, $src}", []>;
303 let isLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
303 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
304304 def MOVSSrm : SSI<0x10, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
305305 "movss\t{$src, $dst|$dst, $src}",
306306 [(set FR32:$dst, (loadf32 addr:$src))]>;
456456
457457 // Alias instruction to load FR32 from f128mem using movaps. Upper bits are
458458 // disregarded.
459 let isLoad = 1 in
459 let isSimpleLoad = 1 in
460460 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
461461 "movaps\t{$src, $dst|$dst, $src}",
462462 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
633633 // Move Instructions
634634 def MOVAPSrr : PSI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
635635 "movaps\t{$src, $dst|$dst, $src}", []>;
636 let isLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
636 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
637637 def MOVAPSrm : PSI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
638638 "movaps\t{$src, $dst|$dst, $src}",
639639 [(set VR128:$dst, (alignedloadv4f32 addr:$src))]>;
644644
645645 def MOVUPSrr : PSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
646646 "movups\t{$src, $dst|$dst, $src}", []>;
647 let isLoad = 1 in
647 let isSimpleLoad = 1 in
648648 def MOVUPSrm : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
649649 "movups\t{$src, $dst|$dst, $src}",
650650 [(set VR128:$dst, (loadv4f32 addr:$src))]>;
653653 [(store (v4f32 VR128:$src), addr:$dst)]>;
654654
655655 // Intrinsic forms of MOVUPS load and store
656 let isLoad = 1 in
656 let isSimpleLoad = 1 in
657657 def MOVUPSrm_Int : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
658658 "movups\t{$src, $dst|$dst, $src}",
659659 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
10021002 // Move Instructions
10031003 def MOVSDrr : SDI<0x10, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
10041004 "movsd\t{$src, $dst|$dst, $src}", []>;
1005 let isLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
1005 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
10061006 def MOVSDrm : SDI<0x10, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
10071007 "movsd\t{$src, $dst|$dst, $src}",
10081008 [(set FR64:$dst, (loadf64 addr:$src))]>;
11521152
11531153 // Alias instruction to load FR64 from f128mem using movapd. Upper bits are
11541154 // disregarded.
1155 let isLoad = 1 in
1155 let isSimpleLoad = 1 in
11561156 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
11571157 "movapd\t{$src, $dst|$dst, $src}",
11581158 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
13291329 // Move Instructions
13301330 def MOVAPDrr : PDI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
13311331 "movapd\t{$src, $dst|$dst, $src}", []>;
1332 let isLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
1332 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
13331333 def MOVAPDrm : PDI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
13341334 "movapd\t{$src, $dst|$dst, $src}",
13351335 [(set VR128:$dst, (alignedloadv2f64 addr:$src))]>;
13401340
13411341 def MOVUPDrr : PDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
13421342 "movupd\t{$src, $dst|$dst, $src}", []>;
1343 let isLoad = 1 in
1343 let isSimpleLoad = 1 in
13441344 def MOVUPDrm : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
13451345 "movupd\t{$src, $dst|$dst, $src}",
13461346 [(set VR128:$dst, (loadv2f64 addr:$src))]>;
17031703 // Move Instructions
17041704 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
17051705 "movdqa\t{$src, $dst|$dst, $src}", []>;
1706 let isLoad = 1 in
1706 let isSimpleLoad = 1 in
17071707 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
17081708 "movdqa\t{$src, $dst|$dst, $src}",
17091709 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
17101710 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
17111711 "movdqa\t{$src, $dst|$dst, $src}",
17121712 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
1713 let isLoad = 1 in
1713 let isSimpleLoad = 1 in
17141714 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
17151715 "movdqu\t{$src, $dst|$dst, $src}",
17161716 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
17211721 XS, Requires<[HasSSE2]>;
17221722
17231723 // Intrinsic forms of MOVDQU load and store
1724 let isLoad = 1 in
1724 let isSimpleLoad = 1 in
17251725 def MOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
17261726 "movdqu\t{$src, $dst|$dst, $src}",
17271727 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
209209 [(set GR64:$dst, i64immSExt32:$src)]>;
210210 }
211211
212 let isLoad = 1 in
212 let isSimpleLoad = 1 in
213213 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
214214 "mov{q}\t{$src, $dst|$dst, $src}",
215215 [(set GR64:$dst, (load addr:$src))]>;
8383 isIndirectBranch = R->getValueAsBit("isIndirectBranch");
8484 isBarrier = R->getValueAsBit("isBarrier");
8585 isCall = R->getValueAsBit("isCall");
86 isLoad = R->getValueAsBit("isLoad");
86 isSimpleLoad = R->getValueAsBit("isSimpleLoad");
8787 mayStore = R->getValueAsBit("mayStore");
8888 isImplicitDef= R->getValueAsBit("isImplicitDef");
8989 bool isTwoAddress = R->getValueAsBit("isTwoAddress");
9393 bool isIndirectBranch;
9494 bool isBarrier;
9595 bool isCall;
96 bool isLoad;
96 bool isSimpleLoad;
9797 bool mayStore;
9898 bool isImplicitDef;
9999 bool isPredicable;
209209 }
210210
211211 // These two override everything.
212 isLoad = Inst.isLoad;
212 isLoad = Inst.isSimpleLoad;
213213 NeverHasSideEffects = Inst.neverHasSideEffects;
214214
215215 #if 0
307307 if (Inst.isBarrier) OS << "|M_BARRIER_FLAG";
308308 if (Inst.hasDelaySlot) OS << "|M_DELAY_SLOT_FLAG";
309309 if (Inst.isCall) OS << "|M_CALL_FLAG";
310 if (isLoad) OS << "|M_LOAD_FLAG";
310 if (isLoad) OS << "|M_SIMPLE_LOAD_FLAG";
311311 if (mayStore) OS << "|M_MAY_STORE_FLAG";
312312 if (Inst.isImplicitDef)OS << "|M_IMPLICIT_DEF_FLAG";
313313 if (Inst.isPredicable) OS << "|M_PREDICABLE";