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[asan] Split load and store checks in test. NFCI git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288991 91177308-0d34-0410-b5e6-96231b3b80d8 Filipe Cabecinhas 3 years ago
1 changed file(s) with 62 addition(s) and 62 deletion(s). Raw diff Collapse all Expand all
None ; RUN: opt < %s -asan -asan-instrumentation-with-call-threshold=0 -S | FileCheck %s
0 ; RUN: opt < %s -asan -asan-instrumentation-with-call-threshold=0 -S | FileCheck %s -check-prefix=LOAD -check-prefix=STORE -check-prefix=BOTH
11 ; Support ASan instrumentation for constant-mask llvm.masked.{load,store}
22
33 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
1212 declare void @llvm.masked.store.v4p0i32.p0v4p0i32(<4 x i32*>, <4 x i32*>*, i32, <4 x i1>) argmemonly nounwind
1313
1414 define void @store.v4f32.1110(<4 x float> %arg) sanitize_address {
15 ; CHECK-LABEL: @store.v4f32.1110
15 ; BOTH-LABEL: @store.v4f32.1110
1616 %p = load <4 x float>*, <4 x float>** @v4f32, align 8
17 ; CHECK: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 0
18 ; CHECK: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP0]] to i64
19 ; CHECK: call void @__asan_store4(i64 [[PGEP0]])
20 ; CHECK: [[GEP1:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 1
21 ; CHECK: [[PGEP1:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP1]] to i64
22 ; CHECK: call void @__asan_store4(i64 [[PGEP1]])
23 ; CHECK: [[GEP2:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 2
24 ; CHECK: [[PGEP2:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP2]] to i64
25 ; CHECK: call void @__asan_store4(i64 [[PGEP2]])
26 ; CHECK: tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %arg, <4 x float>* %p, i32 4, <4 x i1> )
17 ; STORE: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 0
18 ; STORE: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP0]] to i64
19 ; STORE: call void @__asan_store4(i64 [[PGEP0]])
20 ; STORE: [[GEP1:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 1
21 ; STORE: [[PGEP1:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP1]] to i64
22 ; STORE: call void @__asan_store4(i64 [[PGEP1]])
23 ; STORE: [[GEP2:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 2
24 ; STORE: [[PGEP2:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP2]] to i64
25 ; STORE: call void @__asan_store4(i64 [[PGEP2]])
26 ; STORE: tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %arg, <4 x float>* %p, i32 4, <4 x i1> )
2727 tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %arg, <4 x float>* %p, i32 4, <4 x i1> )
2828 ret void
2929 }
3030
3131 define void @store.v8i32.10010110(<8 x i32> %arg) sanitize_address {
32 ; CHECK-LABEL: @store.v8i32.10010110
32 ; BOTH-LABEL: @store.v8i32.10010110
3333 %p = load <8 x i32>*, <8 x i32>** @v8i32, align 8
34 ; CHECK: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 0
35 ; CHECK: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP0]] to i64
36 ; CHECK: call void @__asan_store4(i64 [[PGEP0]])
37 ; CHECK: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 3
38 ; CHECK: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP3]] to i64
39 ; CHECK: call void @__asan_store4(i64 [[PGEP3]])
40 ; CHECK: [[GEP5:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 5
41 ; CHECK: [[PGEP5:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP5]] to i64
42 ; CHECK: call void @__asan_store4(i64 [[PGEP5]])
43 ; CHECK: [[GEP6:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 6
44 ; CHECK: [[PGEP6:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP6]] to i64
45 ; CHECK: call void @__asan_store4(i64 [[PGEP6]])
46 ; CHECK: tail call void @llvm.masked.store.v8i32.p0v8i32(<8 x i32> %arg, <8 x i32>* %p, i32 8, <8 x i1> )
34 ; STORE: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 0
35 ; STORE: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP0]] to i64
36 ; STORE: call void @__asan_store4(i64 [[PGEP0]])
37 ; STORE: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 3
38 ; STORE: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP3]] to i64
39 ; STORE: call void @__asan_store4(i64 [[PGEP3]])
40 ; STORE: [[GEP5:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 5
41 ; STORE: [[PGEP5:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP5]] to i64
42 ; STORE: call void @__asan_store4(i64 [[PGEP5]])
43 ; STORE: [[GEP6:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 6
44 ; STORE: [[PGEP6:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP6]] to i64
45 ; STORE: call void @__asan_store4(i64 [[PGEP6]])
46 ; STORE: tail call void @llvm.masked.store.v8i32.p0v8i32(<8 x i32> %arg, <8 x i32>* %p, i32 8, <8 x i1> )
4747 tail call void @llvm.masked.store.v8i32.p0v8i32(<8 x i32> %arg, <8 x i32>* %p, i32 8, <8 x i1> )
4848 ret void
4949 }
5050
5151 define void @store.v4i64.0001(<4 x i32*> %arg) sanitize_address {
52 ; CHECK-LABEL: @store.v4i64.0001
52 ; BOTH-LABEL: @store.v4i64.0001
5353 %p = load <4 x i32*>*, <4 x i32*>** @v4i64, align 8
54 ; CHECK: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <4 x i32*>, <4 x i32*>* %p, i64 0, i64 3
55 ; CHECK: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint i32** [[GEP3]] to i64
56 ; CHECK: call void @__asan_store8(i64 [[PGEP3]])
57 ; CHECK: tail call void @llvm.masked.store.v4p0i32.p0v4p0i32(<4 x i32*> %arg, <4 x i32*>* %p, i32 8, <4 x i1> )
54 ; STORE: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <4 x i32*>, <4 x i32*>* %p, i64 0, i64 3
55 ; STORE: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint i32** [[GEP3]] to i64
56 ; STORE: call void @__asan_store8(i64 [[PGEP3]])
57 ; STORE: tail call void @llvm.masked.store.v4p0i32.p0v4p0i32(<4 x i32*> %arg, <4 x i32*>* %p, i32 8, <4 x i1> )
5858 tail call void @llvm.masked.store.v4p0i32.p0v4p0i32(<4 x i32*> %arg, <4 x i32*>* %p, i32 8, <4 x i1> )
5959 ret void
6060 }
6161
6262 define void @store.v4f32.variable(<4 x float> %arg, <4 x i1> %mask) sanitize_address {
63 ; CHECK-LABEL: @store.v4f32.variable
63 ; BOTH-LABEL: @store.v4f32.variable
6464 %p = load <4 x float>*, <4 x float>** @v4f32, align 8
65 ; CHECK-NOT: call void @__asan_store
65 ; BOTH-NOT: call void @__asan_store
6666 tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %arg, <4 x float>* %p, i32 4, <4 x i1> %mask)
6767 ret void
6868 }
7373 declare <4 x i32*> @llvm.masked.load.v4p0i32.p0v4p0i32(<4 x i32*>*, i32, <4 x i1>, <4 x i32*>) argmemonly nounwind
7474
7575 define <8 x i32> @load.v8i32.11100001(<8 x i32> %arg) sanitize_address {
76 ; CHECK-LABEL: @load.v8i32.11100001
76 ; BOTH-LABEL: @load.v8i32.11100001
7777 %p = load <8 x i32>*, <8 x i32>** @v8i32, align 8
78 ; CHECK: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 0
79 ; CHECK: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP0]] to i64
80 ; CHECK: call void @__asan_load4(i64 [[PGEP0]])
81 ; CHECK: [[GEP1:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 1
82 ; CHECK: [[PGEP1:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP1]] to i64
83 ; CHECK: call void @__asan_load4(i64 [[PGEP1]])
84 ; CHECK: [[GEP2:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 2
85 ; CHECK: [[PGEP2:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP2]] to i64
86 ; CHECK: call void @__asan_load4(i64 [[PGEP2]])
87 ; CHECK: [[GEP7:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 7
88 ; CHECK: [[PGEP7:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP7]] to i64
89 ; CHECK: call void @__asan_load4(i64 [[PGEP7]])
90 ; CHECK: tail call <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>* %p, i32 8, <8 x i1> , <8 x i32> %arg)
78 ; LOAD: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 0
79 ; LOAD: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP0]] to i64
80 ; LOAD: call void @__asan_load4(i64 [[PGEP0]])
81 ; LOAD: [[GEP1:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 1
82 ; LOAD: [[PGEP1:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP1]] to i64
83 ; LOAD: call void @__asan_load4(i64 [[PGEP1]])
84 ; LOAD: [[GEP2:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 2
85 ; LOAD: [[PGEP2:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP2]] to i64
86 ; LOAD: call void @__asan_load4(i64 [[PGEP2]])
87 ; LOAD: [[GEP7:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 7
88 ; LOAD: [[PGEP7:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP7]] to i64
89 ; LOAD: call void @__asan_load4(i64 [[PGEP7]])
90 ; LOAD: tail call <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>* %p, i32 8, <8 x i1> , <8 x i32> %arg)
9191 %res = tail call <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>* %p, i32 8, <8 x i1> , <8 x i32> %arg)
9292 ret <8 x i32> %res
9393 }
9494
9595 define <4 x float> @load.v4f32.1001(<4 x float> %arg) sanitize_address {
96 ; CHECK-LABEL: @load.v4f32.1001
96 ; BOTH-LABEL: @load.v4f32.1001
9797 %p = load <4 x float>*, <4 x float>** @v4f32, align 8
98 ; CHECK: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 0
99 ; CHECK: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP0]] to i64
100 ; CHECK: call void @__asan_load4(i64 [[PGEP0]])
101 ; CHECK: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 3
102 ; CHECK: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP3]] to i64
103 ; CHECK: call void @__asan_load4(i64 [[PGEP3]])
104 ; CHECK: tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %p, i32 4, <4 x i1> , <4 x float> %arg)
98 ; LOAD: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 0
99 ; LOAD: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP0]] to i64
100 ; LOAD: call void @__asan_load4(i64 [[PGEP0]])
101 ; LOAD: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 3
102 ; LOAD: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP3]] to i64
103 ; LOAD: call void @__asan_load4(i64 [[PGEP3]])
104 ; LOAD: tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %p, i32 4, <4 x i1> , <4 x float> %arg)
105105 %res = tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %p, i32 4, <4 x i1> , <4 x float> %arg)
106106 ret <4 x float> %res
107107 }
108108
109109 define <4 x i32*> @load.v4i64.0001(<4 x i32*> %arg) sanitize_address {
110 ; CHECK-LABEL: @load.v4i64.0001
110 ; BOTH-LABEL: @load.v4i64.0001
111111 %p = load <4 x i32*>*, <4 x i32*>** @v4i64, align 8
112 ; CHECK: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <4 x i32*>, <4 x i32*>* %p, i64 0, i64 3
113 ; CHECK: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint i32** [[GEP3]] to i64
114 ; CHECK: call void @__asan_load8(i64 [[PGEP3]])
115 ; CHECK: tail call <4 x i32*> @llvm.masked.load.v4p0i32.p0v4p0i32(<4 x i32*>* %p, i32 8, <4 x i1> , <4 x i32*> %arg)
112 ; LOAD: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <4 x i32*>, <4 x i32*>* %p, i64 0, i64 3
113 ; LOAD: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint i32** [[GEP3]] to i64
114 ; LOAD: call void @__asan_load8(i64 [[PGEP3]])
115 ; LOAD: tail call <4 x i32*> @llvm.masked.load.v4p0i32.p0v4p0i32(<4 x i32*>* %p, i32 8, <4 x i1> , <4 x i32*> %arg)
116116 %res = tail call <4 x i32*> @llvm.masked.load.v4p0i32.p0v4p0i32(<4 x i32*>* %p, i32 8, <4 x i1> , <4 x i32*> %arg)
117117 ret <4 x i32*> %res
118118 }
119119
120120 define <4 x float> @load.v4f32.variable(<4 x float> %arg, <4 x i1> %mask) sanitize_address {
121 ; CHECK-LABEL: @load.v4f32.variable
121 ; BOTH-LABEL: @load.v4f32.variable
122122 %p = load <4 x float>*, <4 x float>** @v4f32, align 8
123 ; CHECK-NOT: call void @__asan_load
123 ; BOTH-NOT: call void @__asan_load
124124 %res = tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %p, i32 4, <4 x i1> %mask, <4 x float> %arg)
125125 ret <4 x float> %res
126126 }