llvm.org GIT mirror llvm / 82941fa
[ARM] Add MVE vector load/store instructions. This adds the rest of the vector memory access instructions. It includes contiguous loads/stores, with an ordinary addressing mode such as [r0,#offset] (plus writeback variants); gather loads and scatter stores with a scalar base address register and a vector of offsets from it (written [r0,q1] or similar); and gather/scatters with a vector of base addresses (written [q0,#offset], again with writeback). Additionally, some of the loads can widen each loaded value into a larger vector lane, and the corresponding stores narrow them again. To implement these, we also have to add the addressing modes they need. Also, in AsmParser, the `isMem` query function now has subqueries `isGPRMem` and `isMVEMem`, according to which kind of base register is used by a given memory access operand. I've also had to add an extra check in `checkTargetMatchPredicate` in the AsmParser, without which our last-minute check of `rGPR` register operands against SP and PC was failing an assertion because Tablegen had inserted an immediate 0 in place of one of a pair of tied register operands. (This matches the way the corresponding check for `MCK_rGPR` in `validateTargetOperandClass` is guarded.) Apparently the MVE load instructions were the first to have ever triggered this assertion, but I think only because they were the first to have a combination of the usual Arm pre/post writeback system and the `rGPR` class in particular. Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62680 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364291 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Tatham 1 year, 1 month ago
15 changed file(s) with 4371 addition(s) and 60 deletion(s). Raw diff Collapse all Expand all
24762476 NumBits = 8;
24772477 Scale = 2;
24782478 break;
2479 case ARMII::AddrModeT2_i7:
2480 case ARMII::AddrModeT2_i7s2:
24792481 case ARMII::AddrModeT2_i7s4:
24802482 ImmIdx = FrameRegIdx+1;
24812483 InstrOffs = MI.getOperand(ImmIdx).getImm();
24822484 NumBits = 7;
2483 Scale = 4;
2485 Scale = (AddrMode == ARMII::AddrModeT2_i7s2 ? 2 :
2486 AddrMode == ARMII::AddrModeT2_i7s4 ? 4 : 1);
24842487 break;
24852488 default:
24862489 llvm_unreachable("Unsupported addressing mode!");
109109 def AddrMode5FP16 : AddrMode<17>;
110110 def AddrModeT2_ldrex : AddrMode<18>;
111111 def AddrModeT2_i7s4 : AddrMode<19>;
112 def AddrModeT2_i7s2 : AddrMode<20>;
113 def AddrModeT2_i7 : AddrMode<21>;
112114
113115 // Load / store index mode.
114116 class IndexMode val> {
12311231 let DecoderMethod = "DecodeAddrMode7Operand";
12321232 let ParserMatchClass = MemNoOffsetAsmOperand;
12331233 let MIOperandInfo = (ops GPR:$base);
1234 }
1235
1236 // t_addr_offset_none := reg [r0-r7]
1237 def MemNoOffsetTAsmOperand : AsmOperandClass { let Name = "MemNoOffsetT"; }
1238 def t_addr_offset_none : MemOperand {
1239 let PrintMethod = "printAddrMode7Operand";
1240 let DecoderMethod = "DecodetGPRRegisterClass";
1241 let ParserMatchClass = MemNoOffsetTAsmOperand;
1242 let MIOperandInfo = (ops tGPR:$base);
12341243 }
12351244
12361245 def nohash_imm : Operand {
151151 let ParserMatchClass = VecList4QAsmOperand;
152152 let PrintMethod = "printMVEVectorList<4>";
153153 }
154
155 // taddrmode_imm7 := reg[r0-r7] +/- (imm7 << shift)
156 class TMemImm7ShiftOffsetAsmOperand : AsmOperandClass {
157 let Name = "TMemImm7Shift"#shift#"Offset";
158 let PredicateMethod = "isMemImm7ShiftedOffset<"#shift#",ARM::tGPRRegClassID>";
159 let RenderMethod = "addMemImmOffsetOperands";
160 }
161
162 class taddrmode_imm7 : MemOperand {
163 let ParserMatchClass = TMemImm7ShiftOffsetAsmOperand;
164 // They are printed the same way as the T2 imm8 version
165 let PrintMethod = "printT2AddrModeImm8Operand";
166 // This can also be the same as the T2 version.
167 let EncoderMethod = "getT2AddrModeImmOpValue<7,"#shift#">";
168 let DecoderMethod = "DecodeTAddrModeImm7<"#shift#">";
169 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
170 }
171
172 // t2addrmode_imm7 := reg +/- (imm7)
173 class MemImm7ShiftOffsetAsmOperand : AsmOperandClass {
174 let Name = "MemImm7Shift"#shift#"Offset";
175 let PredicateMethod = "isMemImm7ShiftedOffset<" # shift #
176 ",ARM::GPRnopcRegClassID>";
177 let RenderMethod = "addMemImmOffsetOperands";
178 }
179
180 def MemImm7Shift0OffsetAsmOperand : MemImm7ShiftOffsetAsmOperand<0>;
181 def MemImm7Shift1OffsetAsmOperand : MemImm7ShiftOffsetAsmOperand<1>;
182 def MemImm7Shift2OffsetAsmOperand : MemImm7ShiftOffsetAsmOperand<2>;
183 class T2AddrMode_Imm7 : MemOperand,
184 ComplexPattern", []> {
185 let EncoderMethod = "getT2AddrModeImmOpValue<7,"#shift#">";
186 let DecoderMethod = "DecodeT2AddrModeImm7<"#shift#", 0>";
187 let ParserMatchClass =
188 !cast("MemImm7Shift"#shift#"OffsetAsmOperand");
189 let MIOperandInfo = (ops GPRnopc:$base, i32imm:$offsimm);
190 }
191
192 class t2addrmode_imm7 : T2AddrMode_Imm7 {
193 // They are printed the same way as the imm8 version
194 let PrintMethod = "printT2AddrModeImm8Operand";
195 }
196
197 class MemImm7ShiftOffsetWBAsmOperand : AsmOperandClass {
198 let Name = "MemImm7Shift"#shift#"OffsetWB";
199 let PredicateMethod = "isMemImm7ShiftedOffset<" # shift #
200 ",ARM::rGPRRegClassID>";
201 let RenderMethod = "addMemImmOffsetOperands";
202 }
203
204 def MemImm7Shift0OffsetWBAsmOperand : MemImm7ShiftOffsetWBAsmOperand<0>;
205 def MemImm7Shift1OffsetWBAsmOperand : MemImm7ShiftOffsetWBAsmOperand<1>;
206 def MemImm7Shift2OffsetWBAsmOperand : MemImm7ShiftOffsetWBAsmOperand<2>;
207
208 class t2addrmode_imm7_pre : T2AddrMode_Imm7 {
209 // They are printed the same way as the imm8 version
210 let PrintMethod = "printT2AddrModeImm8Operand";
211 let ParserMatchClass =
212 !cast("MemImm7Shift"#shift#"OffsetWBAsmOperand");
213 let DecoderMethod = "DecodeT2AddrModeImm7<"#shift#", 1>";
214 let MIOperandInfo = (ops rGPR:$base, i32imm:$offsim);
215 }
216
217 class t2am_imm7shiftOffsetAsmOperand
218 : AsmOperandClass { let Name = "Imm7Shift"#shift; }
219 def t2am_imm7shift0OffsetAsmOperand : t2am_imm7shiftOffsetAsmOperand<0>;
220 def t2am_imm7shift1OffsetAsmOperand : t2am_imm7shiftOffsetAsmOperand<1>;
221 def t2am_imm7shift2OffsetAsmOperand : t2am_imm7shiftOffsetAsmOperand<2>;
222
223 class t2am_imm7_offset : MemOperand {
224 // They are printed the same way as the imm8 version
225 let PrintMethod = "printT2AddrModeImm8OffsetOperand";
226 let ParserMatchClass =
227 !cast("t2am_imm7shift"#shift#"OffsetAsmOperand");
228 let EncoderMethod = "getT2ScaledImmOpValue<7,"#shift#">";
229 let DecoderMethod = "DecodeT2Imm7<"#shift#">";
230 }
231
232 // Operands for gather/scatter loads of the form [Rbase, Qoffsets]
233 class MemRegRQOffsetAsmOperand : AsmOperandClass {
234 let Name = "MemRegRQS"#shift#"Offset";
235 let PredicateMethod = "isMemRegRQOffset<"#shift#">";
236 let RenderMethod = "addMemRegRQOffsetOperands";
237 }
238
239 def MemRegRQS0OffsetAsmOperand : MemRegRQOffsetAsmOperand<0>;
240 def MemRegRQS1OffsetAsmOperand : MemRegRQOffsetAsmOperand<1>;
241 def MemRegRQS2OffsetAsmOperand : MemRegRQOffsetAsmOperand<2>;
242 def MemRegRQS3OffsetAsmOperand : MemRegRQOffsetAsmOperand<3>;
243
244 // mve_addr_rq_shift := reg + vreg{ << UXTW #shift}
245 class mve_addr_rq_shift : MemOperand {
246 let EncoderMethod = "getMveAddrModeRQOpValue";
247 let PrintMethod = "printMveAddrModeRQOperand<"#shift#">";
248 let ParserMatchClass =
249 !cast("MemRegRQS"#shift#"OffsetAsmOperand");
250 let DecoderMethod = "DecodeMveAddrModeRQ";
251 let MIOperandInfo = (ops GPRnopc:$base, MQPR:$offsreg);
252 }
253
254 class MemRegQOffsetAsmOperand : AsmOperandClass {
255 let Name = "MemRegQS"#shift#"Offset";
256 let PredicateMethod = "isMemRegQOffset<"#shift#">";
257 let RenderMethod = "addMemImmOffsetOperands";
258 }
259
260 def MemRegQS2OffsetAsmOperand : MemRegQOffsetAsmOperand<2>;
261 def MemRegQS3OffsetAsmOperand : MemRegQOffsetAsmOperand<3>;
262
263 // mve_addr_q_shift := vreg {+ #imm7s2/4}
264 class mve_addr_q_shift : MemOperand {
265 let EncoderMethod = "getMveAddrModeQOpValue<"#shift#">";
266 // Can be printed same way as other reg + imm operands
267 let PrintMethod = "printT2AddrModeImm8Operand";
268 let ParserMatchClass =
269 !cast("MemRegQS"#shift#"OffsetAsmOperand");
270 let DecoderMethod = "DecodeMveAddrModeQ<"#shift#">";
271 let MIOperandInfo = (ops MQPR:$base, i32imm:$imm);
272 }
273
274 // --------- Start of base classes for the instructions themselves
154275
155276 class MVE_MI
156277 string ops, string cstr, list pattern>
32443365
32453366 // end of MVE interleaving load/store
32463367
3368 // start of MVE predicable load/store
3369
3370 // A parameter class for the direction of transfer.
3371 class MVE_ldst_direction {
3372 bit load = b;
3373 dag Oops = Oo;
3374 dag Iops = Io;
3375 string cstr = c;
3376 }
3377 def MVE_ld: MVE_ldst_direction<1, (outs MQPR:$Qd), (ins), ",@earlyclobber $Qd">;
3378 def MVE_st: MVE_ldst_direction<0, (outs), (ins MQPR:$Qd)>;
3379
3380 // A parameter class for the size of memory access in a load.
3381 class MVE_memsz e, int s, AddrMode m, string mn, list types> {
3382 bits<2> encoding = e; // opcode bit(s) for encoding
3383 int shift = s; // shift applied to immediate load offset
3384 AddrMode AM = m;
3385
3386 // For instruction aliases: define the complete list of type
3387 // suffixes at this size, and the canonical ones for loads and
3388 // stores.
3389 string MnemonicLetter = mn;
3390 int TypeBits = !shl(8, s);
3391 string CanonLoadSuffix = ".u" # TypeBits;
3392 string CanonStoreSuffix = "." # TypeBits;
3393 list suffixes = !foreach(letter, types, "." # letter # TypeBits);
3394 }
3395
3396 // Instances of MVE_memsz.
3397 //
3398 // (memD doesn't need an AddrMode, because those are only for
3399 // contiguous loads, and memD is only used by gather/scatters.)
3400 def MVE_memB: MVE_memsz<0b00, 0, AddrModeT2_i7, "b", ["", "u", "s"]>;
3401 def MVE_memH: MVE_memsz<0b01, 1, AddrModeT2_i7s2, "h", ["", "u", "s", "f"]>;
3402 def MVE_memW: MVE_memsz<0b10, 2, AddrModeT2_i7s4, "w", ["", "u", "s", "f"]>;
3403 def MVE_memD: MVE_memsz<0b11, 3, ?, "d", ["", "u", "s", "f"]>;
3404
3405 // This is the base class for all the MVE loads and stores other than
3406 // the interleaving ones. All the non-interleaving loads/stores share
3407 // the characteristic that they operate on just one vector register,
3408 // so they are VPT-predicable.
3409 //
3410 // The predication operand is vpred_n, for both loads and stores. For
3411 // store instructions, the reason is obvious: if there is no output
3412 // register, there can't be a need for an input parameter giving the
3413 // output register's previous value. Load instructions also don't need
3414 // that input parameter, because unlike MVE data processing
3415 // instructions, predicated loads are defined to set the inactive
3416 // lanes of the output register to zero, instead of preserving their
3417 // input values.
3418 class MVE_VLDRSTR_base
3419 dag oops, dag iops, string asm, string suffix,
3420 string ops, string cstr, list pattern=[]>
3421 : MVE_p {
3422 bits<3> Qd;
3423
3424 let Inst{28} = U;
3425 let Inst{25} = 0b0;
3426 let Inst{24} = P;
3427 let Inst{22} = 0b0;
3428 let Inst{21} = W;
3429 let Inst{20} = dir.load;
3430 let Inst{15-13} = Qd{2-0};
3431 let Inst{12} = opc;
3432 let Inst{11-9} = 0b111;
3433
3434 let mayLoad = dir.load;
3435 let mayStore = !eq(dir.load,0);
3436 }
3437
3438 // Contiguous load and store instructions. These come in two main
3439 // categories: same-size loads/stores in which 128 bits of vector
3440 // register is transferred to or from 128 bits of memory in the most
3441 // obvious way, and widening loads / narrowing stores, in which the
3442 // size of memory accessed is less than the size of a vector register,
3443 // so the load instructions sign- or zero-extend each memory value
3444 // into a wider vector lane, and the store instructions truncate
3445 // correspondingly.
3446 //
3447 // The instruction mnemonics for these two classes look reasonably
3448 // similar, but the actual encodings are different enough to need two
3449 // separate base classes.
3450
3451 // Contiguous, same size
3452 class MVE_VLDRSTR_cs
3453 dag oops, dag iops, string asm, string suffix,
3454 IndexMode im, string ops, string cstr>
3455 : MVE_VLDRSTR_base {
3456 bits<12> addr;
3457 let Inst{23} = addr{7};
3458 let Inst{19-16} = addr{11-8};
3459 let Inst{8-7} = memsz.encoding;
3460 let Inst{6-0} = addr{6-0};
3461 }
3462
3463 // Contiguous, widening/narrowing
3464 class MVE_VLDRSTR_cw
3465 bit P, bit W, bits<2> size, dag oops, dag iops,
3466 string asm, string suffix, IndexMode im,
3467 string ops, string cstr>
3468 : MVE_VLDRSTR_base {
3469 bits<11> addr;
3470 let Inst{23} = addr{7};
3471 let Inst{19} = memsz.encoding{0}; // enough to tell 16- from 32-bit
3472 let Inst{18-16} = addr{10-8};
3473 let Inst{8-7} = size;
3474 let Inst{6-0} = addr{6-0};
3475
3476 let IM = im;
3477 }
3478
3479 // Multiclass wrapper on each of the _cw and _cs base classes, to
3480 // generate three writeback modes (none, preindex, postindex).
3481
3482 multiclass MVE_VLDRSTR_cw_m
3483 string asm, string suffix, bit U, bits<2> size> {
3484 let AM = memsz.AM in {
3485 def "" : MVE_VLDRSTR_cw<
3486 dir, memsz, U, 1, 0, size,
3487 dir.Oops, !con(dir.Iops, (ins taddrmode_imm7:$addr)),
3488 asm, suffix, IndexModeNone, "$Qd, $addr", "">;
3489
3490 def _pre : MVE_VLDRSTR_cw<
3491 dir, memsz, U, 1, 1, size,
3492 !con((outs tGPR:$wb), dir.Oops),
3493 !con(dir.Iops, (ins taddrmode_imm7:$addr)),
3494 asm, suffix, IndexModePre, "$Qd, $addr!", "$addr.base = $wb"> {
3495 let DecoderMethod = "DecodeMVE_MEM_1_pre<"#memsz.shift#">";
3496 }
3497
3498 def _post : MVE_VLDRSTR_cw<
3499 dir, memsz, U, 0, 1, size,
3500 !con((outs tGPR:$wb), dir.Oops),
3501 !con(dir.Iops, (ins t_addr_offset_none:$Rn,
3502 t2am_imm7_offset:$addr)),
3503 asm, suffix, IndexModePost, "$Qd, $Rn$addr", "$Rn.base = $wb"> {
3504 bits<4> Rn;
3505 let Inst{18-16} = Rn{2-0};
3506 }
3507 }
3508 }
3509
3510 multiclass MVE_VLDRSTR_cs_m
3511 string asm, string suffix> {
3512 let AM = memsz.AM in {
3513 def "" : MVE_VLDRSTR_cs<
3514 dir, memsz, 1, 0,
3515 dir.Oops, !con(dir.Iops, (ins t2addrmode_imm7:$addr)),
3516 asm, suffix, IndexModeNone, "$Qd, $addr", "">;
3517
3518 def _pre : MVE_VLDRSTR_cs<
3519 dir, memsz, 1, 1,
3520 !con((outs rGPR:$wb), dir.Oops),
3521 !con(dir.Iops, (ins t2addrmode_imm7_pre:$addr)),
3522 asm, suffix, IndexModePre, "$Qd, $addr!", "$addr.base = $wb"> {
3523 let DecoderMethod = "DecodeMVE_MEM_2_pre<"#memsz.shift#">";
3524 }
3525
3526 def _post : MVE_VLDRSTR_cs<
3527 dir, memsz, 0, 1,
3528 !con((outs rGPR:$wb), dir.Oops),
3529 // We need an !if here to select the base register class,
3530 // because it's legal to write back to SP in a load of this
3531 // type, but not in a store.
3532 !con(dir.Iops, (ins !if(dir.load, t2_addr_offset_none,
3533 t2_nosp_addr_offset_none):$Rn,
3534 t2am_imm7_offset:$addr)),
3535 asm, suffix, IndexModePost, "$Qd, $Rn$addr", "$Rn.base = $wb"> {
3536 bits<4> Rn;
3537 let Inst{19-16} = Rn{3-0};
3538 }
3539 }
3540 }
3541
3542 // Now actually declare all the contiguous load/stores, via those
3543 // multiclasses. The instruction ids coming out of this are the bare
3544 // names shown in the defm, with _pre or _post appended for writeback,
3545 // e.g. MVE_VLDRBS16, MVE_VSTRB16_pre, MVE_VSTRHU16_post.
3546
3547 defm MVE_VLDRBS16: MVE_VLDRSTR_cw_m;
3548 defm MVE_VLDRBS32: MVE_VLDRSTR_cw_m;
3549 defm MVE_VLDRBU16: MVE_VLDRSTR_cw_m;
3550 defm MVE_VLDRBU32: MVE_VLDRSTR_cw_m;
3551 defm MVE_VLDRHS32: MVE_VLDRSTR_cw_m;
3552 defm MVE_VLDRHU32: MVE_VLDRSTR_cw_m;
3553
3554 defm MVE_VLDRBU8: MVE_VLDRSTR_cs_m;
3555 defm MVE_VLDRHU16: MVE_VLDRSTR_cs_m;
3556 defm MVE_VLDRWU32: MVE_VLDRSTR_cs_m;
3557
3558 defm MVE_VSTRB16: MVE_VLDRSTR_cw_m;
3559 defm MVE_VSTRB32: MVE_VLDRSTR_cw_m;
3560 defm MVE_VSTRH32: MVE_VLDRSTR_cw_m;
3561
3562 defm MVE_VSTRBU8 : MVE_VLDRSTR_cs_m;
3563 defm MVE_VSTRHU16: MVE_VLDRSTR_cs_m;
3564 defm MVE_VSTRWU32: MVE_VLDRSTR_cs_m;
3565
3566 // Gather loads / scatter stores whose address operand is of the form
3567 // [Rn,Qm], i.e. a single GPR as the common base address, plus a
3568 // vector of offset from it. ('Load/store this sequence of elements of
3569 // the same array.')
3570 //
3571 // Like the contiguous family, these loads and stores can widen the
3572 // loaded values / truncate the stored ones, or they can just
3573 // load/store the same size of memory and vector lane. But unlike the
3574 // contiguous family, there's no particular difference in encoding
3575 // between those two cases.
3576 //
3577 // This family also comes with the option to scale the offset values
3578 // in Qm by the size of the loaded memory (i.e. to treat them as array
3579 // indices), or not to scale them (to treat them as plain byte offsets
3580 // in memory, so that perhaps the loaded values are unaligned). The
3581 // scaled instructions' address operand in assembly looks like
3582 // [Rn,Qm,UXTW #2] or similar.
3583
3584 // Base class.
3585 class MVE_VLDRSTR_rq
3586 bits<2> size, bit os, string asm, string suffix, int shift>
3587 : MVE_VLDRSTR_base
3588 !con(dir.Iops, (ins mve_addr_rq_shift:$addr)),
3589 asm, suffix, "$Qd, $addr", dir.cstr> {
3590 bits<7> addr;
3591 let Inst{23} = 0b1;
3592 let Inst{19-16} = addr{6-3};
3593 let Inst{8-7} = size;
3594 let Inst{6} = memsz.encoding{1};
3595 let Inst{5} = 0;
3596 let Inst{4} = memsz.encoding{0};
3597 let Inst{3-1} = addr{2-0};
3598 let Inst{0} = os;
3599 }
3600
3601 // Multiclass that defines the scaled and unscaled versions of an
3602 // instruction, when the memory size is wider than a byte. The scaled
3603 // version gets the default name like MVE_VLDRBU16_rq; the unscaled /
3604 // potentially unaligned version gets a "_u" suffix, e.g.
3605 // MVE_VLDRBU16_rq_u.
3606 multiclass MVE_VLDRSTR_rq_w
3607 string asm, string suffix, bit U, bits<2> size> {
3608 def _u : MVE_VLDRSTR_rq;
3609 def "" : MVE_VLDRSTR_rq;
3610 }
3611
3612 // Subclass of MVE_VLDRSTR_rq with the same API as that multiclass,
3613 // for use when the memory size is one byte, so there's no 'scaled'
3614 // version of the instruction at all. (This is encoded as if it were
3615 // unscaled, but named in the default way with no _u suffix.)
3616 class MVE_VLDRSTR_rq_b
3617 string asm, string suffix, bit U, bits<2> size>
3618 : MVE_VLDRSTR_rq;
3619
3620 // Actually define all the loads and stores in this family.
3621
3622 def MVE_VLDRBU8_rq : MVE_VLDRSTR_rq_b;
3623 def MVE_VLDRBU16_rq: MVE_VLDRSTR_rq_b;
3624 def MVE_VLDRBS16_rq: MVE_VLDRSTR_rq_b;
3625 def MVE_VLDRBU32_rq: MVE_VLDRSTR_rq_b;
3626 def MVE_VLDRBS32_rq: MVE_VLDRSTR_rq_b;
3627
3628 defm MVE_VLDRHU16_rq: MVE_VLDRSTR_rq_w;
3629 defm MVE_VLDRHU32_rq: MVE_VLDRSTR_rq_w;
3630 defm MVE_VLDRHS32_rq: MVE_VLDRSTR_rq_w;
3631 defm MVE_VLDRWU32_rq: MVE_VLDRSTR_rq_w;
3632 defm MVE_VLDRDU64_rq: MVE_VLDRSTR_rq_w;
3633
3634 def MVE_VSTRB8_rq : MVE_VLDRSTR_rq_b;
3635 def MVE_VSTRB16_rq : MVE_VLDRSTR_rq_b;
3636 def MVE_VSTRB32_rq : MVE_VLDRSTR_rq_b;
3637
3638 defm MVE_VSTRH16_rq : MVE_VLDRSTR_rq_w;
3639 defm MVE_VSTRH32_rq : MVE_VLDRSTR_rq_w;
3640 defm MVE_VSTRW32_rq : MVE_VLDRSTR_rq_w;
3641 defm MVE_VSTRD64_rq : MVE_VLDRSTR_rq_w;
3642
3643 // Gather loads / scatter stores whose address operand is of the form
3644 // [Qm,#imm], i.e. a vector containing a full base address for each
3645 // loaded item, plus an immediate offset applied consistently to all
3646 // of them. ('Load/store the same field from this vector of pointers
3647 // to a structure type.')
3648 //
3649 // This family requires the vector lane size to be at least 32 bits
3650 // (so there's room for an address in each lane at all). It has no
3651 // widening/narrowing variants. But it does support preindex
3652 // writeback, in which the address vector is updated to hold the
3653 // addresses actually loaded from.
3654
3655 // Base class.
3656 class MVE_VLDRSTR_qi
3657 string asm, string wbAsm, string suffix, string cstr = "">
3658 : MVE_VLDRSTR_base
3659 !con(dir.Iops, (ins mve_addr_q_shift:$addr)),
3660 asm, suffix, "$Qd, $addr" # wbAsm, cstr # dir.cstr> {
3661 bits<11> addr;
3662 let Inst{23} = addr{7};
3663 let Inst{19-17} = addr{10-8};
3664 let Inst{16} = 0;
3665 let Inst{8} = memsz.encoding{0}; // enough to distinguish 32- from 64-bit
3666 let Inst{7} = 0;
3667 let Inst{6-0} = addr{6-0};
3668 }
3669
3670 // Multiclass that generates the non-writeback and writeback variants.
3671 multiclass MVE_VLDRSTR_qi_m
3672 string asm, string suffix> {
3673 def "" : MVE_VLDRSTR_qi;
3674 def _pre : MVE_VLDRSTR_qi
3675 "$addr.base = $wb"> {
3676 let DecoderMethod="DecodeMVE_MEM_3_pre<"#memsz.shift#">";
3677 }
3678 }
3679
3680 // Actual instruction definitions.
3681 defm MVE_VLDRWU32_qi: MVE_VLDRSTR_qi_m;
3682 defm MVE_VLDRDU64_qi: MVE_VLDRSTR_qi_m;
3683 defm MVE_VSTRW32_qi: MVE_VLDRSTR_qi_m;
3684 defm MVE_VSTRD64_qi: MVE_VLDRSTR_qi_m;
3685
3686 // Define aliases for all the instructions where memory size and
3687 // vector lane size are the same. These are mnemonic aliases, so they
3688 // apply consistently across all of the above families - contiguous
3689 // loads, and both the rq and qi types of gather/scatter.
3690 //
3691 // Rationale: As long as you're loading (for example) 16-bit memory
3692 // values into 16-bit vector lanes, you can think of them as signed or
3693 // unsigned integers, fp16 or just raw 16-bit blobs and it makes no
3694 // difference. So we permit all of vldrh.16, vldrh.u16, vldrh.s16,
3695 // vldrh.f16 and treat them all as equivalent to the canonical
3696 // spelling (which happens to be .u16 for loads, and just .16 for
3697 // stores).
3698
3699 foreach vpt_cond = ["", "t", "e"] in
3700 foreach memsz = [MVE_memB, MVE_memH, MVE_memW, MVE_memD] in
3701 foreach suffix = memsz.suffixes in {
3702
3703 // These foreaches are conceptually ifs, implemented by iterating a
3704 // dummy variable over a list with 0 or 1 elements depending on the
3705 // condition. The idea is to iterate over _nearly_ all the suffixes
3706 // in memsz.suffixes, but omit the one we want all the others to alias.
3707
3708 foreach _ = !if(!ne(suffix, memsz.CanonLoadSuffix), [1], []) in
3709 def : MnemonicAlias<
3710 "vldr" # memsz.MnemonicLetter # vpt_cond # suffix,
3711 "vldr" # memsz.MnemonicLetter # vpt_cond # memsz.CanonLoadSuffix>;
3712
3713 foreach _ = !if(!ne(suffix, memsz.CanonStoreSuffix), [1], []) in
3714 def : MnemonicAlias<
3715 "vstr" # memsz.MnemonicLetter # vpt_cond # suffix,
3716 "vstr" # memsz.MnemonicLetter # vpt_cond # memsz.CanonStoreSuffix>;
3717 }
3718
3719 // end of MVE predicable load/store
3720
32473721 class MVE_VPT size, dag iops, string asm, list pattern=[]>
32483722 : MVE_MI<(outs ), iops, NoItinerary, !strconcat("vpt", "${Mk}", ".", suffix), asm, "", pattern> {
32493723 bits<3> fc;
211211 }
212212
213213 // t2addrmode_posimm8 := reg + imm8
214 def MemPosImm8OffsetAsmOperand : AsmOperandClass {let Name="MemPosImm8Offset";}
214 def MemPosImm8OffsetAsmOperand : AsmOperandClass {
215 let Name="MemPosImm8Offset";
216 let RenderMethod = "addMemImmOffsetOperands";
217 }
215218 def t2addrmode_posimm8 : MemOperand {
216219 let PrintMethod = "printT2AddrModeImm8Operand";
217 let EncoderMethod = "getT2AddrModeImm8OpValue";
220 let EncoderMethod = "getT2AddrModeImmOpValue<8,0>";
218221 let DecoderMethod = "DecodeT2AddrModeImm8";
219222 let ParserMatchClass = MemPosImm8OffsetAsmOperand;
220223 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
221224 }
222225
223226 // t2addrmode_negimm8 := reg - imm8
224 def MemNegImm8OffsetAsmOperand : AsmOperandClass {let Name="MemNegImm8Offset";}
227 def MemNegImm8OffsetAsmOperand : AsmOperandClass {
228 let Name="MemNegImm8Offset";
229 let RenderMethod = "addMemImmOffsetOperands";
230 }
225231 def t2addrmode_negimm8 : MemOperand,
226232 ComplexPattern {
227233 let PrintMethod = "printT2AddrModeImm8Operand";
228 let EncoderMethod = "getT2AddrModeImm8OpValue";
234 let EncoderMethod = "getT2AddrModeImmOpValue<8,0>";
229235 let DecoderMethod = "DecodeT2AddrModeImm8";
230236 let ParserMatchClass = MemNegImm8OffsetAsmOperand;
231237 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
232238 }
233239
234240 // t2addrmode_imm8 := reg +/- imm8
235 def MemImm8OffsetAsmOperand : AsmOperandClass { let Name = "MemImm8Offset"; }
241 def MemImm8OffsetAsmOperand : AsmOperandClass {
242 let Name = "MemImm8Offset";
243 let RenderMethod = "addMemImmOffsetOperands";
244 }
236245 class T2AddrMode_Imm8 : MemOperand,
237246 ComplexPattern {
238 let EncoderMethod = "getT2AddrModeImm8OpValue";
247 let EncoderMethod = "getT2AddrModeImmOpValue<8,0>";
239248 let DecoderMethod = "DecodeT2AddrModeImm8";
240249 let ParserMatchClass = MemImm8OffsetAsmOperand;
241250 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
10241024 if (!CE) return false;
10251025 Val = CE->getValue();
10261026 }
1027 else if (isMem()) {
1027 else if (isGPRMem()) {
10281028 if(!Memory.OffsetImm || Memory.OffsetRegNum) return false;
10291029 if(Memory.BaseRegNum != ARM::PC) return false;
10301030 Val = Memory.OffsetImm->getValue();
10581058 int64_t Value = CE->getValue();
10591059 return ((Value & 3) == 0) && Value >= N && Value <= M;
10601060 }
1061
1061 template
1062 bool isImmediateS2() const {
1063 if (!isImm()) return false;
1064 const MCConstantExpr *CE = dyn_cast(getImm());
1065 if (!CE) return false;
1066 int64_t Value = CE->getValue();
1067 return ((Value & 1) == 0) && Value >= N && Value <= M;
1068 }
10621069 bool isFBits16() const {
10631070 return isImmediate<0, 17>();
10641071 }
10701077 }
10711078 bool isImm7s4() const {
10721079 return isImmediateS4<-508, 508>();
1080 }
1081 bool isImm7Shift0() const {
1082 return isImmediate<-127, 127>();
1083 }
1084 bool isImm7Shift1() const {
1085 return isImmediateS2<-255, 255>();
1086 }
1087 bool isImm7Shift2() const {
1088 return isImmediateS4<-511, 511>();
1089 }
1090 bool isImm7() const {
1091 return isImmediate<-127, 127>();
10731092 }
10741093 bool isImm0_1020s4() const {
10751094 return isImmediateS4<0, 1020>();
12521271 bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
12531272 bool isTraceSyncBarrierOpt() const { return Kind == k_TraceSyncBarrierOpt; }
12541273 bool isMem() const override {
1274 return isGPRMem() || isMVEMem();
1275 }
1276 bool isMVEMem() const {
1277 if (Kind != k_Memory)
1278 return false;
1279 if (Memory.BaseRegNum &&
1280 !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.BaseRegNum) &&
1281 !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Memory.BaseRegNum))
1282 return false;
1283 if (Memory.OffsetRegNum &&
1284 !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(
1285 Memory.OffsetRegNum))
1286 return false;
1287 return true;
1288 }
1289 bool isGPRMem() const {
12551290 if (Kind != k_Memory)
12561291 return false;
12571292 if (Memory.BaseRegNum &&
13311366 return isPostIdxRegShifted() && PostIdxReg.ShiftTy == ARM_AM::no_shift;
13321367 }
13331368 bool isMemNoOffset(bool alignOK = false, unsigned Alignment = 0) const {
1334 if (!isMem())
1369 if (!isGPRMem())
13351370 return false;
13361371 // No offset of any kind.
13371372 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
13381373 (alignOK || Memory.Alignment == Alignment);
13391374 }
13401375 bool isMemNoOffsetT2(bool alignOK = false, unsigned Alignment = 0) const {
1341 if (!isMem())
1376 if (!isGPRMem())
13421377 return false;
13431378
13441379 if (!ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains(
13501385 (alignOK || Memory.Alignment == Alignment);
13511386 }
13521387 bool isMemNoOffsetT2NoSp(bool alignOK = false, unsigned Alignment = 0) const {
1353 if (!isMem())
1388 if (!isGPRMem())
13541389 return false;
13551390
13561391 if (!ARMMCRegisterClasses[ARM::rGPRRegClassID].contains(
13611396 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
13621397 (alignOK || Memory.Alignment == Alignment);
13631398 }
1399 bool isMemNoOffsetT(bool alignOK = false, unsigned Alignment = 0) const {
1400 if (!isGPRMem())
1401 return false;
1402
1403 if (!ARMMCRegisterClasses[ARM::tGPRRegClassID].contains(
1404 Memory.BaseRegNum))
1405 return false;
1406
1407 // No offset of any kind.
1408 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1409 (alignOK || Memory.Alignment == Alignment);
1410 }
13641411 bool isMemPCRelImm12() const {
1365 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1412 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
13661413 return false;
13671414 // Base register must be PC.
13681415 if (Memory.BaseRegNum != ARM::PC)
14491496 }
14501497
14511498 bool isAddrMode2() const {
1452 if (!isMem() || Memory.Alignment != 0) return false;
1499 if (!isGPRMem() || Memory.Alignment != 0) return false;
14531500 // Check for register offset.
14541501 if (Memory.OffsetRegNum) return true;
14551502 // Immediate offset in range [-4095, 4095].
14741521 // and we reject it.
14751522 if (isImm() && !isa(getImm()))
14761523 return true;
1477 if (!isMem() || Memory.Alignment != 0) return false;
1524 if (!isGPRMem() || Memory.Alignment != 0) return false;
14781525 // No shifts are legal for AM3.
14791526 if (Memory.ShiftType != ARM_AM::no_shift) return false;
14801527 // Check for register offset.
15081555 // and we reject it.
15091556 if (isImm() && !isa(getImm()))
15101557 return true;
1511 if (!isMem() || Memory.Alignment != 0) return false;
1558 if (!isGPRMem() || Memory.Alignment != 0) return false;
15121559 // Check for register offset.
15131560 if (Memory.OffsetRegNum) return false;
15141561 // Immediate offset in range [-1020, 1020] and a multiple of 4.
15241571 // and we reject it.
15251572 if (isImm() && !isa(getImm()))
15261573 return true;
1527 if (!isMem() || Memory.Alignment != 0) return false;
1574 if (!isGPRMem() || Memory.Alignment != 0) return false;
15281575 // Check for register offset.
15291576 if (Memory.OffsetRegNum) return false;
15301577 // Immediate offset in range [-510, 510] and a multiple of 2.
15351582 }
15361583
15371584 bool isMemTBB() const {
1538 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1585 if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative ||
15391586 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
15401587 return false;
15411588 return true;
15421589 }
15431590
15441591 bool isMemTBH() const {
1545 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1592 if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative ||
15461593 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
15471594 Memory.Alignment != 0 )
15481595 return false;
15501597 }
15511598
15521599 bool isMemRegOffset() const {
1553 if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
1600 if (!isGPRMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
15541601 return false;
15551602 return true;
15561603 }
15571604
15581605 bool isT2MemRegOffset() const {
1559 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1606 if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative ||
15601607 Memory.Alignment != 0 || Memory.BaseRegNum == ARM::PC)
15611608 return false;
15621609 // Only lsl #{0, 1, 2, 3} allowed.
15701617 bool isMemThumbRR() const {
15711618 // Thumb reg+reg addressing is simple. Just two registers, a base and
15721619 // an offset. No shifts, negations or any other complicating factors.
1573 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1620 if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative ||
15741621 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
15751622 return false;
15761623 return isARMLowRegister(Memory.BaseRegNum) &&
15781625 }
15791626
15801627 bool isMemThumbRIs4() const {
1581 if (!isMem() || Memory.OffsetRegNum != 0 ||
1628 if (!isGPRMem() || Memory.OffsetRegNum != 0 ||
15821629 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
15831630 return false;
15841631 // Immediate offset, multiple of 4 in range [0, 124].
15881635 }
15891636
15901637 bool isMemThumbRIs2() const {
1591 if (!isMem() || Memory.OffsetRegNum != 0 ||
1638 if (!isGPRMem() || Memory.OffsetRegNum != 0 ||
15921639 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
15931640 return false;
15941641 // Immediate offset, multiple of 4 in range [0, 62].
15981645 }
15991646
16001647 bool isMemThumbRIs1() const {
1601 if (!isMem() || Memory.OffsetRegNum != 0 ||
1648 if (!isGPRMem() || Memory.OffsetRegNum != 0 ||
16021649 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
16031650 return false;
16041651 // Immediate offset in range [0, 31].
16081655 }
16091656
16101657 bool isMemThumbSPI() const {
1611 if (!isMem() || Memory.OffsetRegNum != 0 ||
1658 if (!isGPRMem() || Memory.OffsetRegNum != 0 ||
16121659 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
16131660 return false;
16141661 // Immediate offset, multiple of 4 in range [0, 1020].
16231670 // and we reject it.
16241671 if (isImm() && !isa(getImm()))
16251672 return true;
1626 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1673 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
16271674 return false;
16281675 // Immediate offset a multiple of 4 in range [-1020, 1020].
16291676 if (!Memory.OffsetImm) return true;
16381685 // and we reject it.
16391686 if (isImm() && !isa(getImm()))
16401687 return true;
1641 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0 ||
1688 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0 ||
16421689 !ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains(
16431690 Memory.BaseRegNum))
16441691 return false;
16491696 return (Val >= -508 && Val <= 508 && (Val & 3) == 0) || Val == INT32_MIN;
16501697 }
16511698 bool isMemImm0_1020s4Offset() const {
1652 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1699 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
16531700 return false;
16541701 // Immediate offset a multiple of 4 in range [0, 1020].
16551702 if (!Memory.OffsetImm) return true;
16581705 }
16591706
16601707 bool isMemImm8Offset() const {
1661 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1708 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
16621709 return false;
16631710 // Base reg of PC isn't allowed for these encodings.
16641711 if (Memory.BaseRegNum == ARM::PC) return false;
16691716 (Val > -256 && Val < 256);
16701717 }
16711718
1719 template
1720 bool isMemImm7ShiftedOffset() const {
1721 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0 ||
1722 !ARMMCRegisterClasses[RegClassID].contains(Memory.BaseRegNum))
1723 return false;
1724
1725 // Expect an immediate offset equal to an element of the range
1726 // [-127, 127], shifted left by Bits.
1727
1728 if (!Memory.OffsetImm) return true;
1729 int64_t Val = Memory.OffsetImm->getValue();
1730
1731 // INT32_MIN is a special-case value (indicating the encoding with
1732 // zero offset and the subtract bit set)
1733 if (Val == INT32_MIN)
1734 return true;
1735
1736 unsigned Divisor = 1U << Bits;
1737
1738 // Check that the low bits are zero
1739 if (Val % Divisor != 0)
1740 return false;
1741
1742 // Check that the remaining offset is within range.
1743 Val /= Divisor;
1744 return (Val >= -127 && Val <= 127);
1745 }
1746
1747 template bool isMemRegRQOffset() const {
1748 if (!isMVEMem() || Memory.OffsetImm != 0 || Memory.Alignment != 0)
1749 return false;
1750
1751 if (!ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains(
1752 Memory.BaseRegNum))
1753 return false;
1754 if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(
1755 Memory.OffsetRegNum))
1756 return false;
1757
1758 if (shift == 0 && Memory.ShiftType != ARM_AM::no_shift)
1759 return false;
1760
1761 if (shift > 0 &&
1762 (Memory.ShiftType != ARM_AM::uxtw || Memory.ShiftImm != shift))
1763 return false;
1764
1765 return true;
1766 }
1767
1768 template bool isMemRegQOffset() const {
1769 if (!isMVEMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1770 return false;
1771
1772 if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(
1773 Memory.BaseRegNum))
1774 return false;
1775
1776 if(!Memory.OffsetImm) return true;
1777 static_assert(shift < 56,
1778 "Such that we dont shift by a value higher than 62");
1779 int64_t Val = Memory.OffsetImm->getValue();
1780
1781 // The value must be a multiple of (1 << shift)
1782 if ((Val & ((1U << shift) - 1)) != 0)
1783 return false;
1784
1785 // And be in the right range, depending on the amount that it is shifted
1786 // by. Shift 0, is equal to 7 unsigned bits, the sign bit is set
1787 // separately.
1788 int64_t Range = (1U << (7+shift)) - 1;
1789 return (Val == INT32_MIN) || (Val > -Range && Val < Range);
1790 }
1791
16721792 bool isMemPosImm8Offset() const {
1673 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1793 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
16741794 return false;
16751795 // Immediate offset in range [0, 255].
16761796 if (!Memory.OffsetImm) return true;
16791799 }
16801800
16811801 bool isMemNegImm8Offset() const {
1682 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1802 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
16831803 return false;
16841804 // Base reg of PC isn't allowed for these encodings.
16851805 if (Memory.BaseRegNum == ARM::PC) return false;
16911811 }
16921812
16931813 bool isMemUImm12Offset() const {
1694 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1814 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
16951815 return false;
16961816 // Immediate offset in range [0, 4095].
16971817 if (!Memory.OffsetImm) return true;
17071827 if (isImm() && !isa(getImm()))
17081828 return true;
17091829
1710 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1830 if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
17111831 return false;
17121832 // Immediate offset in range [-4095, 4095].
17131833 if (!Memory.OffsetImm) return true;
24222542 Inst.addOperand(MCOperand::createImm(CE->getValue()));
24232543 }
24242544
2545 void addImm7Shift0Operands(MCInst &Inst, unsigned N) const {
2546 assert(N == 1 && "Invalid number of operands!");
2547 const MCConstantExpr *CE = dyn_cast(getImm());
2548 assert(CE != nullptr && "Invalid operand type!");
2549 Inst.addOperand(MCOperand::createImm(CE->getValue()));
2550 }
2551
2552 void addImm7Shift1Operands(MCInst &Inst, unsigned N) const {
2553 assert(N == 1 && "Invalid number of operands!");
2554 const MCConstantExpr *CE = dyn_cast(getImm());
2555 assert(CE != nullptr && "Invalid operand type!");
2556 Inst.addOperand(MCOperand::createImm(CE->getValue()));
2557 }
2558
2559 void addImm7Shift2Operands(MCInst &Inst, unsigned N) const {
2560 assert(N == 1 && "Invalid number of operands!");
2561 const MCConstantExpr *CE = dyn_cast(getImm());
2562 assert(CE != nullptr && "Invalid operand type!");
2563 Inst.addOperand(MCOperand::createImm(CE->getValue()));
2564 }
2565
2566 void addImm7Operands(MCInst &Inst, unsigned N) const {
2567 assert(N == 1 && "Invalid number of operands!");
2568 const MCConstantExpr *CE = dyn_cast(getImm());
2569 assert(CE != nullptr && "Invalid operand type!");
2570 Inst.addOperand(MCOperand::createImm(CE->getValue()));
2571 }
2572
24252573 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
24262574 assert(N == 1 && "Invalid number of operands!");
24272575 // The immediate is scaled by four in the encoding and is stored
25312679 return;
25322680 }
25332681
2534 assert(isMem() && "Unknown value type!");
2682 assert(isGPRMem() && "Unknown value type!");
25352683 assert(isa(Memory.OffsetImm) && "Unknown value type!");
25362684 Inst.addOperand(MCOperand::createImm(Memory.OffsetImm->getValue()));
25372685 }
25622710 }
25632711
25642712 void addMemNoOffsetT2NoSpOperands(MCInst &Inst, unsigned N) const {
2713 assert(N == 1 && "Invalid number of operands!");
2714 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2715 }
2716
2717 void addMemNoOffsetTOperands(MCInst &Inst, unsigned N) const {
25652718 assert(N == 1 && "Invalid number of operands!");
25662719 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
25672720 }
28072960 Inst.addOperand(MCOperand::createImm(Val));
28082961 }
28092962
2810 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2963 void addMemImmOffsetOperands(MCInst &Inst, unsigned N) const {
28112964 assert(N == 2 && "Invalid number of operands!");
28122965 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
28132966 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
28142967 Inst.addOperand(MCOperand::createImm(Val));
28152968 }
28162969
2817 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2818 addMemImm8OffsetOperands(Inst, N);
2819 }
2820
2821 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2822 addMemImm8OffsetOperands(Inst, N);
2970 void addMemRegRQOffsetOperands(MCInst &Inst, unsigned N) const {
2971 assert(N == 2 && "Invalid number of operands!");
2972 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2973 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
28232974 }
28242975
28252976 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
56565807 St = ARM_AM::ror;
56575808 else if (ShiftName == "rrx" || ShiftName == "RRX")
56585809 St = ARM_AM::rrx;
5810 else if (ShiftName == "uxtw" || ShiftName == "UXTW")
5811 St = ARM_AM::uxtw;
56595812 else
56605813 return Error(Loc, "illegal shift operator");
56615814 Parser.Lex(); // Eat shift type token.
65176670
65186671 if (!Op2.isReg())
65196672 return;
6520 if (!Op3.isMem())
6673 if (!Op3.isGPRMem())
65216674 return;
65226675
65236676 const MCRegisterClass &GPR = MRI->getRegClass(ARM::GPRRegClassID);
72907443 "destination register and base register can't be identical");
72917444 return false;
72927445 }
7446
7447 case ARM::MVE_VLDRBU8_rq:
7448 case ARM::MVE_VLDRBU16_rq:
7449 case ARM::MVE_VLDRBS16_rq:
7450 case ARM::MVE_VLDRBU32_rq:
7451 case ARM::MVE_VLDRBS32_rq:
7452 case ARM::MVE_VLDRHU16_rq:
7453 case ARM::MVE_VLDRHU16_rq_u:
7454 case ARM::MVE_VLDRHU32_rq:
7455 case ARM::MVE_VLDRHU32_rq_u:
7456 case ARM::MVE_VLDRHS32_rq:
7457 case ARM::MVE_VLDRHS32_rq_u:
7458 case ARM::MVE_VLDRWU32_rq:
7459 case ARM::MVE_VLDRWU32_rq_u:
7460 case ARM::MVE_VLDRDU64_rq:
7461 case ARM::MVE_VLDRDU64_rq_u:
7462 case ARM::MVE_VLDRWU32_qi:
7463 case ARM::MVE_VLDRWU32_qi_pre:
7464 case ARM::MVE_VLDRDU64_qi:
7465 case ARM::MVE_VLDRDU64_qi_pre: {
7466 // Qd must be different from Qm.
7467 unsigned QdIdx = 0, QmIdx = 2;
7468 bool QmIsPointer = false;
7469 switch (Opcode) {
7470 case ARM::MVE_VLDRWU32_qi:
7471 case ARM::MVE_VLDRDU64_qi:
7472 QmIdx = 1;
7473 QmIsPointer = true;
7474 break;
7475 case ARM::MVE_VLDRWU32_qi_pre:
7476 case ARM::MVE_VLDRDU64_qi_pre:
7477 QdIdx = 1;
7478 QmIsPointer = true;
7479 break;
7480 }
7481
7482 const unsigned Qd = MRI->getEncodingValue(Inst.getOperand(QdIdx).getReg());
7483 const unsigned Qm = MRI->getEncodingValue(Inst.getOperand(QmIdx).getReg());
7484
7485 if (Qd == Qm) {
7486 return Error(Operands[3]->getStartLoc(),
7487 Twine("destination vector register and vector ") +
7488 (QmIsPointer ? "pointer" : "offset") +
7489 " register can't be identical");
7490 }
7491 return false;
7492 }
7493
72937494 case ARM::SBFX:
72947495 case ARM::t2SBFX:
72957496 case ARM::UBFX:
1004110242 for (unsigned I = 0; I < MCID.NumOperands; ++I)
1004210243 if (MCID.OpInfo[I].RegClass == ARM::rGPRRegClassID) {
1004310244 // rGPRRegClass excludes PC, and also excluded SP before ARMv8
10044 if ((Inst.getOperand(I).getReg() == ARM::SP) && !hasV8Ops())
10245 const auto &Op = Inst.getOperand(I);
10246 if (!Op.isReg()) {
10247 // This can happen in awkward cases with tied operands, e.g. a
10248 // writeback load/store with a complex addressing mode in
10249 // which there's an output operand corresponding to the
10250 // updated written-back base register: the Tablegen-generated
10251 // AsmMatcher will have written a placeholder operand to that
10252 // slot in the form of an immediate 0, because it can't
10253 // generate the register part of the complex addressing-mode
10254 // operand ahead of time.
10255 continue;
10256 }
10257
10258 unsigned Reg = Op.getReg();
10259 if ((Reg == ARM::SP) && !hasV8Ops())
1004510260 return Match_RequiresV8;
10046 else if (Inst.getOperand(I).getReg() == ARM::PC)
10261 else if (Reg == ARM::PC)
1004710262 return Match_InvalidOperand;
1004810263 }
1004910264
331331 uint64_t Address, const void *Decoder);
332332 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
333333 uint64_t Address, const void *Decoder);
334 static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn,
335 uint64_t Address, const void *Decoder);
336 template
337 static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn,
338 uint64_t Address, const void *Decoder);
334339 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
335340 uint64_t Address, const void *Decoder);
336341 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
427432 uint64_t Address, const void *Decoder);
428433 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
429434 uint64_t Address, const void *Decoder);
435 template
436 static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val,
437 uint64_t Address, const void *Decoder);
430438 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
439 uint64_t Address, const void *Decoder);
440 template
441 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val,
442 uint64_t Address, const void *Decoder);
443 template
444 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val,
431445 uint64_t Address, const void *Decoder);
432446 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
433447 uint64_t Address, const void *Decoder);
508522 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Insn,
509523 uint64_t Address,
510524 const void *Decoder);
525 template
526 static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val,
527 uint64_t Address, const void *Decoder);
528 template
529 static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val,
530 uint64_t Address, const void *Decoder);
531 template
532 static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val,
533 uint64_t Address, const void *Decoder);
511534 template
512535 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val,
513536 uint64_t Address,
41374160 return MCDisassembler::Success;
41384161 }
41394162
4163 template
4164 static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val,
4165 uint64_t Address, const void *Decoder) {
4166 int imm = Val & 0x7F;
4167 if (Val == 0)
4168 imm = INT32_MIN;
4169 else if (!(Val & 0x80))
4170 imm *= -1;
4171 if (imm != INT32_MIN)
4172 imm <<= shift;
4173 Inst.addOperand(MCOperand::createImm(imm));
4174
4175 return MCDisassembler::Success;
4176 }
4177
41404178 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
41414179 uint64_t Address, const void *Decoder) {
41424180 DecodeStatus S = MCDisassembler::Success;
41834221 return S;
41844222 }
41854223
4224 template
4225 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val,
4226 uint64_t Address,
4227 const void *Decoder) {
4228 DecodeStatus S = MCDisassembler::Success;
4229
4230 unsigned Rn = fieldFromInstruction(Val, 8, 3);
4231 unsigned imm = fieldFromInstruction(Val, 0, 8);
4232
4233 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
4234 return MCDisassembler::Fail;
4235 if (!Check(S, DecodeT2Imm7(Inst, imm, Address, Decoder)))
4236 return MCDisassembler::Fail;
4237
4238 return S;
4239 }
4240
4241 template
4242 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val,
4243 uint64_t Address,
4244 const void *Decoder) {
4245 DecodeStatus S = MCDisassembler::Success;
4246
4247 unsigned Rn = fieldFromInstruction(Val, 8, 4);
4248 unsigned imm = fieldFromInstruction(Val, 0, 8);
4249 if (WriteBack) {
4250 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4251 return MCDisassembler::Fail;
4252 } else if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4253 return MCDisassembler::Fail;
4254 if (!Check(S, DecodeT2Imm7(Inst, imm, Address, Decoder)))
4255 return MCDisassembler::Fail;
4256
4257 return S;
4258 }
4259
41864260 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
41874261 uint64_t Address, const void *Decoder) {
41884262 DecodeStatus S = MCDisassembler::Success;
43264400 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
43274401 return MCDisassembler::Fail;
43284402 Inst.addOperand(MCOperand::createImm(add));
4403
4404 return S;
4405 }
4406
4407 static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn,
4408 uint64_t Address, const void *Decoder) {
4409 DecodeStatus S = MCDisassembler::Success;
4410 unsigned Rn = fieldFromInstruction(Insn, 3, 4);
4411 unsigned Qm = fieldFromInstruction(Insn, 0, 3);
4412
4413 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4414 return MCDisassembler::Fail;
4415 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
4416 return MCDisassembler::Fail;
4417
4418 return S;
4419 }
4420
4421 template
4422 static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn,
4423 uint64_t Address, const void *Decoder) {
4424 DecodeStatus S = MCDisassembler::Success;
4425 unsigned Qm = fieldFromInstruction(Insn, 8, 3);
4426 int imm = fieldFromInstruction(Insn, 0, 7);
4427
4428 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
4429 return MCDisassembler::Fail;
4430
4431 if(!fieldFromInstruction(Insn, 7, 1)) {
4432 if (imm == 0)
4433 imm = INT32_MIN; // indicate -0
4434 else
4435 imm *= -1;
4436 }
4437 if (imm != INT32_MIN)
4438 imm <<= shift;
4439 Inst.addOperand(MCOperand::createImm(imm));
43294440
43304441 return S;
43314442 }
61746285 return S;
61756286 }
61766287
6288 static inline DecodeStatus DecodeMVE_MEM_pre(
6289 MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder,
6290 unsigned Rn, OperandDecoder RnDecoder, OperandDecoder AddrDecoder) {
6291 DecodeStatus S = MCDisassembler::Success;
6292
6293 unsigned Qd = fieldFromInstruction(Val, 13, 3);
6294 unsigned addr = fieldFromInstruction(Val, 0, 7) |
6295 (fieldFromInstruction(Val, 23, 1) << 7) | (Rn << 8);
6296
6297 if (!Check(S, RnDecoder(Inst, Rn, Address, Decoder)))
6298 return MCDisassembler::Fail;
6299 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
6300 return MCDisassembler::Fail;
6301 if (!Check(S, AddrDecoder(Inst, addr, Address, Decoder)))
6302 return MCDisassembler::Fail;
6303
6304 return S;
6305 }
6306
6307 template
6308 static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val,
6309 uint64_t Address, const void *Decoder) {
6310 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder,
6311 fieldFromInstruction(Val, 16, 3),
6312 DecodetGPRRegisterClass,
6313 DecodeTAddrModeImm7);
6314 }
6315
6316 template
6317 static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val,
6318 uint64_t Address, const void *Decoder) {
6319 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder,
6320 fieldFromInstruction(Val, 16, 4),
6321 DecoderGPRRegisterClass,
6322 DecodeT2AddrModeImm7);
6323 }
6324
6325 template
6326 static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val,
6327 uint64_t Address, const void *Decoder) {
6328 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder,
6329 fieldFromInstruction(Val, 17, 3),
6330 DecodeMQPRRegisterClass,
6331 DecodeMveAddrModeQ);
6332 }
6333
61776334 template
61786335 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val,
61796336 uint64_t Address,
2929 lsl,
3030 lsr,
3131 ror,
32 rrx
32 rrx,
33 uxtw
3334 };
3435
3536 enum AddrOpc {
4748 case ARM_AM::lsr: return "lsr";
4849 case ARM_AM::ror: return "ror";
4950 case ARM_AM::rrx: return "rrx";
51 case ARM_AM::uxtw: return "uxtw";
5052 }
5153 }
5254
202202 AddrMode5FP16 = 17, // i8 * 2
203203 AddrModeT2_ldrex = 18, // i8 * 4, with unscaled offset in MCInst
204204 AddrModeT2_i7s4 = 19, // i7 * 4
205 AddrModeT2_i7s2 = 20, // i7 * 2
206 AddrModeT2_i7 = 21, // i7 * 1
205207 };
206208
207209 inline static const char *AddrModeToString(AddrMode addrmode) {
226228 case AddrMode_i12: return "AddrMode_i12";
227229 case AddrModeT2_ldrex:return "AddrModeT2_ldrex";
228230 case AddrModeT2_i7s4: return "AddrModeT2_i7s4";
231 case AddrModeT2_i7s2: return "AddrModeT2_i7s2";
232 case AddrModeT2_i7: return "AddrModeT2_i7";
229233 }
230234 }
231235
602602 << markup(">");
603603 }
604604
605 template
606 void ARMInstPrinter::printMveAddrModeRQOperand(const MCInst *MI, unsigned OpNum,
607 const MCSubtargetInfo &STI,
608 raw_ostream &O) {
609 const MCOperand &MO1 = MI->getOperand(OpNum);
610 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
611
612 O << markup("
613 printRegName(O, MO1.getReg());
614 O << ", ";
615 printRegName(O, MO2.getReg());
616
617 if (shift > 0)
618 printRegImmShift(O, ARM_AM::uxtw, shift, UseMarkup);
619
620 O << "]" << markup(">");
621 }
622
623 void ARMInstPrinter::printMveAddrModeQOperand(const MCInst *MI, unsigned OpNum,
624 const MCSubtargetInfo &STI,
625 raw_ostream &O) {
626 const MCOperand &MO1 = MI->getOperand(OpNum);
627 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
628
629 O << markup("
630 printRegName(O, MO1.getReg());
631
632 int64_t Imm = MO2.getImm();
633 if (Imm != 0)
634 O << ", " << markup("");
635
636 O << "]" << markup(">");
637 }
638
605639 void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
606640 const MCSubtargetInfo &STI,
607641 raw_ostream &O) {
254254 raw_ostream &O);
255255 void printVPTMask(const MCInst *MI, unsigned OpNum,
256256 const MCSubtargetInfo &STI, raw_ostream &O);
257 template
258 void printMveAddrModeRQOperand(const MCInst *MI, unsigned OpNum,
259 const MCSubtargetInfo &STI, raw_ostream &O);
260 void printMveAddrModeQOperand(const MCInst *MI, unsigned OpNum,
261 const MCSubtargetInfo &STI, raw_ostream &O);
257262 void printExpandedImmOperand(const MCInst *MI, unsigned OpNum,
258263 const MCSubtargetInfo &STI, raw_ostream &O);
259264
207207 SmallVectorImpl &Fixups,
208208 const MCSubtargetInfo &STI) const;
209209
210 /// getMveAddrModeRQOpValue - Return encoding info for 'reg, vreg'
211 /// operand.
212 uint32_t getMveAddrModeRQOpValue(const MCInst &MI, unsigned OpIdx,
213 SmallVectorImpl &Fixups,
214 const MCSubtargetInfo &STI) const;
215
216 /// getMveAddrModeQOpValue - Return encoding info for 'reg +/- imm7<<{shift}'
217 /// operand.
218 template
219 uint32_t getMveAddrModeQOpValue(const MCInst &MI, unsigned OpIdx,
220 SmallVectorImpl &Fixups,
221 const MCSubtargetInfo &STI) const;
222
210223 /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
211224 /// operand as needed by load/store instructions.
212225 uint32_t getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx,
237250 case ARM_AM::asr: return 2;
238251 case ARM_AM::ror:
239252 case ARM_AM::rrx: return 3;
253 case ARM_AM::uxtw:
254 default:
255 llvm_unreachable("Invalid ShiftOpc!");
240256 }
241 llvm_unreachable("Invalid ShiftOpc!");
242257 }
243258
244259 /// getAddrMode2OffsetOpValue - Return encoding for am2offset operands.
337352 unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
338353 SmallVectorImpl &Fixups,
339354 const MCSubtargetInfo &STI) const;
340 unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
355 template
356 unsigned getT2AddrModeImmOpValue(const MCInst &MI, unsigned OpNum,
341357 SmallVectorImpl &Fixups,
342358 const MCSubtargetInfo &STI) const;
343359 unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
10391055 Binary |= (1U << Bits);
10401056 return Binary;
10411057 }
1058
1059 /// getMveAddrModeRQOpValue - Return encoding info for 'reg, vreg'
1060 /// operand.
1061 uint32_t ARMMCCodeEmitter::
1062 getMveAddrModeRQOpValue(const MCInst &MI, unsigned OpIdx,
1063 SmallVectorImpl &Fixups,
1064 const MCSubtargetInfo &STI) const {
1065 // {6-3} Rn
1066 // {2-0} Qm
1067 const MCOperand &M0 = MI.getOperand(OpIdx);
1068 const MCOperand &M1 = MI.getOperand(OpIdx + 1);
1069
1070 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(M0.getReg());
1071 unsigned Qm = CTX.getRegisterInfo()->getEncodingValue(M1.getReg());
1072
1073 assert(Qm < 8 && "Qm is supposed to be encodable in 3 bits");
1074
1075 return (Rn << 3) | Qm;
1076 }
1077
1078 /// getMveAddrModeRQOpValue - Return encoding info for 'reg, vreg'
1079 /// operand.
1080 template
1081 uint32_t ARMMCCodeEmitter::
1082 getMveAddrModeQOpValue(const MCInst &MI, unsigned OpIdx,
1083 SmallVectorImpl &Fixups,
1084 const MCSubtargetInfo &STI) const {
1085 // {10-8} Qm
1086 // {7-0} Imm
1087 const MCOperand &M0 = MI.getOperand(OpIdx);
1088 const MCOperand &M1 = MI.getOperand(OpIdx + 1);
1089
1090 unsigned Qm = CTX.getRegisterInfo()->getEncodingValue(M0.getReg());
1091 int32_t Imm = M1.getImm();
1092
1093 bool isAdd = Imm >= 0;
1094
1095 Imm >>= shift;
1096
1097 if (!isAdd)
1098 Imm = -(uint32_t)Imm;
1099
1100 Imm &= 0x7f;
1101
1102 if (isAdd)
1103 Imm |= 0x80;
1104
1105 assert(Qm < 8 && "Qm is supposed to be encodable in 3 bits");
1106
1107 return (Qm << 8) | Imm;
1108 }
1109
10421110 /// getT2AddrModeImm8s4OpValue - Return encoding info for
10431111 /// 'reg +/- imm8<<2' operand.
10441112 uint32_t ARMMCCodeEmitter::
15391607 return Value;
15401608 }
15411609
1610 template
15421611 unsigned ARMMCCodeEmitter::
1543 getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
1544 SmallVectorImpl &Fixups,
1545 const MCSubtargetInfo &STI) const {
1612 getT2AddrModeImmOpValue(const MCInst &MI, unsigned OpNum,
1613 SmallVectorImpl &Fixups,
1614 const MCSubtargetInfo &STI) const {
15461615 const MCOperand &MO1 = MI.getOperand(OpNum);
15471616 const MCOperand &MO2 = MI.getOperand(OpNum+1);
15481617
15491618 // FIXME: Needs fixup support.
15501619 unsigned Value = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg());
15511620
1552 // Even though the immediate is 8 bits long, we need 9 bits in order
1621 // If the immediate is B bits long, we need B+1 bits in order
15531622 // to represent the (inverse of the) sign bit.
1554 Value <<= 9;
1555 int32_t tmp = (int32_t)MO2.getImm();
1623 Value <<= (Bits + 1);
1624 int32_t tmp = (int32_t)MO2.getImm() >> Shift;
15561625 if (tmp < 0)
15571626 tmp = abs(tmp);
15581627 else
1559 Value |= 256; // Set the ADD bit
1560 Value |= tmp & 255;
1628 Value |= (1U << Bits); // Set the ADD bit
1629 Value |= tmp & ((1U << Bits) - 1);
15611630 return Value;
15621631 }
15631632
609609 Offset = -Offset;
610610 isSub = true;
611611 }
612 } else if (AddrMode == ARMII::AddrModeT2_i7s4) {
612 } else if (AddrMode == ARMII::AddrModeT2_i7s4 ||
613 AddrMode == ARMII::AddrModeT2_i7s2 ||
614 AddrMode == ARMII::AddrModeT2_i7) {
613615 Offset += MI.getOperand(FrameRegIdx + 1).getImm();
614 NumBits = 9; // 7 bits scaled by 4
615 unsigned OffsetMask = 0x3;
616 unsigned OffsetMask;
617 switch (AddrMode) {
618 case ARMII::AddrModeT2_i7s4: NumBits = 9; OffsetMask = 0x3; break;
619 case ARMII::AddrModeT2_i7s2: NumBits = 8; OffsetMask = 0x1; break;
620 default: NumBits = 7; OffsetMask = 0x0; break;
621 }
616622 // MCInst operand expects already scaled value.
617623 Scale = 1;
618624 assert((Offset & OffsetMask) == 0 && "Can't encode this offset!");
619625 (void)OffsetMask; // squash unused-variable warning at -NDEBUG
620626 } else if (AddrMode == ARMII::AddrModeT2_i8s4) {
621627 Offset += MI.getOperand(FrameRegIdx + 1).getImm() * 4;
622 NumBits = 10; // 8 bits scaled by 4
628 NumBits = 8 + 2;
623629 // MCInst operand expects already scaled value.
624630 Scale = 1;
625631 assert((Offset & 3) == 0 && "Can't encode this offset!");
0 # RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve -show-encoding < %s 2>%t \
1 # RUN: | FileCheck --check-prefix=CHECK %s
2 # RUN: FileCheck --check-prefix=ERROR < %t %s
3 # RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -show-encoding < %s 2>%t
4 # RUN: FileCheck --check-prefix=ERROR-NOMVE < %t %s
5
6 # CHECK: vldrb.u8 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1e]
7 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
8 vldrb.u8 q0, [r0]
9
10 # CHECK: vldrb.u8 q1, [r0] @ encoding: [0x90,0xed,0x00,0x3e]
11 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
12 vldrb.u8 q1, [r0]
13
14 # CHECK: vldrb.u8 q0, [r11] @ encoding: [0x9b,0xed,0x00,0x1e]
15 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
16 vldrb.u8 q0, [r11]
17
18 # CHECK: vldrb.u8 q3, [r11] @ encoding: [0x9b,0xed,0x00,0x7e]
19 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
20 vldrb.u8 q3, [r11]
21
22 # CHECK: vldrb.u8 q0, [r4, #56] @ encoding: [0x94,0xed,0x38,0x1e]
23 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
24 vldrb.u8 q0, [r4, #56]
25
26 # CHECK: vldrb.u8 q4, [r4, #56] @ encoding: [0x94,0xed,0x38,0x9e]
27 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
28 vldrb.u8 q4, [r4, #56]
29
30 # CHECK: vldrb.u8 q0, [r8, #56] @ encoding: [0x98,0xed,0x38,0x1e]
31 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
32 vldrb.u8 q0, [r8, #56]
33
34 # CHECK: vldrb.u8 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xbe]
35 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
36 vldrb.u8 q5, [r4, #56]!
37
38 # CHECK: vldrb.u8 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xbe]
39 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
40 vldrb.u8 q5, [r4, #56]!
41
42 # CHECK: vldrb.u8 q5, [r4], #-25 @ encoding: [0x34,0xec,0x19,0xbe]
43 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
44 vldrb.u8 q5, [r4], #-25
45
46 # CHECK: vldrb.u8 q5, [r10], #-25 @ encoding: [0x3a,0xec,0x19,0xbe]
47 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
48 vldrb.u8 q5, [r10], #-25
49
50 # CHECK: vldrb.u8 q5, [sp, #-25] @ encoding: [0x1d,0xed,0x19,0xbe]
51 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
52 vldrb.u8 q5, [sp, #-25]
53
54 # CHECK: vldrb.u8 q5, [sp, #-127] @ encoding: [0x1d,0xed,0x7f,0xbe]
55 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
56 vldrb.u8 q5, [sp, #-127]
57
58 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
59 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
60 vldrb.u8 q0, [r0, #128]
61
62 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
63 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
64 vldrb.u8 q0, [r0, #-128]!
65
66 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
67 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
68 vldrb.u8 q0, [r0], #128
69
70 # CHECK: vstrb.8 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1e]
71 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
72 vstrb.8 q0, [r0]
73
74 # CHECK: vstrb.8 q1, [r0] @ encoding: [0x80,0xed,0x00,0x3e]
75 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
76 vstrb.8 q1, [r0]
77
78 # CHECK: vstrb.8 q0, [r11] @ encoding: [0x8b,0xed,0x00,0x1e]
79 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
80 vstrb.8 q0, [r11]
81
82 # CHECK: vstrb.8 q3, [r11] @ encoding: [0x8b,0xed,0x00,0x7e]
83 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
84 vstrb.8 q3, [r11]
85
86 # CHECK: vstrb.8 q0, [r4, #56] @ encoding: [0x84,0xed,0x38,0x1e]
87 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
88 vstrb.8 q0, [r4, #56]
89
90 # CHECK: vstrb.8 q4, [r4, #56] @ encoding: [0x84,0xed,0x38,0x9e]
91 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
92 vstrb.8 q4, [r4, #56]
93
94 # CHECK: vstrb.8 q0, [r8, #56] @ encoding: [0x88,0xed,0x38,0x1e]
95 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
96 vstrb.8 q0, [r8, #56]
97
98 # CHECK: vstrb.8 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xbe]
99 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
100 vstrb.8 q5, [r4, #56]!
101
102 # CHECK: vstrb.8 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xbe]
103 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
104 vstrb.8 q5, [r4, #56]!
105
106 # CHECK: vstrb.8 q5, [r4], #-25 @ encoding: [0x24,0xec,0x19,0xbe]
107 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
108 vstrb.8 q5, [r4], #-25
109
110 # CHECK: vstrb.8 q5, [r10], #-25 @ encoding: [0x2a,0xec,0x19,0xbe]
111 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
112 vstrb.8 q5, [r10], #-25
113
114 # CHECK: vstrb.8 q5, [sp, #-25] @ encoding: [0x0d,0xed,0x19,0xbe]
115 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
116 vstrb.8 q5, [sp, #-25]
117
118 # CHECK: vstrb.8 q5, [sp, #127] @ encoding: [0x8d,0xed,0x7f,0xbe]
119 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
120 vstrb.8 q5, [sp, #127]
121
122 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
123 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
124 vstrb.u8 q0, [r0, #128]
125
126 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
127 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
128 vstrb.u8 q0, [r0, #-128]!
129
130 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
131 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
132 vstrb.u8 q0, [r0], #128
133
134 # CHECK: vldrb.u16 q0, [r0] @ encoding: [0x90,0xfd,0x80,0x0e]
135 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
136 vldrb.u16 q0, [r0]
137
138 # CHECK: vldrb.u16 q1, [r0] @ encoding: [0x90,0xfd,0x80,0x2e]
139 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
140 vldrb.u16 q1, [r0]
141
142 # CHECK: vldrb.u16 q0, [r7] @ encoding: [0x97,0xfd,0x80,0x0e]
143 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
144 vldrb.u16 q0, [r7]
145
146 # CHECK: vldrb.u16 q3, [r7] @ encoding: [0x97,0xfd,0x80,0x6e]
147 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
148 vldrb.u16 q3, [r7]
149
150 # CHECK: vldrb.u16 q0, [r4, #56] @ encoding: [0x94,0xfd,0xb8,0x0e]
151 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
152 vldrb.u16 q0, [r4, #56]
153
154 # CHECK: vldrb.u16 q4, [r4, #56] @ encoding: [0x94,0xfd,0xb8,0x8e]
155 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
156 vldrb.u16 q4, [r4, #56]
157
158 # CHECK: vldrb.u16 q0, [r2, #56] @ encoding: [0x92,0xfd,0xb8,0x0e]
159 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
160 vldrb.u16 q0, [r2, #56]
161
162 # CHECK: vldrb.u16 q5, [r4, #56]! @ encoding: [0xb4,0xfd,0xb8,0xae]
163 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
164 vldrb.u16 q5, [r4, #56]!
165
166 # CHECK: vldrb.u16 q5, [r4, #56]! @ encoding: [0xb4,0xfd,0xb8,0xae]
167 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
168 vldrb.u16 q5, [r4, #56]!
169
170 # CHECK: vldrb.u16 q5, [r4], #-1 @ encoding: [0x34,0xfc,0x81,0xae]
171 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
172 vldrb.u16 q5, [r4], #-1
173
174 # CHECK: vldrb.u16 q5, [r3], #-25 @ encoding: [0x33,0xfc,0x99,0xae]
175 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
176 vldrb.u16 q5, [r3], #-25
177
178 # CHECK: vldrb.u16 q5, [r6, #-25] @ encoding: [0x16,0xfd,0x99,0xae]
179 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
180 vldrb.u16 q5, [r6, #-25]
181
182 # CHECK: vldrb.u16 q5, [r6, #-64] @ encoding: [0x16,0xfd,0xc0,0xae]
183 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
184 vldrb.u16 q5, [r6, #-64]
185
186 # CHECK: vldrb.s16 q0, [r0] @ encoding: [0x90,0xed,0x80,0x0e]
187 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
188 vldrb.s16 q0, [r0]
189
190 # CHECK: vldrb.s16 q1, [r0] @ encoding: [0x90,0xed,0x80,0x2e]
191 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
192 vldrb.s16 q1, [r0]
193
194 # CHECK: vldrb.s16 q0, [r7] @ encoding: [0x97,0xed,0x80,0x0e]
195 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
196 vldrb.s16 q0, [r7]
197
198 # CHECK: vldrb.s16 q3, [r7] @ encoding: [0x97,0xed,0x80,0x6e]
199 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
200 vldrb.s16 q3, [r7]
201
202 # CHECK: vldrb.s16 q0, [r4, #56] @ encoding: [0x94,0xed,0xb8,0x0e]
203 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
204 vldrb.s16 q0, [r4, #56]
205
206 # CHECK: vldrb.s16 q4, [r4, #56] @ encoding: [0x94,0xed,0xb8,0x8e]
207 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
208 vldrb.s16 q4, [r4, #56]
209
210 # CHECK: vldrb.s16 q0, [r2, #56] @ encoding: [0x92,0xed,0xb8,0x0e]
211 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
212 vldrb.s16 q0, [r2, #56]
213
214 # CHECK: vldrb.s16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0xb8,0xae]
215 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
216 vldrb.s16 q5, [r4, #56]!
217
218 # CHECK: vldrb.s16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0xb8,0xae]
219 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
220 vldrb.s16 q5, [r4, #56]!
221
222 # CHECK: vldrb.s16 q5, [r4], #-25 @ encoding: [0x34,0xec,0x99,0xae]
223 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
224 vldrb.s16 q5, [r4], #-25
225
226 # CHECK: vldrb.s16 q5, [r3], #-25 @ encoding: [0x33,0xec,0x99,0xae]
227 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
228 vldrb.s16 q5, [r3], #-25
229
230 # CHECK: vldrb.s16 q5, [r6, #-25] @ encoding: [0x16,0xed,0x99,0xae]
231 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
232 vldrb.s16 q5, [r6, #-25]
233
234 # CHECK: vldrb.s16 q5, [r6, #-64] @ encoding: [0x16,0xed,0xc0,0xae]
235 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
236 vldrb.s16 q5, [r6, #-64]
237
238 # CHECK: vstrb.16 q0, [r0] @ encoding: [0x80,0xed,0x80,0x0e]
239 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
240 vstrb.16 q0, [r0]
241
242 # CHECK: vstrb.16 q1, [r0] @ encoding: [0x80,0xed,0x80,0x2e]
243 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
244 vstrb.16 q1, [r0]
245
246 # CHECK: vstrb.16 q0, [r7] @ encoding: [0x87,0xed,0x80,0x0e]
247 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
248 vstrb.16 q0, [r7]
249
250 # CHECK: vstrb.16 q3, [r7] @ encoding: [0x87,0xed,0x80,0x6e]
251 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
252 vstrb.16 q3, [r7]
253
254 # CHECK: vstrb.16 q0, [r4, #56] @ encoding: [0x84,0xed,0xb8,0x0e]
255 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
256 vstrb.16 q0, [r4, #56]
257
258 # CHECK: vstrb.16 q4, [r4, #56] @ encoding: [0x84,0xed,0xb8,0x8e]
259 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
260 vstrb.16 q4, [r4, #56]
261
262 # CHECK: vstrb.16 q0, [r5, #56] @ encoding: [0x85,0xed,0xb8,0x0e]
263 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
264 vstrb.16 q0, [r5, #56]
265
266 # CHECK: vstrb.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0xb8,0xae]
267 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
268 vstrb.16 q5, [r4, #56]!
269
270 # CHECK: vstrb.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0xb8,0xae]
271 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
272 vstrb.16 q5, [r4, #56]!
273
274 # CHECK: vstrb.16 q5, [r4], #-25 @ encoding: [0x24,0xec,0x99,0xae]
275 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
276 vstrb.16 q5, [r4], #-25
277
278 # CHECK: vstrb.16 q5, [r3], #-25 @ encoding: [0x23,0xec,0x99,0xae]
279 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
280 vstrb.16 q5, [r3], #-25
281
282 # CHECK: vstrb.16 q5, [r2, #-25] @ encoding: [0x02,0xed,0x99,0xae]
283 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
284 vstrb.16 q5, [r2, #-25]
285
286 # CHECK: vstrb.16 q5, [r2, #-64] @ encoding: [0x02,0xed,0xc0,0xae]
287 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
288 vstrb.16 q5, [r2, #-64]
289
290 # CHECK: vldrb.u32 q0, [r0] @ encoding: [0x90,0xfd,0x00,0x0f]
291 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
292 vldrb.u32 q0, [r0]
293
294 # CHECK: vldrb.u32 q1, [r0] @ encoding: [0x90,0xfd,0x00,0x2f]
295 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
296 vldrb.u32 q1, [r0]
297
298 # CHECK: vldrb.u32 q0, [r7] @ encoding: [0x97,0xfd,0x00,0x0f]
299 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
300 vldrb.u32 q0, [r7]
301
302 # CHECK: vldrb.u32 q3, [r7] @ encoding: [0x97,0xfd,0x00,0x6f]
303 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
304 vldrb.u32 q3, [r7]
305
306 # CHECK: vldrb.u32 q0, [r4, #56] @ encoding: [0x94,0xfd,0x38,0x0f]
307 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
308 vldrb.u32 q0, [r4, #56]
309
310 # CHECK: vldrb.u32 q4, [r4, #56] @ encoding: [0x94,0xfd,0x38,0x8f]
311 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
312 vldrb.u32 q4, [r4, #56]
313
314 # CHECK: vldrb.u32 q0, [r2, #56] @ encoding: [0x92,0xfd,0x38,0x0f]
315 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
316 vldrb.u32 q0, [r2, #56]
317
318 # CHECK: vldrb.u32 q5, [r4, #56]! @ encoding: [0xb4,0xfd,0x38,0xaf]
319 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
320 vldrb.u32 q5, [r4, #56]!
321
322 # CHECK: vldrb.u32 q5, [r4, #56]! @ encoding: [0xb4,0xfd,0x38,0xaf]
323 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
324 vldrb.u32 q5, [r4, #56]!
325
326 # CHECK: vldrb.u32 q5, [r4], #-25 @ encoding: [0x34,0xfc,0x19,0xaf]
327 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
328 vldrb.u32 q5, [r4], #-25
329
330 # CHECK: vldrb.u32 q5, [r3], #-25 @ encoding: [0x33,0xfc,0x19,0xaf]
331 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
332 vldrb.u32 q5, [r3], #-25
333
334 # CHECK: vldrb.u32 q5, [r6, #-25] @ encoding: [0x16,0xfd,0x19,0xaf]
335 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
336 vldrb.u32 q5, [r6, #-25]
337
338 # CHECK: vldrb.u32 q5, [r6, #-64] @ encoding: [0x16,0xfd,0x40,0xaf]
339 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
340 vldrb.u32 q5, [r6, #-64]
341
342 # CHECK: vldrb.s32 q0, [r0] @ encoding: [0x90,0xed,0x00,0x0f]
343 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
344 vldrb.s32 q0, [r0]
345
346 # CHECK: vldrb.s32 q1, [r0] @ encoding: [0x90,0xed,0x00,0x2f]
347 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
348 vldrb.s32 q1, [r0]
349
350 # CHECK: vldrb.s32 q0, [r7] @ encoding: [0x97,0xed,0x00,0x0f]
351 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
352 vldrb.s32 q0, [r7]
353
354 # CHECK: vldrb.s32 q3, [r7] @ encoding: [0x97,0xed,0x00,0x6f]
355 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
356 vldrb.s32 q3, [r7]
357
358 # CHECK: vldrb.s32 q0, [r4, #56] @ encoding: [0x94,0xed,0x38,0x0f]
359 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
360 vldrb.s32 q0, [r4, #56]
361
362 # CHECK: vldrb.s32 q4, [r4, #56] @ encoding: [0x94,0xed,0x38,0x8f]
363 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
364 vldrb.s32 q4, [r4, #56]
365
366 # CHECK: vldrb.s32 q0, [r2, #56] @ encoding: [0x92,0xed,0x38,0x0f]
367 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
368 vldrb.s32 q0, [r2, #56]
369
370 # CHECK: vldrb.s32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xaf]
371 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
372 vldrb.s32 q5, [r4, #56]!
373
374 # CHECK: vldrb.s32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xaf]
375 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
376 vldrb.s32 q5, [r4, #56]!
377
378 # CHECK: vldrb.s32 q5, [r4], #-25 @ encoding: [0x34,0xec,0x19,0xaf]
379 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
380 vldrb.s32 q5, [r4], #-25
381
382 # CHECK: vldrb.s32 q5, [r3], #-25 @ encoding: [0x33,0xec,0x19,0xaf]
383 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
384 vldrb.s32 q5, [r3], #-25
385
386 # CHECK: vldrb.s32 q5, [r6, #-25] @ encoding: [0x16,0xed,0x19,0xaf]
387 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
388 vldrb.s32 q5, [r6, #-25]
389
390 # CHECK: vldrb.s32 q5, [r6, #-64] @ encoding: [0x16,0xed,0x40,0xaf]
391 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
392 vldrb.s32 q5, [r6, #-64]
393
394 # CHECK: vstrb.32 q0, [r0] @ encoding: [0x80,0xed,0x00,0x0f]
395 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
396 vstrb.32 q0, [r0]
397
398 # CHECK: vstrb.32 q1, [r0] @ encoding: [0x80,0xed,0x00,0x2f]
399 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
400 vstrb.32 q1, [r0]
401
402 # CHECK: vstrb.32 q0, [r7] @ encoding: [0x87,0xed,0x00,0x0f]
403 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
404 vstrb.32 q0, [r7]
405
406 # CHECK: vstrb.32 q3, [r7] @ encoding: [0x87,0xed,0x00,0x6f]
407 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
408 vstrb.32 q3, [r7]
409
410 # CHECK: vstrb.32 q0, [r4, #56] @ encoding: [0x84,0xed,0x38,0x0f]
411 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
412 vstrb.32 q0, [r4, #56]
413
414 # CHECK: vstrb.32 q4, [r4, #56] @ encoding: [0x84,0xed,0x38,0x8f]
415 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
416 vstrb.32 q4, [r4, #56]
417
418 # CHECK: vstrb.32 q0, [r5, #56] @ encoding: [0x85,0xed,0x38,0x0f]
419 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
420 vstrb.32 q0, [r5, #56]
421
422 # CHECK: vstrb.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xaf]
423 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
424 vstrb.32 q5, [r4, #56]!
425
426 # CHECK: vstrb.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xaf]
427 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
428 vstrb.32 q5, [r4, #56]!
429
430 # CHECK: vstrb.32 q5, [r4], #-25 @ encoding: [0x24,0xec,0x19,0xaf]
431 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
432 vstrb.32 q5, [r4], #-25
433
434 # CHECK: vstrb.32 q5, [r3], #-25 @ encoding: [0x23,0xec,0x19,0xaf]
435 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
436 vstrb.32 q5, [r3], #-25
437
438 # CHECK: vstrb.32 q5, [r2, #-25] @ encoding: [0x02,0xed,0x19,0xaf]
439 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
440 vstrb.32 q5, [r2, #-25]
441
442 # CHECK: vstrb.32 q5, [r2, #-64] @ encoding: [0x02,0xed,0x40,0xaf]
443 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
444 vstrb.32 q5, [r2, #-64]
445
446 # CHECK: vldrh.u16 q0, [r0] @ encoding: [0x90,0xed,0x80,0x1e]
447 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
448 vldrh.u16 q0, [r0]
449
450 # CHECK: vldrh.u16 q1, [r0] @ encoding: [0x90,0xed,0x80,0x3e]
451 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
452 vldrh.u16 q1, [r0]
453
454 # CHECK: vldrh.u16 q0, [r11] @ encoding: [0x9b,0xed,0x80,0x1e]
455 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
456 vldrh.u16 q0, [r11]
457
458 # CHECK: vldrh.u16 q3, [r11] @ encoding: [0x9b,0xed,0x80,0x7e]
459 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
460 vldrh.u16 q3, [r11]
461
462 # CHECK: vldrh.u16 q0, [r4, #56] @ encoding: [0x94,0xed,0x9c,0x1e]
463 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
464 vldrh.u16 q0, [r4, #56]
465
466 # CHECK: vldrh.u16 q4, [r4, #56] @ encoding: [0x94,0xed,0x9c,0x9e]
467 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
468 vldrh.u16 q4, [r4, #56]
469
470 # CHECK: vldrh.u16 q0, [r8, #56] @ encoding: [0x98,0xed,0x9c,0x1e]
471 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
472 vldrh.u16 q0, [r8, #56]
473
474 # CHECK: vldrh.u16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x9c,0xbe]
475 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
476 vldrh.u16 q5, [r4, #56]!
477
478 # CHECK: vldrh.u16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x9c,0xbe]
479 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
480 vldrh.u16 q5, [r4, #56]!
481
482 # CHECK: vldrh.u16 q5, [r4], #-26 @ encoding: [0x34,0xec,0x8d,0xbe]
483 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
484 vldrh.u16 q5, [r4], #-26
485
486 # CHECK: vldrh.u16 q5, [r10], #-26 @ encoding: [0x3a,0xec,0x8d,0xbe]
487 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
488 vldrh.u16 q5, [r10], #-26
489
490 # CHECK: vldrh.u16 q5, [sp, #-26] @ encoding: [0x1d,0xed,0x8d,0xbe]
491 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
492 vldrh.u16 q5, [sp, #-26]
493
494 # CHECK: vldrh.u16 q5, [sp, #-64] @ encoding: [0x1d,0xed,0xa0,0xbe]
495 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
496 vldrh.u16 q5, [sp, #-64]
497
498 # CHECK: vldrh.u16 q5, [sp, #-254] @ encoding: [0x1d,0xed,0xff,0xbe]
499 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
500 vldrh.u16 q5, [sp, #-254]
501
502 # CHECK: vldrh.u16 q5, [r10], #254 @ encoding: [0xba,0xec,0xff,0xbe]
503 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
504 vldrh.u16 q5, [r10], #254
505
506 # CHECK: vstrh.16 q0, [r0] @ encoding: [0x80,0xed,0x80,0x1e]
507 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
508 vstrh.16 q0, [r0]
509
510 # CHECK: vstrh.16 q1, [r0] @ encoding: [0x80,0xed,0x80,0x3e]
511 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
512 vstrh.16 q1, [r0]
513
514 # CHECK: vstrh.16 q0, [r11] @ encoding: [0x8b,0xed,0x80,0x1e]
515 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
516 vstrh.16 q0, [r11]
517
518 # CHECK: vstrh.16 q3, [r11] @ encoding: [0x8b,0xed,0x80,0x7e]
519 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
520 vstrh.16 q3, [r11]
521
522 # CHECK: vstrh.16 q0, [r4, #56] @ encoding: [0x84,0xed,0x9c,0x1e]
523 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
524 vstrh.16 q0, [r4, #56]
525
526 # CHECK: vstrh.16 q4, [r4, #56] @ encoding: [0x84,0xed,0x9c,0x9e]
527 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
528 vstrh.16 q4, [r4, #56]
529
530 # CHECK: vstrh.16 q0, [r8, #56] @ encoding: [0x88,0xed,0x9c,0x1e]
531 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
532 vstrh.16 q0, [r8, #56]
533
534 # CHECK: vstrh.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x9c,0xbe]
535 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
536 vstrh.16 q5, [r4, #56]!
537
538 # CHECK: vstrh.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x9c,0xbe]
539 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
540 vstrh.16 q5, [r4, #56]!
541
542 # CHECK: vstrh.16 q5, [r4], #-26 @ encoding: [0x24,0xec,0x8d,0xbe]
543 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
544 vstrh.16 q5, [r4], #-26
545
546 # CHECK: vstrh.16 q5, [r10], #-26 @ encoding: [0x2a,0xec,0x8d,0xbe]
547 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
548 vstrh.16 q5, [r10], #-26
549
550 # CHECK: vstrh.16 q5, [sp, #-26] @ encoding: [0x0d,0xed,0x8d,0xbe]
551 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
552 vstrh.16 q5, [sp, #-26]
553
554 # CHECK: vstrh.16 q5, [sp, #-64] @ encoding: [0x0d,0xed,0xa0,0xbe]
555 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
556 vstrh.16 q5, [sp, #-64]
557
558 # CHECK: vstrh.16 q5, [sp, #-254] @ encoding: [0x0d,0xed,0xff,0xbe]
559 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
560 vstrh.16 q5, [sp, #-254]
561
562 # CHECK: vstrh.16 q5, [r10], #254 @ encoding: [0xaa,0xec,0xff,0xbe]
563 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
564 vstrh.16 q5, [r10], #254
565
566 # CHECK: vldrh.u32 q0, [r0] @ encoding: [0x98,0xfd,0x00,0x0f]
567 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
568 vldrh.u32 q0, [r0]
569
570 # CHECK: vldrh.u32 q1, [r0] @ encoding: [0x98,0xfd,0x00,0x2f]
571 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
572 vldrh.u32 q1, [r0]
573
574 # CHECK: vldrh.u32 q0, [r7] @ encoding: [0x9f,0xfd,0x00,0x0f]
575 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
576 vldrh.u32 q0, [r7]
577
578 # CHECK: vldrh.u32 q3, [r7] @ encoding: [0x9f,0xfd,0x00,0x6f]
579 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
580 vldrh.u32 q3, [r7]
581
582 # CHECK: vldrh.u32 q0, [r4, #56] @ encoding: [0x9c,0xfd,0x1c,0x0f]
583 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
584 vldrh.u32 q0, [r4, #56]
585
586 # CHECK: vldrh.u32 q4, [r4, #56] @ encoding: [0x9c,0xfd,0x1c,0x8f]
587 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
588 vldrh.u32 q4, [r4, #56]
589
590 # CHECK: vldrh.u32 q0, [r2, #56] @ encoding: [0x9a,0xfd,0x1c,0x0f]
591 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
592 vldrh.u32 q0, [r2, #56]
593
594 # CHECK: vldrh.u32 q5, [r4, #56]! @ encoding: [0xbc,0xfd,0x1c,0xaf]
595 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
596 vldrh.u32 q5, [r4, #56]!
597
598 # CHECK: vldrh.u32 q5, [r4, #56]! @ encoding: [0xbc,0xfd,0x1c,0xaf]
599 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
600 vldrh.u32 q5, [r4, #56]!
601
602 # CHECK: vldrh.u32 q5, [r4], #-26 @ encoding: [0x3c,0xfc,0x0d,0xaf]
603 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
604 vldrh.u32 q5, [r4], #-26
605
606 # CHECK: vldrh.u32 q5, [r3], #-26 @ encoding: [0x3b,0xfc,0x0d,0xaf]
607 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
608 vldrh.u32 q5, [r3], #-26
609
610 # CHECK: vldrh.u32 q5, [r6, #-26] @ encoding: [0x1e,0xfd,0x0d,0xaf]
611 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
612 vldrh.u32 q5, [r6, #-26]
613
614 # CHECK: vldrh.u32 q5, [r6, #-64] @ encoding: [0x1e,0xfd,0x20,0xaf]
615 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
616 vldrh.u32 q5, [r6, #-64]
617
618 # CHECK: vldrh.u32 q5, [r6, #-254] @ encoding: [0x1e,0xfd,0x7f,0xaf]
619 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
620 vldrh.u32 q5, [r6, #-254]
621
622 # CHECK: vldrh.u32 q5, [r4, #254]! @ encoding: [0xbc,0xfd,0x7f,0xaf]
623 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
624 vldrh.u32 q5, [r4, #254]!
625
626 # CHECK: vldrh.s32 q0, [r0] @ encoding: [0x98,0xed,0x00,0x0f]
627 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
628 vldrh.s32 q0, [r0]
629
630 # CHECK: vldrh.s32 q1, [r0] @ encoding: [0x98,0xed,0x00,0x2f]
631 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
632 vldrh.s32 q1, [r0]
633
634 # CHECK: vldrh.s32 q0, [r7] @ encoding: [0x9f,0xed,0x00,0x0f]
635 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
636 vldrh.s32 q0, [r7]
637
638 # CHECK: vldrh.s32 q3, [r7] @ encoding: [0x9f,0xed,0x00,0x6f]
639 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
640 vldrh.s32 q3, [r7]
641
642 # CHECK: vldrh.s32 q0, [r4, #56] @ encoding: [0x9c,0xed,0x1c,0x0f]
643 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
644 vldrh.s32 q0, [r4, #56]
645
646 # CHECK: vldrh.s32 q4, [r4, #56] @ encoding: [0x9c,0xed,0x1c,0x8f]
647 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
648 vldrh.s32 q4, [r4, #56]
649
650 # CHECK: vldrh.s32 q0, [r2, #56] @ encoding: [0x9a,0xed,0x1c,0x0f]
651 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
652 vldrh.s32 q0, [r2, #56]
653
654 # CHECK: vldrh.s32 q5, [r4, #56]! @ encoding: [0xbc,0xed,0x1c,0xaf]
655 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
656 vldrh.s32 q5, [r4, #56]!
657
658 # CHECK: vldrh.s32 q5, [r4, #56]! @ encoding: [0xbc,0xed,0x1c,0xaf]
659 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
660 vldrh.s32 q5, [r4, #56]!
661
662 # CHECK: vldrh.s32 q5, [r4], #-26 @ encoding: [0x3c,0xec,0x0d,0xaf]
663 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
664 vldrh.s32 q5, [r4], #-26
665
666 # CHECK: vldrh.s32 q5, [r3], #-26 @ encoding: [0x3b,0xec,0x0d,0xaf]
667 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
668 vldrh.s32 q5, [r3], #-26
669
670 # CHECK: vldrh.s32 q5, [r6, #-26] @ encoding: [0x1e,0xed,0x0d,0xaf]
671 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
672 vldrh.s32 q5, [r6, #-26]
673
674 # CHECK: vldrh.s32 q5, [r6, #-64] @ encoding: [0x1e,0xed,0x20,0xaf]
675 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
676 vldrh.s32 q5, [r6, #-64]
677
678 # CHECK: vldrh.s32 q5, [r6, #-254] @ encoding: [0x1e,0xed,0x7f,0xaf]
679 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
680 vldrh.s32 q5, [r6, #-254]
681
682 # CHECK: vldrh.s32 q5, [r4, #254]! @ encoding: [0xbc,0xed,0x7f,0xaf]
683 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
684 vldrh.s32 q5, [r4, #254]!
685
686 # CHECK: vstrh.32 q0, [r0] @ encoding: [0x88,0xed,0x00,0x0f]
687 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
688 vstrh.32 q0, [r0]
689
690 # CHECK: vstrh.32 q1, [r0] @ encoding: [0x88,0xed,0x00,0x2f]
691 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
692 vstrh.32 q1, [r0]
693
694 # CHECK: vstrh.32 q0, [r7] @ encoding: [0x8f,0xed,0x00,0x0f]
695 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
696 vstrh.32 q0, [r7]
697
698 # CHECK: vstrh.32 q3, [r7] @ encoding: [0x8f,0xed,0x00,0x6f]
699 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
700 vstrh.32 q3, [r7]
701
702 # CHECK: vstrh.32 q0, [r4, #56] @ encoding: [0x8c,0xed,0x1c,0x0f]
703 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
704 vstrh.32 q0, [r4, #56]
705
706 # CHECK: vstrh.32 q4, [r4, #56] @ encoding: [0x8c,0xed,0x1c,0x8f]
707 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
708 vstrh.32 q4, [r4, #56]
709
710 # CHECK: vstrh.32 q0, [r5, #56] @ encoding: [0x8d,0xed,0x1c,0x0f]
711 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
712 vstrh.32 q0, [r5, #56]
713
714 # CHECK: vstrh.32 q5, [r4, #56]! @ encoding: [0xac,0xed,0x1c,0xaf]
715 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
716 vstrh.32 q5, [r4, #56]!
717
718 # CHECK: vstrh.32 q5, [r4, #56]! @ encoding: [0xac,0xed,0x1c,0xaf]
719 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
720 vstrh.32 q5, [r4, #56]!
721
722 # CHECK: vstrh.32 q5, [r4], #-26 @ encoding: [0x2c,0xec,0x0d,0xaf]
723 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
724 vstrh.32 q5, [r4], #-26
725
726 # CHECK: vstrh.32 q5, [r3], #-26 @ encoding: [0x2b,0xec,0x0d,0xaf]
727 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
728 vstrh.32 q5, [r3], #-26
729
730 # CHECK: vstrh.32 q5, [r2, #-26] @ encoding: [0x0a,0xed,0x0d,0xaf]
731 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
732 vstrh.32 q5, [r2, #-26]
733
734 # CHECK: vstrh.32 q5, [r2, #-64] @ encoding: [0x0a,0xed,0x20,0xaf]
735 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
736 vstrh.32 q5, [r2, #-64]
737
738 # CHECK: vstrh.32 q5, [r2, #-254] @ encoding: [0x0a,0xed,0x7f,0xaf]
739 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
740 vstrh.32 q5, [r2, #-254]
741
742 # CHECK: vstrh.32 q5, [r4, #254]! @ encoding: [0xac,0xed,0x7f,0xaf]
743 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
744 vstrh.32 q5, [r4, #254]!
745
746 # CHECK: vldrw.u32 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1f]
747 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
748 vldrw.u32 q0, [r0]
749
750 # CHECK: vldrw.u32 q1, [r0] @ encoding: [0x90,0xed,0x00,0x3f]
751 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
752 vldrw.u32 q1, [r0]
753
754 # CHECK: vldrw.u32 q0, [r11] @ encoding: [0x9b,0xed,0x00,0x1f]
755 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
756 vldrw.u32 q0, [r11]
757
758 # CHECK: vldrw.u32 q3, [r11] @ encoding: [0x9b,0xed,0x00,0x7f]
759 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
760 vldrw.u32 q3, [r11]
761
762 # CHECK: vldrw.u32 q0, [r4, #56] @ encoding: [0x94,0xed,0x0e,0x1f]
763 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
764 vldrw.u32 q0, [r4, #56]
765
766 # CHECK: vldrw.u32 q4, [r4, #56] @ encoding: [0x94,0xed,0x0e,0x9f]
767 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
768 vldrw.u32 q4, [r4, #56]
769
770 # CHECK: vldrw.u32 q0, [r8, #56] @ encoding: [0x98,0xed,0x0e,0x1f]
771 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
772 vldrw.u32 q0, [r8, #56]
773
774 # CHECK: vldrw.u32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x0e,0xbf]
775 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
776 vldrw.u32 q5, [r4, #56]!
777
778 # CHECK: vldrw.u32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x0e,0xbf]
779 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
780 vldrw.u32 q5, [r4, #56]!
781
782 # CHECK: vldrw.u32 q5, [r4], #-28 @ encoding: [0x34,0xec,0x07,0xbf]
783 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
784 vldrw.u32 q5, [r4], #-28
785
786 # CHECK: vldrw.u32 q5, [r10], #-28 @ encoding: [0x3a,0xec,0x07,0xbf]
787 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
788 vldrw.u32 q5, [r10], #-28
789
790 # CHECK: vldrw.u32 q5, [sp, #-28] @ encoding: [0x1d,0xed,0x07,0xbf]
791 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
792 vldrw.u32 q5, [sp, #-28]
793
794 # CHECK: vldrw.u32 q5, [sp, #-64] @ encoding: [0x1d,0xed,0x10,0xbf]
795 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
796 vldrw.u32 q5, [sp, #-64]
797
798 # CHECK: vldrw.u32 q5, [sp, #-508] @ encoding: [0x1d,0xed,0x7f,0xbf]
799 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
800 vldrw.u32 q5, [sp, #-508]
801
802 # CHECK: vldrw.u32 q5, [r4, #508]! @ encoding: [0xb4,0xed,0x7f,0xbf]
803 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
804 vldrw.u32 q5, [r4, #508]!
805
806 # CHECK: vstrw.32 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1f]
807 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
808 vstrw.32 q0, [r0]
809
810 # CHECK: vstrw.32 q1, [r0] @ encoding: [0x80,0xed,0x00,0x3f]
811 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
812 vstrw.32 q1, [r0]
813
814 # CHECK: vstrw.32 q0, [r11] @ encoding: [0x8b,0xed,0x00,0x1f]
815 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
816 vstrw.32 q0, [r11]
817
818 # CHECK: vstrw.32 q3, [r11] @ encoding: [0x8b,0xed,0x00,0x7f]
819 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
820 vstrw.32 q3, [r11]
821
822 # CHECK: vstrw.32 q0, [r4, #56] @ encoding: [0x84,0xed,0x0e,0x1f]
823 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
824 vstrw.32 q0, [r4, #56]
825
826 # CHECK: vstrw.32 q4, [r4, #56] @ encoding: [0x84,0xed,0x0e,0x9f]
827 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
828 vstrw.32 q4, [r4, #56]
829
830 # CHECK: vstrw.32 q0, [r8, #56] @ encoding: [0x88,0xed,0x0e,0x1f]
831 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
832 vstrw.32 q0, [r8, #56]
833
834 # CHECK: vstrw.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x0e,0xbf]
835 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
836 vstrw.32 q5, [r4, #56]!
837
838 # CHECK: vstrw.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x0e,0xbf]
839 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
840 vstrw.32 q5, [r4, #56]!
841
842 # CHECK: vstrw.32 q5, [r4], #-28 @ encoding: [0x24,0xec,0x07,0xbf]
843 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
844 vstrw.32 q5, [r4], #-28
845
846 # CHECK: vstrw.32 q5, [r10], #-28 @ encoding: [0x2a,0xec,0x07,0xbf]
847 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
848 vstrw.32 q5, [r10], #-28
849
850 # CHECK: vstrw.32 q5, [sp, #-28] @ encoding: [0x0d,0xed,0x07,0xbf]
851 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
852 vstrw.32 q5, [sp, #-28]
853
854 # CHECK: vstrw.32 q5, [sp, #-64] @ encoding: [0x0d,0xed,0x10,0xbf]
855 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
856 vstrw.32 q5, [sp, #-64]
857
858 # CHECK: vstrw.32 q5, [sp, #-508] @ encoding: [0x0d,0xed,0x7f,0xbf]
859 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
860 vstrw.32 q5, [sp, #-508]
861
862 # CHECK: vstrw.32 q5, [r4, #508]! @ encoding: [0xa4,0xed,0x7f,0xbf]
863 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
864 vstrw.32 q5, [r4, #508]!
865
866 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
867 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
868 vstrb.16 q0, [r8]
869
870 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
871 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
872 vldrh.u32 q0, [r8]
873
874 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
875 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
876 vstrw.32 q5, [sp, #-64]!
877
878 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
879 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
880 vstrw.32 q5, [sp, #-3]
881
882 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
883 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
884 vstrw.32 q5, [sp, #512]
885
886 # CHECK: vldrb.u8 q0, [r0, q1] @ encoding: [0x90,0xfc,0x02,0x0e]
887 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
888 vldrb.u8 q0, [r0, q1]
889
890 # CHECK: vldrb.u8 q3, [r10, q1] @ encoding: [0x9a,0xfc,0x02,0x6e]
891 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
892 vldrb.u8 q3, [r10, q1]
893
894 # CHECK: vldrb.u16 q0, [r0, q1] @ encoding: [0x90,0xfc,0x82,0x0e]
895 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
896 vldrb.u16 q0, [r0, q1]
897
898 # CHECK: vldrb.u16 q3, [r9, q1] @ encoding: [0x99,0xfc,0x82,0x6e]
899 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
900 vldrb.u16 q3, [r9, q1]
901
902 # CHECK: vldrb.s16 q0, [r0, q1] @ encoding: [0x90,0xec,0x82,0x0e]
903 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
904 vldrb.s16 q0, [r0, q1]
905
906 # CHECK: vldrb.s16 q3, [sp, q1] @ encoding: [0x9d,0xec,0x82,0x6e]
907 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
908 vldrb.s16 q3, [sp, q1]
909
910 # CHECK: vldrb.u32 q0, [r0, q1] @ encoding: [0x90,0xfc,0x02,0x0f]
911 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
912 vldrb.u32 q0, [r0, q1]
913
914 # CHECK: vldrb.u32 q3, [r0, q1] @ encoding: [0x90,0xfc,0x02,0x6f]
915 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
916 vldrb.u32 q3, [r0, q1]
917
918 # CHECK: vldrb.s32 q0, [r0, q1] @ encoding: [0x90,0xec,0x02,0x0f]
919 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
920 vldrb.s32 q0, [r0, q1]
921
922 # CHECK: vldrb.s32 q3, [r0, q1] @ encoding: [0x90,0xec,0x02,0x6f]
923 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
924 vldrb.s32 q3, [r0, q1]
925
926 # CHECK: vldrh.u16 q0, [r0, q1] @ encoding: [0x90,0xfc,0x92,0x0e]
927 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
928 vldrh.u16 q0, [r0, q1]
929
930 # CHECK: vldrh.u16 q3, [r0, q1] @ encoding: [0x90,0xfc,0x92,0x6e]
931 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
932 vldrh.u16 q3, [r0, q1]
933
934 # CHECK: vldrh.u32 q0, [r0, q1] @ encoding: [0x90,0xfc,0x12,0x0f]
935 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
936 vldrh.u32 q0, [r0, q1]
937
938 # CHECK: vldrh.u32 q3, [r0, q1] @ encoding: [0x90,0xfc,0x12,0x6f]
939 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
940 vldrh.u32 q3, [r0, q1]
941
942 # CHECK: vldrh.s32 q0, [r0, q1] @ encoding: [0x90,0xec,0x12,0x0f]
943 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
944 vldrh.s32 q0, [r0, q1]
945
946 # CHECK: vldrh.s32 q3, [r0, q1] @ encoding: [0x90,0xec,0x12,0x6f]
947 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
948 vldrh.s32 q3, [r0, q1]
949
950 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical
951 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
952 vldrb.u8 q0, [r0, q0]
953
954 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical
955 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
956 vldrb.u16 q0, [r0, q0]
957
958 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical
959 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
960 vldrb.s16 q0, [r0, q0]
961
962 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical
963 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
964 vldrb.u32 q0, [r0, q0]
965
966 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical
967 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
968 vldrb.s32 q0, [r0, q0]
969
970 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical
971 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
972 vldrh.u16 q0, [r0, q0]
973
974 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical
975 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
976 vldrh.u32 q0, [r0, q0]
977
978 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical
979 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
980 vldrh.s32 q0, [r0, q0]
981
982 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical
983 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
984 vldrh.u16 q0, [r0, q0, uxtw #1]
985
986 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical
987 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
988 vldrh.u32 q0, [r0, q0, uxtw #1]
989
990 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical
991 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
992 vldrh.s32 q0, [r0, q0, uxtw #1]
993
994 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical
995 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
996 vldrw.u32 q0, [r0, q0]
997
998 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical
999 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1000 vldrw.u32 q0, [r0, q0, uxtw #2]
1001
1002 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical
1003 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1004 vldrd.u64 q0, [r0, q0]
1005
1006 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector offset register can't be identical
1007 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1008 vldrd.u64 q0, [r0, q0, uxtw #3]
1009
1010 # CHECK: vldrh.u16 q0, [r0, q1, uxtw #1] @ encoding: [0x90,0xfc,0x93,0x0e]
1011 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1012 vldrh.u16 q0, [r0, q1, uxtw #1]
1013
1014 # CHECK: vldrw.u32 q0, [r0, q1] @ encoding: [0x90,0xfc,0x42,0x0f]
1015 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1016 vldrw.u32 q0, [r0, q1]
1017
1018 # CHECK: vldrw.u32 q3, [r0, q1] @ encoding: [0x90,0xfc,0x42,0x6f]
1019 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1020 vldrw.u32 q3, [r0, q1]
1021
1022 # CHECK: vldrw.u32 q0, [r0, q1, uxtw #2] @ encoding: [0x90,0xfc,0x43,0x0f]
1023 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1024 vldrw.u32 q0, [r0, q1, uxtw #2]
1025
1026 # CHECK: vldrw.u32 q0, [sp, q1, uxtw #2] @ encoding: [0x9d,0xfc,0x43,0x0f]
1027 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1028 vldrw.u32 q0, [sp, q1, uxtw #2]
1029
1030 # CHECK: vldrd.u64 q0, [r0, q1] @ encoding: [0x90,0xfc,0xd2,0x0f]
1031 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1032 vldrd.u64 q0, [r0, q1]
1033
1034 # CHECK: vldrd.u64 q3, [r0, q1] @ encoding: [0x90,0xfc,0xd2,0x6f]
1035 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1036 vldrd.u64 q3, [r0, q1]
1037
1038 # CHECK: vldrd.u64 q0, [r0, q1, uxtw #3] @ encoding: [0x90,0xfc,0xd3,0x0f]
1039 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1040 vldrd.u64 q0, [r0, q1, uxtw #3]
1041
1042 # CHECK: vldrd.u64 q0, [sp, q1, uxtw #3] @ encoding: [0x9d,0xfc,0xd3,0x0f]
1043 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1044 vldrd.u64 q0, [sp, q1, uxtw #3]
1045
1046 # CHECK: vstrb.8 q0, [r0, q1] @ encoding: [0x80,0xec,0x02,0x0e]
1047 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1048 vstrb.8 q0, [r0, q1]
1049
1050 # CHECK: vstrb.8 q3, [r10, q1] @ encoding: [0x8a,0xec,0x02,0x6e]
1051 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1052 vstrb.8 q3, [r10, q1]
1053
1054 # CHECK: vstrb.8 q3, [r0, q3] @ encoding: [0x80,0xec,0x06,0x6e]
1055 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1056 vstrb.8 q3, [r0, q3]
1057
1058 # CHECK: vstrb.16 q0, [r0, q1] @ encoding: [0x80,0xec,0x82,0x0e]
1059 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1060 vstrb.16 q0, [r0, q1]
1061
1062 # CHECK: vstrb.16 q3, [sp, q1] @ encoding: [0x8d,0xec,0x82,0x6e]
1063 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1064 vstrb.16 q3, [sp, q1]
1065
1066 # CHECK: vstrb.16 q3, [r0, q3] @ encoding: [0x80,0xec,0x86,0x6e]
1067 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1068 vstrb.16 q3, [r0, q3]
1069
1070 # CHECK: vstrb.32 q0, [r0, q1] @ encoding: [0x80,0xec,0x02,0x0f]
1071 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1072 vstrb.32 q0, [r0, q1]
1073
1074 # CHECK: vstrb.32 q3, [r0, q1] @ encoding: [0x80,0xec,0x02,0x6f]
1075 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1076 vstrb.32 q3, [r0, q1]
1077
1078 # CHECK: vstrb.32 q3, [r0, q3] @ encoding: [0x80,0xec,0x06,0x6f]
1079 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1080 vstrb.32 q3, [r0, q3]
1081
1082 # CHECK: vstrh.16 q0, [r0, q1] @ encoding: [0x80,0xec,0x92,0x0e]
1083 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1084 vstrh.16 q0, [r0, q1]
1085
1086 # CHECK: vstrh.16 q3, [r0, q1] @ encoding: [0x80,0xec,0x92,0x6e]
1087 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1088 vstrh.16 q3, [r0, q1]
1089
1090 # CHECK: vstrh.16 q3, [r0, q3] @ encoding: [0x80,0xec,0x96,0x6e]
1091 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1092 vstrh.16 q3, [r0, q3]
1093
1094 # CHECK: vstrh.32 q0, [r0, q1] @ encoding: [0x80,0xec,0x12,0x0f]
1095 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1096 vstrh.32 q0, [r0, q1]
1097
1098 # CHECK: vstrh.32 q3, [r0, q1] @ encoding: [0x80,0xec,0x12,0x6f]
1099 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1100 vstrh.32 q3, [r0, q1]
1101
1102 # CHECK: vstrh.32 q3, [r0, q3] @ encoding: [0x80,0xec,0x16,0x6f]
1103 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1104 vstrh.32 q3, [r0, q3]
1105
1106 # CHECK: vstrh.16 q0, [r0, q1, uxtw #1] @ encoding: [0x80,0xec,0x93,0x0e]
1107 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1108 vstrh.16 q0, [r0, q1, uxtw #1]
1109
1110 # CHECK: vstrh.32 q3, [r8, q3, uxtw #1] @ encoding: [0x88,0xec,0x17,0x6f]
1111 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1112 vstrh.32 q3, [r8, q3, uxtw #1]
1113
1114 # CHECK: vstrw.32 q0, [r0, q1] @ encoding: [0x80,0xec,0x42,0x0f]
1115 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1116 vstrw.32 q0, [r0, q1]
1117
1118 # CHECK: vstrw.32 q3, [r0, q1] @ encoding: [0x80,0xec,0x42,0x6f]
1119 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1120 vstrw.32 q3, [r0, q1]
1121
1122 # CHECK: vstrw.32 q3, [r0, q3] @ encoding: [0x80,0xec,0x46,0x6f]
1123 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1124 vstrw.32 q3, [r0, q3]
1125
1126 # CHECK: vstrw.32 q0, [r0, q1, uxtw #2] @ encoding: [0x80,0xec,0x43,0x0f]
1127 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1128 vstrw.32 q0, [r0, q1, uxtw #2]
1129
1130 # CHECK: vstrw.32 q0, [sp, q1, uxtw #2] @ encoding: [0x8d,0xec,0x43,0x0f]
1131 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1132 vstrw.32 q0, [sp, q1, uxtw #2]
1133
1134 # CHECK: vstrd.64 q0, [r0, q1] @ encoding: [0x80,0xec,0xd2,0x0f]
1135 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1136 vstrd.64 q0, [r0, q1]
1137
1138 # CHECK: vstrd.64 q3, [r0, q1] @ encoding: [0x80,0xec,0xd2,0x6f]
1139 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1140 vstrd.64 q3, [r0, q1]
1141
1142 # CHECK: vstrd.64 q3, [r0, q3] @ encoding: [0x80,0xec,0xd6,0x6f]
1143 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1144 vstrd.64 q3, [r0, q3]
1145
1146 # CHECK: vstrd.64 q0, [r0, q1, uxtw #3] @ encoding: [0x80,0xec,0xd3,0x0f]
1147 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1148 vstrd.64 q0, [r0, q1, uxtw #3]
1149
1150 # CHECK: vstrd.64 q0, [sp, q1, uxtw #3] @ encoding: [0x8d,0xec,0xd3,0x0f]
1151 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1152 vstrd.64 q0, [sp, q1, uxtw #3]
1153
1154 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: operand must be a register in range [q0, q7]
1155 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1156 vstrw.32 q9, [sp, q1, uxtw #2]
1157
1158 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
1159 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1160 vstrh.16 q3, [pc, q1]
1161
1162 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
1163 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1164 vstrd.64 q0, [r0, q1, uxtw #1]
1165
1166 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
1167 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1168 vldrd.u64 q0, [r0, q1, uxtw #1]
1169
1170 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
1171 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1172 vstrd.64 q0, [r0, q1, uxtw #2]
1173
1174 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
1175 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1176 vldrd.u64 q0, [r0, q1, uxtw #2]
1177
1178 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
1179 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1180 vldrw.u32 q0, [r0, q1, uxtw #1]
1181
1182 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
1183 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1184 vstrh.16 q0, [r0, q1, uxtw #2]
1185
1186 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
1187 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1188 vstrb.32 q0, [r11, q1, uxtw #1]
1189
1190 # CHECK: vldrw.u32 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1e]
1191 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1192 vldrw.u32 q0, [q1]
1193
1194 # CHECK: vldrw.u32 q7, [q1] @ encoding: [0x92,0xfd,0x00,0xfe]
1195 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1196 vldrw.u32 q7, [q1]
1197
1198 # CHECK: vldrw.u32 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xfe]
1199 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1200 vldrw.u32 q7, [q1]!
1201
1202 # CHECK: vldrw.u32 q7, [q1, #4] @ encoding: [0x92,0xfd,0x01,0xfe]
1203 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1204 vldrw.u32 q7, [q1, #4]
1205
1206 # CHECK: vldrw.u32 q7, [q1, #-4] @ encoding: [0x12,0xfd,0x01,0xfe]
1207 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1208 vldrw.u32 q7, [q1, #-4]
1209
1210 # CHECK: vldrw.u32 q7, [q1, #508] @ encoding: [0x92,0xfd,0x7f,0xfe]
1211 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1212 vldrw.u32 q7, [q1, #508]
1213
1214 # CHECK: vldrw.u32 q7, [q1, #-508] @ encoding: [0x12,0xfd,0x7f,0xfe]
1215 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1216 vldrw.u32 q7, [q1, #-508]
1217
1218 # CHECK: vldrw.u32 q7, [q1, #264] @ encoding: [0x92,0xfd,0x42,0xfe]
1219 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1220 vldrw.u32 q7, [q1, #264]
1221
1222 # CHECK: vldrw.u32 q7, [q1, #4]! @ encoding: [0xb2,0xfd,0x01,0xfe]
1223 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1224 vldrw.u32 q7, [q1, #4]!
1225
1226 # CHECK: vstrw.32 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1e]
1227 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1228 vstrw.32 q0, [q1]
1229
1230 # CHECK: vstrw.32 q1, [q1] @ encoding: [0x82,0xfd,0x00,0x3e]
1231 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1232 vstrw.32 q1, [q1]
1233
1234 # CHECK: vstrw.32 q7, [q1] @ encoding: [0x82,0xfd,0x00,0xfe]
1235 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1236 vstrw.32 q7, [q1]
1237
1238 # CHECK: vstrw.32 q7, [q1]! @ encoding: [0xa2,0xfd,0x00,0xfe]
1239 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1240 vstrw.32 q7, [q1]!
1241
1242 # CHECK: vstrw.32 q7, [q7] @ encoding: [0x8e,0xfd,0x00,0xfe]
1243 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1244 vstrw.32 q7, [q7]
1245
1246 # CHECK: vstrw.32 q7, [q1, #4] @ encoding: [0x82,0xfd,0x01,0xfe]
1247 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1248 vstrw.32 q7, [q1, #4]
1249
1250 # CHECK: vstrw.32 q7, [q1, #-4] @ encoding: [0x02,0xfd,0x01,0xfe]
1251 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1252 vstrw.32 q7, [q1, #-4]
1253
1254 # CHECK: vstrw.32 q7, [q1, #508] @ encoding: [0x82,0xfd,0x7f,0xfe]
1255 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1256 vstrw.32 q7, [q1, #508]
1257
1258 # CHECK: vstrw.32 q7, [q1, #-508] @ encoding: [0x02,0xfd,0x7f,0xfe]
1259 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1260 vstrw.32 q7, [q1, #-508]
1261
1262 # CHECK: vstrw.32 q7, [q1, #264]! @ encoding: [0xa2,0xfd,0x42,0xfe]
1263 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1264 vstrw.32 q7, [q1, #264]!
1265
1266 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: operand must be a register in range [q0, q7]
1267 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1268 vstrw.32 q8, [q1]!
1269
1270 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
1271 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1272 vstrw.32 q4, [q1, #3]!
1273
1274 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
1275 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1276 vldrw.u32 q7, [q1, #512]
1277
1278 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector pointer register can't be identical
1279 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1280 vldrw.32 q1, [q1, #264]
1281
1282 # CHECK: vldrd.u64 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1f]
1283 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1284 vldrd.u64 q0, [q1]
1285
1286 # CHECK: vldrd.u64 q7, [q1] @ encoding: [0x92,0xfd,0x00,0xff]
1287 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1288 vldrd.u64 q7, [q1]
1289
1290 # CHECK: vldrd.u64 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xff]
1291 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1292 vldrd.u64 q7, [q1]!
1293
1294 # CHECK: vldrd.u64 q7, [q1, #8] @ encoding: [0x92,0xfd,0x01,0xff]
1295 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1296 vldrd.u64 q7, [q1, #8]
1297
1298 # CHECK: vldrd.u64 q7, [q1, #-8] @ encoding: [0x12,0xfd,0x01,0xff]
1299 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1300 vldrd.u64 q7, [q1, #-8]
1301
1302 # CHECK: vldrd.u64 q7, [q1, #1016] @ encoding: [0x92,0xfd,0x7f,0xff]
1303 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1304 vldrd.u64 q7, [q1, #1016]
1305
1306 # CHECK: vldrd.u64 q7, [q1, #-1016] @ encoding: [0x12,0xfd,0x7f,0xff]
1307 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1308 vldrd.u64 q7, [q1, #-1016]
1309
1310 # CHECK: vldrd.u64 q7, [q1, #264] @ encoding: [0x92,0xfd,0x21,0xff]
1311 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1312 vldrd.u64 q7, [q1, #264]
1313
1314 # CHECK: vldrd.u64 q7, [q1, #624] @ encoding: [0x92,0xfd,0x4e,0xff]
1315 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1316 vldrd.u64 q7, [q1, #624]
1317
1318 # CHECK: vldrd.u64 q7, [q1, #264] @ encoding: [0x92,0xfd,0x21,0xff]
1319 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1320 vldrd.u64 q7, [q1, #264]
1321
1322 # CHECK: vldrd.u64 q7, [q1, #-1016]! @ encoding: [0x32,0xfd,0x7f,0xff]
1323 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1324 vldrd.u64 q7, [q1, #-1016]!
1325
1326 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: destination vector register and vector pointer register can't be identical
1327 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1328 vldrd.u64 q6, [q6]
1329
1330 # CHECK: vstrd.64 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1f]
1331 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1332 vstrd.64 q0, [q1]
1333
1334 # CHECK: vstrd.64 q1, [q1] @ encoding: [0x82,0xfd,0x00,0x3f]
1335 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1336 vstrd.64 q1, [q1]
1337
1338 # CHECK: vstrd.64 q7, [q1] @ encoding: [0x82,0xfd,0x00,0xff]
1339 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1340 vstrd.64 q7, [q1]
1341
1342 # CHECK: vstrd.64 q7, [q1]! @ encoding: [0xa2,0xfd,0x00,0xff]
1343 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1344 vstrd.64 q7, [q1]!
1345
1346 # CHECK: vstrd.64 q7, [q7] @ encoding: [0x8e,0xfd,0x00,0xff]
1347 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1348 vstrd.64 q7, [q7]
1349
1350 # CHECK: vstrd.64 q7, [q1, #8] @ encoding: [0x82,0xfd,0x01,0xff]
1351 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1352 vstrd.64 q7, [q1, #8]
1353
1354 # CHECK: vstrd.64 q7, [q1, #-8]! @ encoding: [0x22,0xfd,0x01,0xff]
1355 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1356 vstrd.64 q7, [q1, #-8]!
1357
1358 # CHECK: vstrd.64 q7, [q1, #1016] @ encoding: [0x82,0xfd,0x7f,0xff]
1359 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1360 vstrd.64 q7, [q1, #1016]
1361
1362 # CHECK: vstrd.64 q7, [q1, #-1016] @ encoding: [0x02,0xfd,0x7f,0xff]
1363 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1364 vstrd.64 q7, [q1, #-1016]
1365
1366 # CHECK: vstrd.64 q7, [q1, #264] @ encoding: [0x82,0xfd,0x21,0xff]
1367 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1368 vstrd.64 q7, [q1, #264]
1369
1370 # CHECK: vstrd.64 q7, [q1, #624] @ encoding: [0x82,0xfd,0x4e,0xff]
1371 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1372 vstrd.64 q7, [q1, #624]
1373
1374 # CHECK: vstrd.64 q7, [q1, #264] @ encoding: [0x82,0xfd,0x21,0xff]
1375 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1376 vstrd.64 q7, [q1, #264]
1377
1378 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: operand must be a register in range [q0, q7]
1379 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1380 vldrd.u64 q8, [q1]!
1381
1382 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
1383 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1384 vstrd.64 q7, [q1, #1024]
1385
1386 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
1387 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1388 vstrd.64 q4, [q1, #3]
1389
1390 # ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
1391 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1392 vstrd.64 q4, [q1, #4]
1393
1394 # CHECK: vldrb.u8 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1e]
1395 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1396 vldrb.s8 q0, [r0]
1397
1398 # CHECK: vldrb.u8 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1e]
1399 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1400 vldrb.8 q0, [r0]
1401
1402 # CHECK: vldrb.u8 q0, [r8, #56] @ encoding: [0x98,0xed,0x38,0x1e]
1403 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1404 vldrb.s8 q0, [r8, #56]
1405
1406 # CHECK: vldrb.u8 q0, [r8, #56] @ encoding: [0x98,0xed,0x38,0x1e]
1407 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1408 vldrb.8 q0, [r8, #56]
1409
1410 # CHECK: vldrb.u8 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xbe]
1411 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1412 vldrb.s8 q5, [r4, #56]!
1413
1414 # CHECK: vldrb.u8 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x38,0xbe]
1415 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1416 vldrb.8 q5, [r4, #56]!
1417
1418 # CHECK: vstrb.8 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1e]
1419 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1420 vstrb.u8 q0, [r0]
1421
1422 # CHECK: vstrb.8 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1e]
1423 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1424 vstrb.s8 q0, [r0]
1425
1426 # CHECK: vstrb.8 q4, [r4, #56] @ encoding: [0x84,0xed,0x38,0x9e]
1427 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1428 vstrb.u8 q4, [r4, #56]
1429
1430 # CHECK: vstrb.8 q4, [r4, #56] @ encoding: [0x84,0xed,0x38,0x9e]
1431 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1432 vstrb.s8 q4, [r4, #56]
1433
1434 # CHECK: vstrb.8 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xbe]
1435 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1436 vstrb.u8 q5, [r4, #56]!
1437
1438 # CHECK: vstrb.8 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x38,0xbe]
1439 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1440 vstrb.s8 q5, [r4, #56]!
1441
1442 # CHECK: vldrh.u16 q0, [r0] @ encoding: [0x90,0xed,0x80,0x1e]
1443 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1444 vldrh.s16 q0, [r0]
1445
1446 # CHECK: vldrh.u16 q0, [r0] @ encoding: [0x90,0xed,0x80,0x1e]
1447 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1448 vldrh.f16 q0, [r0]
1449
1450 # CHECK: vldrh.u16 q0, [r0] @ encoding: [0x90,0xed,0x80,0x1e]
1451 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1452 vldrh.16 q0, [r0]
1453
1454 # CHECK: vldrh.u16 q0, [r4, #56] @ encoding: [0x94,0xed,0x9c,0x1e]
1455 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1456 vldrh.s16 q0, [r4, #56]
1457
1458 # CHECK: vldrh.u16 q0, [r4, #56] @ encoding: [0x94,0xed,0x9c,0x1e]
1459 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1460 vldrh.f16 q0, [r4, #56]
1461
1462 # CHECK: vldrh.u16 q0, [r4, #56] @ encoding: [0x94,0xed,0x9c,0x1e]
1463 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1464 vldrh.16 q0, [r4, #56]
1465
1466 # CHECK: vldrh.u16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x9c,0xbe]
1467 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1468 vldrh.s16 q5, [r4, #56]!
1469
1470 # CHECK: vldrh.u16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x9c,0xbe]
1471 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1472 vldrh.f16 q5, [r4, #56]!
1473
1474 # CHECK: vldrh.u16 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x9c,0xbe]
1475 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1476 vldrh.16 q5, [r4, #56]!
1477
1478 # CHECK: vstrh.16 q0, [r0] @ encoding: [0x80,0xed,0x80,0x1e]
1479 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1480 vstrh.u16 q0, [r0]
1481
1482 # CHECK: vstrh.16 q0, [r0] @ encoding: [0x80,0xed,0x80,0x1e]
1483 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1484 vstrh.s16 q0, [r0]
1485
1486 # CHECK: vstrh.16 q0, [r0] @ encoding: [0x80,0xed,0x80,0x1e]
1487 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1488 vstrh.f16 q0, [r0]
1489
1490 # CHECK: vstrh.16 q0, [r4, #56] @ encoding: [0x84,0xed,0x9c,0x1e]
1491 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1492 vstrh.u16 q0, [r4, #56]
1493
1494 # CHECK: vstrh.16 q0, [r4, #56] @ encoding: [0x84,0xed,0x9c,0x1e]
1495 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1496 vstrh.s16 q0, [r4, #56]
1497
1498 # CHECK: vstrh.16 q0, [r4, #56] @ encoding: [0x84,0xed,0x9c,0x1e]
1499 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1500 vstrh.f16 q0, [r4, #56]
1501
1502 # CHECK: vstrh.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x9c,0xbe]
1503 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1504 vstrh.u16 q5, [r4, #56]!
1505
1506 # CHECK: vstrh.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x9c,0xbe]
1507 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1508 vstrh.s16 q5, [r4, #56]!
1509
1510 # CHECK: vstrh.16 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x9c,0xbe]
1511 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1512 vstrh.f16 q5, [r4, #56]!
1513
1514 # CHECK: vldrw.u32 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1f]
1515 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1516 vldrw.s32 q0, [r0]
1517
1518 # CHECK: vldrw.u32 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1f]
1519 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1520 vldrw.f32 q0, [r0]
1521
1522 # CHECK: vldrw.u32 q0, [r0] @ encoding: [0x90,0xed,0x00,0x1f]
1523 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1524 vldrw.32 q0, [r0]
1525
1526 # CHECK: vldrw.u32 q0, [r4, #56] @ encoding: [0x94,0xed,0x0e,0x1f]
1527 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1528 vldrw.s32 q0, [r4, #56]
1529
1530 # CHECK: vldrw.u32 q0, [r4, #56] @ encoding: [0x94,0xed,0x0e,0x1f]
1531 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1532 vldrw.f32 q0, [r4, #56]
1533
1534 # CHECK: vldrw.u32 q0, [r4, #56] @ encoding: [0x94,0xed,0x0e,0x1f]
1535 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1536 vldrw.32 q0, [r4, #56]
1537
1538 # CHECK: vldrw.u32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x0e,0xbf]
1539 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1540 vldrw.s32 q5, [r4, #56]!
1541
1542 # CHECK: vldrw.u32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x0e,0xbf]
1543 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1544 vldrw.f32 q5, [r4, #56]!
1545
1546 # CHECK: vldrw.u32 q5, [r4, #56]! @ encoding: [0xb4,0xed,0x0e,0xbf]
1547 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1548 vldrw.32 q5, [r4, #56]!
1549
1550 # CHECK: vstrw.32 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1f]
1551 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1552 vstrw.u32 q0, [r0]
1553
1554 # CHECK: vstrw.32 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1f]
1555 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1556 vstrw.s32 q0, [r0]
1557
1558 # CHECK: vstrw.32 q0, [r0] @ encoding: [0x80,0xed,0x00,0x1f]
1559 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1560 vstrw.f32 q0, [r0]
1561
1562 # CHECK: vstrw.32 q0, [r4, #56] @ encoding: [0x84,0xed,0x0e,0x1f]
1563 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1564 vstrw.u32 q0, [r4, #56]
1565
1566 # CHECK: vstrw.32 q0, [r4, #56] @ encoding: [0x84,0xed,0x0e,0x1f]
1567 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1568 vstrw.s32 q0, [r4, #56]
1569
1570 # CHECK: vstrw.32 q0, [r4, #56] @ encoding: [0x84,0xed,0x0e,0x1f]
1571 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1572 vstrw.f32 q0, [r4, #56]
1573
1574 # CHECK: vstrw.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x0e,0xbf]
1575 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1576 vstrw.u32 q5, [r4, #56]!
1577
1578 # CHECK: vstrw.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x0e,0xbf]
1579 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1580 vstrw.s32 q5, [r4, #56]!
1581
1582 # CHECK: vstrw.32 q5, [r4, #56]! @ encoding: [0xa4,0xed,0x0e,0xbf]
1583 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1584 vstrw.f32 q5, [r4, #56]!
1585
1586 # CHECK: vldrb.u8 q0, [r0, q1] @ encoding: [0x90,0xfc,0x02,0x0e]
1587 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1588 vldrb.s8 q0, [r0, q1]
1589
1590 # CHECK: vldrb.u8 q0, [r0, q1] @ encoding: [0x90,0xfc,0x02,0x0e]
1591 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1592 vldrb.8 q0, [r0, q1]
1593
1594 # CHECK: vldrh.u16 q3, [r0, q1] @ encoding: [0x90,0xfc,0x92,0x6e]
1595 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1596 vldrh.s16 q3, [r0, q1]
1597
1598 # CHECK: vldrh.u16 q3, [r0, q1] @ encoding: [0x90,0xfc,0x92,0x6e]
1599 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1600 vldrh.f16 q3, [r0, q1]
1601
1602 # CHECK: vldrh.u16 q3, [r0, q1] @ encoding: [0x90,0xfc,0x92,0x6e]
1603 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1604 vldrh.16 q3, [r0, q1]
1605
1606 # CHECK: vldrh.u16 q0, [r0, q1, uxtw #1] @ encoding: [0x90,0xfc,0x93,0x0e]
1607 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1608 vldrh.s16 q0, [r0, q1, uxtw #1]
1609
1610 # CHECK: vldrh.u16 q0, [r0, q1, uxtw #1] @ encoding: [0x90,0xfc,0x93,0x0e]
1611 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1612 vldrh.f16 q0, [r0, q1, uxtw #1]
1613
1614 # CHECK: vldrh.u16 q0, [r0, q1, uxtw #1] @ encoding: [0x90,0xfc,0x93,0x0e]
1615 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1616 vldrh.16 q0, [r0, q1, uxtw #1]
1617
1618 # CHECK: vldrw.u32 q0, [r0, q1] @ encoding: [0x90,0xfc,0x42,0x0f]
1619 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1620 vldrw.s32 q0, [r0, q1]
1621
1622 # CHECK: vldrw.u32 q0, [r0, q1] @ encoding: [0x90,0xfc,0x42,0x0f]
1623 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1624 vldrw.f32 q0, [r0, q1]
1625
1626 # CHECK: vldrw.u32 q0, [r0, q1] @ encoding: [0x90,0xfc,0x42,0x0f]
1627 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1628 vldrw.32 q0, [r0, q1]
1629
1630 # CHECK: vldrw.u32 q0, [r0, q1, uxtw #2] @ encoding: [0x90,0xfc,0x43,0x0f]
1631 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1632 vldrw.s32 q0, [r0, q1, uxtw #2]
1633
1634 # CHECK: vldrw.u32 q0, [r0, q1, uxtw #2] @ encoding: [0x90,0xfc,0x43,0x0f]
1635 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1636 vldrw.f32 q0, [r0, q1, uxtw #2]
1637
1638 # CHECK: vldrw.u32 q0, [r0, q1, uxtw #2] @ encoding: [0x90,0xfc,0x43,0x0f]
1639 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1640 vldrw.32 q0, [r0, q1, uxtw #2]
1641
1642 # CHECK: vldrd.u64 q0, [r0, q1] @ encoding: [0x90,0xfc,0xd2,0x0f]
1643 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1644 vldrd.s64 q0, [r0, q1]
1645
1646 # CHECK: vldrd.u64 q0, [r0, q1] @ encoding: [0x90,0xfc,0xd2,0x0f]
1647 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1648 vldrd.f64 q0, [r0, q1]
1649
1650 # CHECK: vldrd.u64 q0, [r0, q1] @ encoding: [0x90,0xfc,0xd2,0x0f]
1651 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1652 vldrd.64 q0, [r0, q1]
1653
1654 # CHECK: vldrd.u64 q0, [r0, q1, uxtw #3] @ encoding: [0x90,0xfc,0xd3,0x0f]
1655 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1656 vldrd.s64 q0, [r0, q1, uxtw #3]
1657
1658 # CHECK: vldrd.u64 q0, [r0, q1, uxtw #3] @ encoding: [0x90,0xfc,0xd3,0x0f]
1659 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1660 vldrd.f64 q0, [r0, q1, uxtw #3]
1661
1662 # CHECK: vldrd.u64 q0, [r0, q1, uxtw #3] @ encoding: [0x90,0xfc,0xd3,0x0f]
1663 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1664 vldrd.64 q0, [r0, q1, uxtw #3]
1665
1666 # CHECK: vstrb.8 q0, [r0, q1] @ encoding: [0x80,0xec,0x02,0x0e]
1667 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1668 vstrb.u8 q0, [r0, q1]
1669
1670 # CHECK: vstrb.8 q0, [r0, q1] @ encoding: [0x80,0xec,0x02,0x0e]
1671 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1672 vstrb.s8 q0, [r0, q1]
1673
1674 # CHECK: vstrh.16 q3, [r0, q1] @ encoding: [0x80,0xec,0x92,0x6e]
1675 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1676 vstrh.u16 q3, [r0, q1]
1677
1678 # CHECK: vstrh.16 q3, [r0, q1] @ encoding: [0x80,0xec,0x92,0x6e]
1679 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1680 vstrh.s16 q3, [r0, q1]
1681
1682 # CHECK: vstrh.16 q3, [r0, q1] @ encoding: [0x80,0xec,0x92,0x6e]
1683 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1684 vstrh.f16 q3, [r0, q1]
1685
1686 # CHECK: vstrh.16 q0, [r0, q1, uxtw #1] @ encoding: [0x80,0xec,0x93,0x0e]
1687 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1688 vstrh.u16 q0, [r0, q1, uxtw #1]
1689
1690 # CHECK: vstrh.16 q0, [r0, q1, uxtw #1] @ encoding: [0x80,0xec,0x93,0x0e]
1691 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1692 vstrh.s16 q0, [r0, q1, uxtw #1]
1693
1694 # CHECK: vstrh.16 q0, [r0, q1, uxtw #1] @ encoding: [0x80,0xec,0x93,0x0e]
1695 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1696 vstrh.f16 q0, [r0, q1, uxtw #1]
1697
1698 # CHECK: vstrw.32 q0, [r0, q1] @ encoding: [0x80,0xec,0x42,0x0f]
1699 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1700 vstrw.u32 q0, [r0, q1]
1701
1702 # CHECK: vstrw.32 q0, [r0, q1] @ encoding: [0x80,0xec,0x42,0x0f]
1703 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1704 vstrw.s32 q0, [r0, q1]
1705
1706 # CHECK: vstrw.32 q0, [r0, q1] @ encoding: [0x80,0xec,0x42,0x0f]
1707 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1708 vstrw.f32 q0, [r0, q1]
1709
1710 # CHECK: vstrw.32 q0, [r0, q1, uxtw #2] @ encoding: [0x80,0xec,0x43,0x0f]
1711 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1712 vstrw.u32 q0, [r0, q1, uxtw #2]
1713
1714 # CHECK: vstrw.32 q0, [r0, q1, uxtw #2] @ encoding: [0x80,0xec,0x43,0x0f]
1715 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1716 vstrw.s32 q0, [r0, q1, uxtw #2]
1717
1718 # CHECK: vstrw.32 q0, [r0, q1, uxtw #2] @ encoding: [0x80,0xec,0x43,0x0f]
1719 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1720 vstrw.f32 q0, [r0, q1, uxtw #2]
1721
1722 # CHECK: vstrd.64 q3, [r0, q1] @ encoding: [0x80,0xec,0xd2,0x6f]
1723 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1724 vstrd.u64 q3, [r0, q1]
1725
1726 # CHECK: vstrd.64 q3, [r0, q1] @ encoding: [0x80,0xec,0xd2,0x6f]
1727 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1728 vstrd.s64 q3, [r0, q1]
1729
1730 # CHECK: vstrd.64 q3, [r0, q1] @ encoding: [0x80,0xec,0xd2,0x6f]
1731 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1732 vstrd.f64 q3, [r0, q1]
1733
1734 # CHECK: vstrd.64 q0, [r0, q1, uxtw #3] @ encoding: [0x80,0xec,0xd3,0x0f]
1735 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1736 vstrd.u64 q0, [r0, q1, uxtw #3]
1737
1738 # CHECK: vstrd.64 q0, [r0, q1, uxtw #3] @ encoding: [0x80,0xec,0xd3,0x0f]
1739 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1740 vstrd.s64 q0, [r0, q1, uxtw #3]
1741
1742 # CHECK: vstrd.64 q0, [r0, q1, uxtw #3] @ encoding: [0x80,0xec,0xd3,0x0f]
1743 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1744 vstrd.f64 q0, [r0, q1, uxtw #3]
1745
1746 # CHECK: vldrw.u32 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1e]
1747 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1748 vldrw.s32 q0, [q1]
1749
1750 # CHECK: vldrw.u32 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1e]
1751 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1752 vldrw.f32 q0, [q1]
1753
1754 # CHECK: vldrw.u32 q0, [q1] @ encoding: [0x92,0xfd,0x00,0x1e]
1755 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1756 vldrw.32 q0, [q1]
1757
1758 # CHECK: vldrw.u32 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xfe]
1759 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1760 vldrw.s32 q7, [q1]!
1761
1762 # CHECK: vldrw.u32 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xfe]
1763 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1764 vldrw.f32 q7, [q1]!
1765
1766 # CHECK: vldrw.u32 q7, [q1]! @ encoding: [0xb2,0xfd,0x00,0xfe]
1767 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1768 vldrw.32 q7, [q1]!
1769
1770 # CHECK: vldrw.u32 q7, [q1, #4] @ encoding: [0x92,0xfd,0x01,0xfe]
1771 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1772 vldrw.s32 q7, [q1, #4]
1773
1774 # CHECK: vldrw.u32 q7, [q1, #4] @ encoding: [0x92,0xfd,0x01,0xfe]
1775 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1776 vldrw.f32 q7, [q1, #4]
1777
1778 # CHECK: vldrw.u32 q7, [q1, #4] @ encoding: [0x92,0xfd,0x01,0xfe]
1779 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1780 vldrw.32 q7, [q1, #4]
1781
1782 # CHECK: vldrw.u32 q7, [q1, #4]! @ encoding: [0xb2,0xfd,0x01,0xfe]
1783 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1784 vldrw.s32 q7, [q1, #4]!
1785
1786 # CHECK: vldrw.u32 q7, [q1, #4]! @ encoding: [0xb2,0xfd,0x01,0xfe]
1787 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1788 vldrw.f32 q7, [q1, #4]!
1789
1790 # CHECK: vldrw.u32 q7, [q1, #4]! @ encoding: [0xb2,0xfd,0x01,0xfe]
1791 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction
1792 vldrw.u32 q7, [q1, #4]!
1793
1794 # CHECK: vstrw.32 q0, [q1] @ encoding: [0x82,0xfd,0x00,0x1e]
1795 # ERROR-NOMVE: [[@LINE+1]]:1: error: invalid instruction