llvm.org GIT mirror llvm / 82804ad
[X86][AVX512] Add missing entries to EVEX2VEX tables evex2vex pass defines 2 tables which maps EVEX instructions to their VEX identical when possible. Adding all missing entries. Differential Revision: https://reviews.llvm.org/D30501 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297126 91177308-0d34-0410-b5e6-96231b3b80d8 Ayman Musa 2 years ago
13 changed file(s) with 318 addition(s) and 186 deletion(s). Raw diff Collapse all Expand all
4646 { X86::VCOMISDZrr , X86::VCOMISDrr },
4747 { X86::VCOMISSZrm , X86::VCOMISSrm },
4848 { X86::VCOMISSZrr , X86::VCOMISSrr },
49 { X86::VCVTSD2SI64Zrm , X86::VCVTSD2SI64rm },
5049 { X86::VCVTSD2SI64Zrr , X86::VCVTSD2SI64rr },
51 { X86::VCVTSD2SIZrm , X86::VCVTSD2SIrm },
5250 { X86::VCVTSD2SIZrr , X86::VCVTSD2SIrr },
5351 { X86::VCVTSD2SSZrm , X86::VCVTSD2SSrm },
5452 { X86::VCVTSD2SSZrr , X86::VCVTSD2SSrr },
6058 { X86::VCVTSI2SSZrm_Int , X86::Int_VCVTSI2SSrm },
6159 { X86::VCVTSI2SSZrr , X86::VCVTSI2SSrr },
6260 { X86::VCVTSI2SSZrr_Int , X86::Int_VCVTSI2SSrr },
61 { X86::VCVTSI642SDZrm , X86::VCVTSI2SD64rm },
62 { X86::VCVTSI642SDZrm_Int , X86::Int_VCVTSI2SD64rm },
63 { X86::VCVTSI642SDZrr , X86::VCVTSI2SD64rr },
64 { X86::VCVTSI642SDZrr_Int , X86::Int_VCVTSI2SD64rr },
65 { X86::VCVTSI642SSZrm , X86::VCVTSI2SS64rm },
66 { X86::VCVTSI642SSZrm_Int , X86::Int_VCVTSI2SS64rm },
67 { X86::VCVTSI642SSZrr , X86::VCVTSI2SS64rr },
68 { X86::VCVTSI642SSZrr_Int , X86::Int_VCVTSI2SS64rr },
6369 { X86::VCVTSS2SDZrm , X86::VCVTSS2SDrm },
6470 { X86::VCVTSS2SDZrr , X86::VCVTSS2SDrr },
65 { X86::VCVTSS2SI64Zrm , X86::VCVTSS2SI64rm },
6671 { X86::VCVTSS2SI64Zrr , X86::VCVTSS2SI64rr },
67 { X86::VCVTSS2SIZrm , X86::VCVTSS2SIrm },
6872 { X86::VCVTSS2SIZrr , X86::VCVTSS2SIrr },
6973 { X86::VCVTTSD2SI64Zrm , X86::VCVTTSD2SI64rm },
7074 { X86::VCVTTSD2SI64Zrm_Int , X86::Int_VCVTTSD2SI64rm },
9094 { X86::VDIVSSZrm_Int , X86::VDIVSSrm_Int },
9195 { X86::VDIVSSZrr , X86::VDIVSSrr },
9296 { X86::VDIVSSZrr_Int , X86::VDIVSSrr_Int },
97 { X86::VEXTRACTPSZmr , X86::VEXTRACTPSmr },
98 { X86::VEXTRACTPSZrr , X86::VEXTRACTPSrr },
9399 { X86::VFMADD132SDZm , X86::VFMADD132SDm },
94100 { X86::VFMADD132SDZm_Int , X86::VFMADD132SDm_Int },
95101 { X86::VFMADD132SDZr , X86::VFMADD132SDr },
186192 { X86::VFNMSUB231SSZm_Int , X86::VFNMSUB231SSm_Int },
187193 { X86::VFNMSUB231SSZr , X86::VFNMSUB231SSr },
188194 { X86::VFNMSUB231SSZr_Int , X86::VFNMSUB231SSr_Int },
195 { X86::VINSERTPSZrm , X86::VINSERTPSrm },
196 { X86::VINSERTPSZrr , X86::VINSERTPSrr },
189197 { X86::VMAXCSDZrm , X86::VMAXCSDrm },
190198 { X86::VMAXCSDZrr , X86::VMAXCSDrr },
191199 { X86::VMAXCSSZrm , X86::VMAXCSSrm },
192200 { X86::VMAXCSSZrr , X86::VMAXCSSrr },
193 { X86::VMAXSDZrm , X86::VMAXSDrm },
201 { X86::VMAXSDZrm , X86::VMAXCSDrm },
194202 { X86::VMAXSDZrm_Int , X86::VMAXSDrm_Int },
195 { X86::VMAXSDZrr , X86::VMAXSDrr },
203 { X86::VMAXSDZrr , X86::VMAXCSDrr },
196204 { X86::VMAXSDZrr_Int , X86::VMAXSDrr_Int },
197 { X86::VMAXSSZrm , X86::VMAXSSrm },
205 { X86::VMAXSSZrm , X86::VMAXCSSrm },
198206 { X86::VMAXSSZrm_Int , X86::VMAXSSrm_Int },
199 { X86::VMAXSSZrr , X86::VMAXSSrr },
207 { X86::VMAXSSZrr , X86::VMAXCSSrr },
200208 { X86::VMAXSSZrr_Int , X86::VMAXSSrr_Int },
201209 { X86::VMINCSDZrm , X86::VMINCSDrm },
202210 { X86::VMINCSDZrr , X86::VMINCSDrr },
203211 { X86::VMINCSSZrm , X86::VMINCSSrm },
204212 { X86::VMINCSSZrr , X86::VMINCSSrr },
205 { X86::VMINSDZrm , X86::VMINSDrm },
213 { X86::VMINSDZrm , X86::VMINCSDrm },
206214 { X86::VMINSDZrm_Int , X86::VMINSDrm_Int },
207 { X86::VMINSDZrr , X86::VMINSDrr },
215 { X86::VMINSDZrr , X86::VMINCSDrr },
208216 { X86::VMINSDZrr_Int , X86::VMINSDrr_Int },
209 { X86::VMINSSZrm , X86::VMINSSrm },
217 { X86::VMINSSZrm , X86::VMINCSSrm },
210218 { X86::VMINSSZrm_Int , X86::VMINSSrm_Int },
211 { X86::VMINSSZrr , X86::VMINSSrr },
219 { X86::VMINSSZrr , X86::VMINCSSrr },
212220 { X86::VMINSSZrr_Int , X86::VMINSSrr_Int },
213221 { X86::VMOV64toSDZrr , X86::VMOV64toSDrr },
214222 { X86::VMOVDI2SSZrm , X86::VMOVDI2SSrm },
215223 { X86::VMOVDI2SSZrr , X86::VMOVDI2SSrr },
224 { X86::VMOVSDto64Zmr , X86::VMOVSDto64mr },
225 { X86::VMOVSDto64Zrr , X86::VMOVSDto64rr },
216226 { X86::VMOVSDZmr , X86::VMOVSDmr },
217227 { X86::VMOVSDZrm , X86::VMOVSDrm },
218228 { X86::VMOVSDZrr , X86::VMOVSDrr },
229 { X86::VMOVSDZrr_REV , X86::VMOVSDrr_REV },
230 { X86::VMOVSS2DIZmr , X86::VMOVSS2DImr },
231 { X86::VMOVSS2DIZrr , X86::VMOVSS2DIrr },
219232 { X86::VMOVSSZmr , X86::VMOVSSmr },
220233 { X86::VMOVSSZrm , X86::VMOVSSrm },
221234 { X86::VMOVSSZrr , X86::VMOVSSrr },
249262 { X86::VUCOMISSZrm , X86::VUCOMISSrm },
250263 { X86::VUCOMISSZrr , X86::VUCOMISSrr },
251264
265 { X86::VMOV64toPQIZrm , X86::VMOV64toPQIrm },
252266 { X86::VMOV64toPQIZrr , X86::VMOV64toPQIrr },
253267 { X86::VMOV64toSDZrr , X86::VMOV64toSDrr },
254268 { X86::VMOVDI2PDIZrm , X86::VMOVDI2PDIrm },
258272 { X86::VMOVPDI2DIZmr , X86::VMOVPDI2DImr },
259273 { X86::VMOVPDI2DIZrr , X86::VMOVPDI2DIrr },
260274 { X86::VMOVPQI2QIZmr , X86::VMOVPQI2QImr },
275 { X86::VMOVPQI2QIZrr , X86::VMOVPQI2QIrr },
276 { X86::VMOVPQIto64Zmr , X86::VMOVPQIto64mr },
261277 { X86::VMOVPQIto64Zrr , X86::VMOVPQIto64rr },
262278 { X86::VMOVQI2PQIZrm , X86::VMOVQI2PQIrm },
263279 { X86::VMOVZPQILo2PQIZrr , X86::VMOVZPQILo2PQIrr },
270286 { X86::VPEXTRQZrr , X86::VPEXTRQrr },
271287 { X86::VPEXTRWZmr , X86::VPEXTRWmr },
272288 { X86::VPEXTRWZrr , X86::VPEXTRWri },
289 { X86::VPEXTRWZrr_REV , X86::VPEXTRWrr_REV },
273290
274291 { X86::VPINSRBZrm , X86::VPINSRBrm },
275292 { X86::VPINSRBZrr , X86::VPINSRBrr },
293310 { X86::VANDPDZ128rr , X86::VANDPDrr },
294311 { X86::VANDPSZ128rm , X86::VANDPSrm },
295312 { X86::VANDPSZ128rr , X86::VANDPSrr },
313 { X86::VBROADCASTI32X2Z128m , X86::VPBROADCASTQrm },
314 { X86::VBROADCASTI32X2Z128r , X86::VPBROADCASTQrr },
296315 { X86::VBROADCASTSSZ128m , X86::VBROADCASTSSrm },
297316 { X86::VBROADCASTSSZ128r , X86::VBROADCASTSSrr },
298317 { X86::VCVTDQ2PDZ128rm , X86::VCVTDQ2PDrm },
395414 { X86::VMAXCPDZ128rr , X86::VMAXCPDrr },
396415 { X86::VMAXCPSZ128rm , X86::VMAXCPSrm },
397416 { X86::VMAXCPSZ128rr , X86::VMAXCPSrr },
398 { X86::VMAXPDZ128rm , X86::VMAXPDrm },
399 { X86::VMAXPDZ128rr , X86::VMAXPDrr },
400 { X86::VMAXPSZ128rm , X86::VMAXPSrm },
401 { X86::VMAXPSZ128rr , X86::VMAXPSrr },
417 { X86::VMAXPDZ128rm , X86::VMAXCPDrm },
418 { X86::VMAXPDZ128rr , X86::VMAXCPDrr },
419 { X86::VMAXPSZ128rm , X86::VMAXCPSrm },
420 { X86::VMAXPSZ128rr , X86::VMAXCPSrr },
402421 { X86::VMINCPDZ128rm , X86::VMINCPDrm },
403422 { X86::VMINCPDZ128rr , X86::VMINCPDrr },
404423 { X86::VMINCPSZ128rm , X86::VMINCPSrm },
405424 { X86::VMINCPSZ128rr , X86::VMINCPSrr },
406 { X86::VMINPDZ128rm , X86::VMINPDrm },
407 { X86::VMINPDZ128rr , X86::VMINPDrr },
408 { X86::VMINPSZ128rm , X86::VMINPSrm },
409 { X86::VMINPSZ128rr , X86::VMINPSrr },
425 { X86::VMINPDZ128rm , X86::VMINCPDrm },
426 { X86::VMINPDZ128rr , X86::VMINCPDrr },
427 { X86::VMINPSZ128rm , X86::VMINCPSrm },
428 { X86::VMINPSZ128rr , X86::VMINCPSrr },
410429 { X86::VMOVAPDZ128mr , X86::VMOVAPDmr },
411430 { X86::VMOVAPDZ128rm , X86::VMOVAPDrm },
412431 { X86::VMOVAPDZ128rr , X86::VMOVAPDrr },
509528 { X86::VPANDDZ128rr , X86::VPANDrr },
510529 { X86::VPANDQZ128rm , X86::VPANDrm },
511530 { X86::VPANDQZ128rr , X86::VPANDrr },
531 { X86::VPANDNDZ128rm , X86::VPANDNrm },
532 { X86::VPANDNDZ128rr , X86::VPANDNrr },
533 { X86::VPANDNQZ128rm , X86::VPANDNrm },
534 { X86::VPANDNQZ128rr , X86::VPANDNrr },
512535 { X86::VPAVGBZ128rm , X86::VPAVGBrm },
513536 { X86::VPAVGBZ128rr , X86::VPAVGBrr },
514537 { X86::VPAVGWZ128rm , X86::VPAVGWrm },
723746 { X86::VANDPDZ256rr , X86::VANDPDYrr },
724747 { X86::VANDPSZ256rm , X86::VANDPSYrm },
725748 { X86::VANDPSZ256rr , X86::VANDPSYrr },
749 { X86::VBROADCASTF32X2Z256m , X86::VBROADCASTSDYrm },
750 { X86::VBROADCASTF32X2Z256r , X86::VBROADCASTSDYrr },
751 { X86::VBROADCASTF32X4Z256rm , X86::VBROADCASTF128 },
752 { X86::VBROADCASTI32X2Z256m , X86::VPBROADCASTQYrm },
753 { X86::VBROADCASTI32X2Z256r , X86::VPBROADCASTQYrr },
754 { X86::VBROADCASTI32X4Z256rm , X86::VBROADCASTI128 },
726755 { X86::VBROADCASTSDZ256m , X86::VBROADCASTSDYrm },
727756 { X86::VBROADCASTSDZ256r , X86::VBROADCASTSDYrr },
728757 { X86::VBROADCASTSSZ256m , X86::VBROADCASTSSYrm },
843872 { X86::VMAXCPDZ256rr , X86::VMAXCPDYrr },
844873 { X86::VMAXCPSZ256rm , X86::VMAXCPSYrm },
845874 { X86::VMAXCPSZ256rr , X86::VMAXCPSYrr },
846 { X86::VMAXPDZ256rm , X86::VMAXPDYrm },
847 { X86::VMAXPDZ256rr , X86::VMAXPDYrr },
848 { X86::VMAXPSZ256rm , X86::VMAXPSYrm },
849 { X86::VMAXPSZ256rr , X86::VMAXPSYrr },
875 { X86::VMAXPDZ256rm , X86::VMAXCPDYrm },
876 { X86::VMAXPDZ256rr , X86::VMAXCPDYrr },
877 { X86::VMAXPSZ256rm , X86::VMAXCPSYrm },
878 { X86::VMAXPSZ256rr , X86::VMAXCPSYrr },
850879 { X86::VMINCPDZ256rm , X86::VMINCPDYrm },
851880 { X86::VMINCPDZ256rr , X86::VMINCPDYrr },
852881 { X86::VMINCPSZ256rm , X86::VMINCPSYrm },
853882 { X86::VMINCPSZ256rr , X86::VMINCPSYrr },
854 { X86::VMINPDZ256rm , X86::VMINPDYrm },
855 { X86::VMINPDZ256rr , X86::VMINPDYrr },
856 { X86::VMINPSZ256rm , X86::VMINPSYrm },
857 { X86::VMINPSZ256rr , X86::VMINPSYrr },
883 { X86::VMINPDZ256rm , X86::VMINCPDYrm },
884 { X86::VMINPDZ256rr , X86::VMINCPDYrr },
885 { X86::VMINPSZ256rm , X86::VMINCPSYrm },
886 { X86::VMINPSZ256rr , X86::VMINCPSYrr },
858887 { X86::VMOVAPDZ256mr , X86::VMOVAPDYmr },
859888 { X86::VMOVAPDZ256rm , X86::VMOVAPDYrm },
860889 { X86::VMOVAPDZ256rr , X86::VMOVAPDYrr },
949978 { X86::VPANDDZ256rr , X86::VPANDYrr },
950979 { X86::VPANDQZ256rm , X86::VPANDYrm },
951980 { X86::VPANDQZ256rr , X86::VPANDYrr },
981 { X86::VPANDNDZ256rm , X86::VPANDNYrm },
982 { X86::VPANDNDZ256rr , X86::VPANDNYrr },
983 { X86::VPANDNQZ256rm , X86::VPANDNYrm },
984 { X86::VPANDNQZ256rr , X86::VPANDNYrr },
952985 { X86::VPAVGBZ256rm , X86::VPAVGBYrm },
953986 { X86::VPAVGBZ256rr , X86::VPAVGBYrr },
954987 { X86::VPAVGWZ256rm , X86::VPAVGWYrm },
33 define i32 @test1(float %x) {
44 ; CHECK-LABEL: test1:
55 ; CHECK: ## BB#0:
6 ; CHECK-NEXT: vmovd %xmm0, %eax ## encoding: [0x62,0xf1,0x7d,0x08,0x7e,0xc0]
6 ; CHECK-NEXT: vmovd %xmm0, %eax ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x7e,0xc0]
77 ; CHECK-NEXT: retq ## encoding: [0xc3]
88 %res = bitcast float %x to i32
99 ret i32 %res
99 define <4 x double> @test_broadcast_2f64_4f64(<2 x double> *%p) nounwind {
1010 ; X64-AVX512VL-LABEL: test_broadcast_2f64_4f64:
1111 ; X64-AVX512VL: ## BB#0:
12 ; X64-AVX512VL-NEXT: vbroadcastf32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
12 ; X64-AVX512VL-NEXT: vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
1313 ; X64-AVX512VL-NEXT: vaddpd {{.*}}(%rip), %ymm0, %ymm0
1414 ; X64-AVX512VL-NEXT: retq
1515 ;
1616 ; X64-AVX512BWVL-LABEL: test_broadcast_2f64_4f64:
1717 ; X64-AVX512BWVL: ## BB#0:
18 ; X64-AVX512BWVL-NEXT: vbroadcastf32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
18 ; X64-AVX512BWVL-NEXT: vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
1919 ; X64-AVX512BWVL-NEXT: vaddpd {{.*}}(%rip), %ymm0, %ymm0
2020 ; X64-AVX512BWVL-NEXT: retq
2121 ;
3333 define <4 x i64> @test_broadcast_2i64_4i64(<2 x i64> *%p) nounwind {
3434 ; X64-AVX512VL-LABEL: test_broadcast_2i64_4i64:
3535 ; X64-AVX512VL: ## BB#0:
36 ; X64-AVX512VL-NEXT: vbroadcasti32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
36 ; X64-AVX512VL-NEXT: vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
3737 ; X64-AVX512VL-NEXT: vpaddq {{.*}}(%rip), %ymm0, %ymm0
3838 ; X64-AVX512VL-NEXT: retq
3939 ;
4040 ; X64-AVX512BWVL-LABEL: test_broadcast_2i64_4i64:
4141 ; X64-AVX512BWVL: ## BB#0:
42 ; X64-AVX512BWVL-NEXT: vbroadcasti32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
42 ; X64-AVX512BWVL-NEXT: vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
4343 ; X64-AVX512BWVL-NEXT: vpaddq {{.*}}(%rip), %ymm0, %ymm0
4444 ; X64-AVX512BWVL-NEXT: retq
4545 ;
5757 define <8 x float> @test_broadcast_4f32_8f32(<4 x float> *%p) nounwind {
5858 ; X64-AVX512-LABEL: test_broadcast_4f32_8f32:
5959 ; X64-AVX512: ## BB#0:
60 ; X64-AVX512-NEXT: vbroadcastf32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
60 ; X64-AVX512-NEXT: vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
6161 ; X64-AVX512-NEXT: vaddps {{.*}}(%rip), %ymm0, %ymm0
6262 ; X64-AVX512-NEXT: retq
6363 %1 = load <4 x float>, <4 x float> *%p
6969 define <8 x i32> @test_broadcast_4i32_8i32(<4 x i32> *%p) nounwind {
7070 ; X64-AVX512-LABEL: test_broadcast_4i32_8i32:
7171 ; X64-AVX512: ## BB#0:
72 ; X64-AVX512-NEXT: vbroadcasti32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
72 ; X64-AVX512-NEXT: vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
7373 ; X64-AVX512-NEXT: vpaddd {{.*}}(%rip), %ymm0, %ymm0
7474 ; X64-AVX512-NEXT: retq
7575 %1 = load <4 x i32>, <4 x i32> *%p
8181 define <16 x i16> @test_broadcast_8i16_16i16(<8 x i16> *%p) nounwind {
8282 ; X64-AVX512-LABEL: test_broadcast_8i16_16i16:
8383 ; X64-AVX512: ## BB#0:
84 ; X64-AVX512-NEXT: vbroadcasti32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
84 ; X64-AVX512-NEXT: vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
8585 ; X64-AVX512-NEXT: vpaddw {{.*}}(%rip), %ymm0, %ymm0
8686 ; X64-AVX512-NEXT: retq
8787 %1 = load <8 x i16>, <8 x i16> *%p
9393 define <32 x i8> @test_broadcast_16i8_32i8(<16 x i8> *%p) nounwind {
9494 ; X64-AVX512-LABEL: test_broadcast_16i8_32i8:
9595 ; X64-AVX512: ## BB#0:
96 ; X64-AVX512-NEXT: vbroadcasti32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
96 ; X64-AVX512-NEXT: vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
9797 ; X64-AVX512-NEXT: vpaddb {{.*}}(%rip), %ymm0, %ymm0
9898 ; X64-AVX512-NEXT: retq
9999 %1 = load <16 x i8>, <16 x i8> *%p
181181 define <32 x i16> @test_broadcast_8i16_32i16(<8 x i16> *%p) nounwind {
182182 ; X64-AVX512VL-LABEL: test_broadcast_8i16_32i16:
183183 ; X64-AVX512VL: ## BB#0:
184 ; X64-AVX512VL-NEXT: vbroadcasti32x4 {{.*#+}} ymm1 = mem[0,1,2,3,0,1,2,3]
184 ; X64-AVX512VL-NEXT: vbroadcasti128 {{.*#+}} ymm1 = mem[0,1,0,1]
185185 ; X64-AVX512VL-NEXT: vpaddw {{.*}}(%rip), %ymm1, %ymm0
186186 ; X64-AVX512VL-NEXT: vpaddw {{.*}}(%rip), %ymm1, %ymm1
187187 ; X64-AVX512VL-NEXT: retq
194194 ;
195195 ; X64-AVX512DQVL-LABEL: test_broadcast_8i16_32i16:
196196 ; X64-AVX512DQVL: ## BB#0:
197 ; X64-AVX512DQVL-NEXT: vbroadcasti32x4 {{.*#+}} ymm1 = mem[0,1,2,3,0,1,2,3]
197 ; X64-AVX512DQVL-NEXT: vbroadcasti128 {{.*#+}} ymm1 = mem[0,1,0,1]
198198 ; X64-AVX512DQVL-NEXT: vpaddw {{.*}}(%rip), %ymm1, %ymm0
199199 ; X64-AVX512DQVL-NEXT: vpaddw {{.*}}(%rip), %ymm1, %ymm1
200200 ; X64-AVX512DQVL-NEXT: retq
207207 define <64 x i8> @test_broadcast_16i8_64i8(<16 x i8> *%p) nounwind {
208208 ; X64-AVX512VL-LABEL: test_broadcast_16i8_64i8:
209209 ; X64-AVX512VL: ## BB#0:
210 ; X64-AVX512VL-NEXT: vbroadcasti32x4 {{.*#+}} ymm1 = mem[0,1,2,3,0,1,2,3]
210 ; X64-AVX512VL-NEXT: vbroadcasti128 {{.*#+}} ymm1 = mem[0,1,0,1]
211211 ; X64-AVX512VL-NEXT: vpaddb {{.*}}(%rip), %ymm1, %ymm0
212212 ; X64-AVX512VL-NEXT: vpaddb {{.*}}(%rip), %ymm1, %ymm1
213213 ; X64-AVX512VL-NEXT: retq
220220 ;
221221 ; X64-AVX512DQVL-LABEL: test_broadcast_16i8_64i8:
222222 ; X64-AVX512DQVL: ## BB#0:
223 ; X64-AVX512DQVL-NEXT: vbroadcasti32x4 {{.*#+}} ymm1 = mem[0,1,2,3,0,1,2,3]
223 ; X64-AVX512DQVL-NEXT: vbroadcasti128 {{.*#+}} ymm1 = mem[0,1,0,1]
224224 ; X64-AVX512DQVL-NEXT: vpaddb {{.*}}(%rip), %ymm1, %ymm0
225225 ; X64-AVX512DQVL-NEXT: vpaddb {{.*}}(%rip), %ymm1, %ymm1
226226 ; X64-AVX512DQVL-NEXT: retq
630630 ; CHECK-NEXT: ## ymm1 {%k1} = xmm0[0,1,0,1,0,1,0,1]
631631 ; CHECK-NEXT: vbroadcastf32x2 %xmm0, %ymm2 {%k1} {z} ## encoding: [0x62,0xf2,0x7d,0xa9,0x19,0xd0]
632632 ; CHECK-NEXT: ## ymm2 {%k1} {z} = xmm0[0,1,0,1,0,1,0,1]
633 ; CHECK-NEXT: vbroadcastf32x2 %xmm0, %ymm0 ## encoding: [0x62,0xf2,0x7d,0x28,0x19,0xc0]
634 ; CHECK-NEXT: ## ymm0 = xmm0[0,1,0,1,0,1,0,1]
633 ; CHECK-NEXT: vbroadcastsd %xmm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x19,0xc0]
635634 ; CHECK-NEXT: vaddps %ymm2, %ymm1, %ymm1 ## EVEX TO VEX Compression encoding: [0xc5,0xf4,0x58,0xca]
636635 ; CHECK-NEXT: vaddps %ymm0, %ymm1, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf4,0x58,0xc0]
637636 ; CHECK-NEXT: retq ## encoding: [0xc3]
653652 ; CHECK-NEXT: ## ymm1 {%k1} = mem[0,1,0,1,0,1,0,1]
654653 ; CHECK-NEXT: vbroadcasti32x2 %xmm0, %ymm2 {%k1} {z} ## encoding: [0x62,0xf2,0x7d,0xa9,0x59,0xd0]
655654 ; CHECK-NEXT: ## ymm2 {%k1} {z} = xmm0[0,1,0,1,0,1,0,1]
656 ; CHECK-NEXT: vbroadcasti32x2 %xmm0, %ymm0 ## encoding: [0x62,0xf2,0x7d,0x28,0x59,0xc0]
657 ; CHECK-NEXT: ## ymm0 = xmm0[0,1,0,1,0,1,0,1]
655 ; CHECK-NEXT: vpbroadcastq %xmm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x59,0xc0]
658656 ; CHECK-NEXT: vpaddd %ymm0, %ymm2, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xed,0xfe,0xc0]
659657 ; CHECK-NEXT: vpaddd %ymm0, %ymm1, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf5,0xfe,0xc0]
660658 ; CHECK-NEXT: retq ## encoding: [0xc3]
677675 ; CHECK-NEXT: kmovb %edi, %k1 ## encoding: [0xc5,0xf9,0x92,0xcf]
678676 ; CHECK-NEXT: vbroadcasti32x2 %xmm0, %xmm1 {%k1} ## encoding: [0x62,0xf2,0x7d,0x09,0x59,0xc8]
679677 ; CHECK-NEXT: vbroadcasti32x2 %xmm0, %xmm2 {%k1} {z} ## encoding: [0x62,0xf2,0x7d,0x89,0x59,0xd0]
680 ; CHECK-NEXT: vbroadcasti32x2 %xmm0, %xmm0 ## encoding: [0x62,0xf2,0x7d,0x08,0x59,0xc0]
678 ; CHECK-NEXT: vpbroadcastq %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x59,0xc0]
681679 ; CHECK-NEXT: vpaddd %xmm2, %xmm1, %xmm1 ## EVEX TO VEX Compression encoding: [0xc5,0xf1,0xfe,0xca]
682680 ; CHECK-NEXT: vpaddd %xmm0, %xmm1, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf1,0xfe,0xc0]
683681 ; CHECK-NEXT: retq ## encoding: [0xc3]
21052105 define <4 x i32> @test_mask_andnot_epi32_rr_128(<4 x i32> %a, <4 x i32> %b) {
21062106 ; CHECK-LABEL: test_mask_andnot_epi32_rr_128:
21072107 ; CHECK: ## BB#0:
2108 ; CHECK-NEXT: vpandnd %xmm1, %xmm0, %xmm0 ## encoding: [0x62,0xf1,0x7d,0x08,0xdf,0xc1]
2108 ; CHECK-NEXT: vpandn %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xdf,0xc1]
21092109 ; CHECK-NEXT: retq ## encoding: [0xc3]
21102110 %res = call <4 x i32> @llvm.x86.avx512.mask.pandn.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 -1)
21112111 ret <4 x i32> %res
21352135 define <4 x i32> @test_mask_andnot_epi32_rm_128(<4 x i32> %a, <4 x i32>* %ptr_b) {
21362136 ; CHECK-LABEL: test_mask_andnot_epi32_rm_128:
21372137 ; CHECK: ## BB#0:
2138 ; CHECK-NEXT: vpandnd (%rdi), %xmm0, %xmm0 ## encoding: [0x62,0xf1,0x7d,0x08,0xdf,0x07]
2138 ; CHECK-NEXT: vpandn (%rdi), %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xdf,0x07]
21392139 ; CHECK-NEXT: retq ## encoding: [0xc3]
21402140 %b = load <4 x i32>, <4 x i32>* %ptr_b
21412141 %res = call <4 x i32> @llvm.x86.avx512.mask.pandn.d.128(<4 x i32> %a, <4 x i32> %b, <4 x i32> zeroinitializer, i8 -1)
22092209 define <8 x i32> @test_mask_andnot_epi32_rr_256(<8 x i32> %a, <8 x i32> %b) {
22102210 ; CHECK-LABEL: test_mask_andnot_epi32_rr_256:
22112211 ; CHECK: ## BB#0:
2212 ; CHECK-NEXT: vpandnd %ymm1, %ymm0, %ymm0 ## encoding: [0x62,0xf1,0x7d,0x28,0xdf,0xc1]
2212 ; CHECK-NEXT: vpandn %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xdf,0xc1]
22132213 ; CHECK-NEXT: retq ## encoding: [0xc3]
22142214 %res = call <8 x i32> @llvm.x86.avx512.mask.pandn.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 -1)
22152215 ret <8 x i32> %res
22392239 define <8 x i32> @test_mask_andnot_epi32_rm_256(<8 x i32> %a, <8 x i32>* %ptr_b) {
22402240 ; CHECK-LABEL: test_mask_andnot_epi32_rm_256:
22412241 ; CHECK: ## BB#0:
2242 ; CHECK-NEXT: vpandnd (%rdi), %ymm0, %ymm0 ## encoding: [0x62,0xf1,0x7d,0x28,0xdf,0x07]
2242 ; CHECK-NEXT: vpandn (%rdi), %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xdf,0x07]
22432243 ; CHECK-NEXT: retq ## encoding: [0xc3]
22442244 %b = load <8 x i32>, <8 x i32>* %ptr_b
22452245 %res = call <8 x i32> @llvm.x86.avx512.mask.pandn.d.256(<8 x i32> %a, <8 x i32> %b, <8 x i32> zeroinitializer, i8 -1)
23132313 define <2 x i64> @test_mask_andnot_epi64_rr_128(<2 x i64> %a, <2 x i64> %b) {
23142314 ; CHECK-LABEL: test_mask_andnot_epi64_rr_128:
23152315 ; CHECK: ## BB#0:
2316 ; CHECK-NEXT: vpandnq %xmm1, %xmm0, %xmm0 ## encoding: [0x62,0xf1,0xfd,0x08,0xdf,0xc1]
2316 ; CHECK-NEXT: vpandn %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xdf,0xc1]
23172317 ; CHECK-NEXT: retq ## encoding: [0xc3]
23182318 %res = call <2 x i64> @llvm.x86.avx512.mask.pandn.q.128(<2 x i64> %a, <2 x i64> %b, <2 x i64> zeroinitializer, i8 -1)
23192319 ret <2 x i64> %res
23432343 define <2 x i64> @test_mask_andnot_epi64_rm_128(<2 x i64> %a, <2 x i64>* %ptr_b) {
23442344 ; CHECK-LABEL: test_mask_andnot_epi64_rm_128:
23452345 ; CHECK: ## BB#0:
2346 ; CHECK-NEXT: vpandnq (%rdi), %xmm0, %xmm0 ## encoding: [0x62,0xf1,0xfd,0x08,0xdf,0x07]
2346 ; CHECK-NEXT: vpandn (%rdi), %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xdf,0x07]
23472347 ; CHECK-NEXT: retq ## encoding: [0xc3]
23482348 %b = load <2 x i64>, <2 x i64>* %ptr_b
23492349 %res = call <2 x i64> @llvm.x86.avx512.mask.pandn.q.128(<2 x i64> %a, <2 x i64> %b, <2 x i64> zeroinitializer, i8 -1)
24172417 define <4 x i64> @test_mask_andnot_epi64_rr_256(<4 x i64> %a, <4 x i64> %b) {
24182418 ; CHECK-LABEL: test_mask_andnot_epi64_rr_256:
24192419 ; CHECK: ## BB#0:
2420 ; CHECK-NEXT: vpandnq %ymm1, %ymm0, %ymm0 ## encoding: [0x62,0xf1,0xfd,0x28,0xdf,0xc1]
2420 ; CHECK-NEXT: vpandn %ymm1, %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xdf,0xc1]
24212421 ; CHECK-NEXT: retq ## encoding: [0xc3]
24222422 %res = call <4 x i64> @llvm.x86.avx512.mask.pandn.q.256(<4 x i64> %a, <4 x i64> %b, <4 x i64> zeroinitializer, i8 -1)
24232423 ret <4 x i64> %res
24472447 define <4 x i64> @test_mask_andnot_epi64_rm_256(<4 x i64> %a, <4 x i64>* %ptr_b) {
24482448 ; CHECK-LABEL: test_mask_andnot_epi64_rm_256:
24492449 ; CHECK: ## BB#0:
2450 ; CHECK-NEXT: vpandnq (%rdi), %ymm0, %ymm0 ## encoding: [0x62,0xf1,0xfd,0x28,0xdf,0x07]
2450 ; CHECK-NEXT: vpandn (%rdi), %ymm0, %ymm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfd,0xdf,0x07]
24512451 ; CHECK-NEXT: retq ## encoding: [0xc3]
24522452 %b = load <4 x i64>, <4 x i64>* %ptr_b
24532453 %res = call <4 x i64> @llvm.x86.avx512.mask.pandn.q.256(<4 x i64> %a, <4 x i64> %b, <4 x i64> zeroinitializer, i8 -1)
2020 ; CHECK-LABEL: vpandnd256:
2121 ; CHECK: ## BB#0: ## %entry
2222 ; CHECK-NEXT: vpaddd {{.*}}(%rip){1to8}, %ymm0, %ymm1
23 ; CHECK-NEXT: vpandnd %ymm1, %ymm0, %ymm0
23 ; CHECK-NEXT: vpandn %ymm1, %ymm0, %ymm0
2424 ; CHECK-NEXT: retq
2525 entry:
2626 ; Force the execution domain with an add.
7373 ; CHECK-LABEL: vpandnq256:
7474 ; CHECK: ## BB#0: ## %entry
7575 ; CHECK-NEXT: vpaddq {{.*}}(%rip){1to4}, %ymm0, %ymm0
76 ; CHECK-NEXT: vpandnq %ymm0, %ymm1, %ymm0
76 ; CHECK-NEXT: vpandn %ymm0, %ymm1, %ymm0
7777 ; CHECK-NEXT: retq
7878 entry:
7979 ; Force the execution domain with an add.
128128 ; CHECK-LABEL: vpandnd128:
129129 ; CHECK: ## BB#0: ## %entry
130130 ; CHECK-NEXT: vpaddd {{.*}}(%rip){1to4}, %xmm0, %xmm0
131 ; CHECK-NEXT: vpandnd %xmm0, %xmm1, %xmm0
131 ; CHECK-NEXT: vpandn %xmm0, %xmm1, %xmm0
132132 ; CHECK-NEXT: retq
133133 entry:
134134 ; Force the execution domain with an add.
181181 ; CHECK-LABEL: vpandnq128:
182182 ; CHECK: ## BB#0: ## %entry
183183 ; CHECK-NEXT: vpaddq {{.*}}(%rip), %xmm0, %xmm0
184 ; CHECK-NEXT: vpandnq %xmm0, %xmm1, %xmm0
184 ; CHECK-NEXT: vpandn %xmm0, %xmm1, %xmm0
185185 ; CHECK-NEXT: retq
186186 entry:
187187 ; Force the execution domain with an add.
118118 %ymm0 = VPANDQZ256rm %ymm0, %rip, 1, _, %rax, _
119119 ; CHECK: %ymm0 = VPANDYrr %ymm0, %ymm1
120120 %ymm0 = VPANDQZ256rr %ymm0, %ymm1
121 ; CHECK: %ymm0 = VPANDNYrm %ymm0, %rip, 1, _, %rax, _
122 %ymm0 = VPANDNDZ256rm %ymm0, %rip, 1, _, %rax, _
123 ; CHECK: %ymm0 = VPANDNYrr %ymm0, %ymm1
124 %ymm0 = VPANDNDZ256rr %ymm0, %ymm1
125 ; CHECK: %ymm0 = VPANDNYrm %ymm0, %rip, 1, _, %rax, _
126 %ymm0 = VPANDNQZ256rm %ymm0, %rip, 1, _, %rax, _
127 ; CHECK: %ymm0 = VPANDNYrr %ymm0, %ymm1
128 %ymm0 = VPANDNQZ256rr %ymm0, %ymm1
121129 ; CHECK: %ymm0 = VPAVGBYrm %ymm0, %rip, 1, _, %rax, _
122130 %ymm0 = VPAVGBZ256rm %ymm0, %rip, 1, _, %rax, _
123131 ; CHECK: %ymm0 = VPAVGBYrr %ymm0, %ymm1
346354 %ymm0 = VMAXCPSZ256rm %ymm0, %rip, 1, _, %rax, _
347355 ; CHECK: %ymm0 = VMAXCPSYrr %ymm0, %ymm1
348356 %ymm0 = VMAXCPSZ256rr %ymm0, %ymm1
349 ; CHECK: %ymm0 = VMAXPDYrm %ymm0, %rip, 1, _, %rax, _
357 ; CHECK: %ymm0 = VMAXCPDYrm %ymm0, %rip, 1, _, %rax, _
350358 %ymm0 = VMAXPDZ256rm %ymm0, %rip, 1, _, %rax, _
351 ; CHECK: %ymm0 = VMAXPDYrr %ymm0, %ymm1
359 ; CHECK: %ymm0 = VMAXCPDYrr %ymm0, %ymm1
352360 %ymm0 = VMAXPDZ256rr %ymm0, %ymm1
353 ; CHECK: %ymm0 = VMAXPSYrm %ymm0, %rip, 1, _, %rax, _
361 ; CHECK: %ymm0 = VMAXCPSYrm %ymm0, %rip, 1, _, %rax, _
354362 %ymm0 = VMAXPSZ256rm %ymm0, %rip, 1, _, %rax, _
355 ; CHECK: %ymm0 = VMAXPSYrr %ymm0, %ymm1
363 ; CHECK: %ymm0 = VMAXCPSYrr %ymm0, %ymm1
356364 %ymm0 = VMAXPSZ256rr %ymm0, %ymm1
357365 ; CHECK: %ymm0 = VMINCPDYrm %ymm0, %rip, 1, _, %rax, _
358366 %ymm0 = VMINCPDZ256rm %ymm0, %rip, 1, _, %rax, _
362370 %ymm0 = VMINCPSZ256rm %ymm0, %rip, 1, _, %rax, _
363371 ; CHECK: %ymm0 = VMINCPSYrr %ymm0, %ymm1
364372 %ymm0 = VMINCPSZ256rr %ymm0, %ymm1
365 ; CHECK: %ymm0 = VMINPDYrm %ymm0, %rip, 1, _, %rax, _
373 ; CHECK: %ymm0 = VMINCPDYrm %ymm0, %rip, 1, _, %rax, _
366374 %ymm0 = VMINPDZ256rm %ymm0, %rip, 1, _, %rax, _
367 ; CHECK: %ymm0 = VMINPDYrr %ymm0, %ymm1
375 ; CHECK: %ymm0 = VMINCPDYrr %ymm0, %ymm1
368376 %ymm0 = VMINPDZ256rr %ymm0, %ymm1
369 ; CHECK: %ymm0 = VMINPSYrm %ymm0, %rip, 1, _, %rax, _
377 ; CHECK: %ymm0 = VMINCPSYrm %ymm0, %rip, 1, _, %rax, _
370378 %ymm0 = VMINPSZ256rm %ymm0, %rip, 1, _, %rax, _
371 ; CHECK: %ymm0 = VMINPSYrr %ymm0, %ymm1
379 ; CHECK: %ymm0 = VMINCPSYrr %ymm0, %ymm1
372380 %ymm0 = VMINPSZ256rr %ymm0, %ymm1
373381 ; CHECK: %ymm0 = VXORPDYrm %ymm0, %rip, 1, _, %rax, _
374382 %ymm0 = VXORPDZ256rm %ymm0, %rip, 1, _, %rax, _
686694 %ymm0 = VPMOVZXWQZ256rm %rip, 1, _, %rax, _
687695 ; CHECK: %ymm0 = VPMOVZXWQYrr %xmm0
688696 %ymm0 = VPMOVZXWQZ256rr %xmm0
697 ; CHECK: %ymm0 = VBROADCASTF128 %rip, 1, _, %rax, _
698 %ymm0 = VBROADCASTF32X4Z256rm %rip, 1, _, %rax, _
699 ; CHECK: %ymm0 = VBROADCASTSDYrm %rip, 1, _, %rax, _
700 %ymm0 = VBROADCASTF32X2Z256m %rip, 1, _, %rax, _
701 ; CHECK: %ymm0 = VBROADCASTSDYrr %xmm0
702 %ymm0 = VBROADCASTF32X2Z256r %xmm0
689703 ; CHECK: %ymm0 = VBROADCASTSDYrm %rip, 1, _, %rax, _
690704 %ymm0 = VBROADCASTSDZ256m %rip, 1, _, %rax, _
691705 ; CHECK: %ymm0 = VBROADCASTSDYrr %xmm0
706720 %ymm0 = VPBROADCASTWZ256m %rip, 1, _, %rax, _
707721 ; CHECK: %ymm0 = VPBROADCASTWYrr %xmm0
708722 %ymm0 = VPBROADCASTWZ256r %xmm0
723 ; CHECK: %ymm0 = VBROADCASTI128 %rip, 1, _, %rax, _
724 %ymm0 = VBROADCASTI32X4Z256rm %rip, 1, _, %rax, _
725 ; CHECK: %ymm0 = VPBROADCASTQYrm %rip, 1, _, %rax, _
726 %ymm0 = VBROADCASTI32X2Z256m %rip, 1, _, %rax, _
727 ; CHECK: %ymm0 = VPBROADCASTQYrr %xmm0
728 %ymm0 = VBROADCASTI32X2Z256r %xmm0
709729 ; CHECK: %ymm0 = VPBROADCASTQYrm %rip, 1, _, %rax, _
710730 %ymm0 = VPBROADCASTQZ256m %rip, 1, _, %rax, _
711731 ; CHECK: %ymm0 = VPBROADCASTQYrr %xmm0
10381058 %xmm0 = VMAXCPSZ128rm %xmm0, %rip, 1, _, %rax, _
10391059 ; CHECK: %xmm0 = VMAXCPSrr %xmm0, %xmm1
10401060 %xmm0 = VMAXCPSZ128rr %xmm0, %xmm1
1041 ; CHECK: %xmm0 = VMAXPDrm %xmm0, %rip, 1, _, %rax, _
1061 ; CHECK: %xmm0 = VMAXCPDrm %xmm0, %rip, 1, _, %rax, _
10421062 %xmm0 = VMAXPDZ128rm %xmm0, %rip, 1, _, %rax, _
1043 ; CHECK: %xmm0 = VMAXPDrr %xmm0, %xmm1
1063 ; CHECK: %xmm0 = VMAXCPDrr %xmm0, %xmm1
10441064 %xmm0 = VMAXPDZ128rr %xmm0, %xmm1
1045 ; CHECK: %xmm0 = VMAXPSrm %xmm0, %rip, 1, _, %rax, _
1065 ; CHECK: %xmm0 = VMAXCPSrm %xmm0, %rip, 1, _, %rax, _
10461066 %xmm0 = VMAXPSZ128rm %xmm0, %rip, 1, _, %rax, _
1047 ; CHECK: %xmm0 = VMAXPSrr %xmm0, %xmm1
1067 ; CHECK: %xmm0 = VMAXCPSrr %xmm0, %xmm1
10481068 %xmm0 = VMAXPSZ128rr %xmm0, %xmm1
10491069 ; CHECK: %xmm0 = VMINCPDrm %xmm0, %rip, 1, _, %rax, _
10501070 %xmm0 = VMINCPDZ128rm %xmm0, %rip, 1, _, %rax, _
10541074 %xmm0 = VMINCPSZ128rm %xmm0, %rip, 1, _, %rax, _
10551075 ; CHECK: %xmm0 = VMINCPSrr %xmm0, %xmm1
10561076 %xmm0 = VMINCPSZ128rr %xmm0, %xmm1
1057 ; CHECK: %xmm0 = VMINPDrm %xmm0, %rip, 1, _, %rax, _
1077 ; CHECK: %xmm0 = VMINCPDrm %xmm0, %rip, 1, _, %rax, _
10581078 %xmm0 = VMINPDZ128rm %xmm0, %rip, 1, _, %rax, _
1059 ; CHECK: %xmm0 = VMINPDrr %xmm0, %xmm1
1079 ; CHECK: %xmm0 = VMINCPDrr %xmm0, %xmm1
10601080 %xmm0 = VMINPDZ128rr %xmm0, %xmm1
1061 ; CHECK: %xmm0 = VMINPSrm %xmm0, %rip, 1, _, %rax, _
1081 ; CHECK: %xmm0 = VMINCPSrm %xmm0, %rip, 1, _, %rax, _
10621082 %xmm0 = VMINPSZ128rm %xmm0, %rip, 1, _, %rax, _
1063 ; CHECK: %xmm0 = VMINPSrr %xmm0, %xmm1
1083 ; CHECK: %xmm0 = VMINCPSrr %xmm0, %xmm1
10641084 %xmm0 = VMINPSZ128rr %xmm0, %xmm1
10651085 ; CHECK: %xmm0 = VMULPDrm %xmm0, %rip, 1, _, %rax, _
10661086 %xmm0 = VMULPDZ128rm %xmm0, %rip, 1, _, %rax, _
11181138 %xmm0 = VPANDQZ128rm %xmm0, %rip, 1, _, %rax, _
11191139 ; CHECK: %xmm0 = VPANDrr %xmm0, %xmm1
11201140 %xmm0 = VPANDQZ128rr %xmm0, %xmm1
1141 ; CHECK: %xmm0 = VPANDNrm %xmm0, %rip, 1, _, %rax, _
1142 %xmm0 = VPANDNDZ128rm %xmm0, %rip, 1, _, %rax, _
1143 ; CHECK: %xmm0 = VPANDNrr %xmm0, %xmm1
1144 %xmm0 = VPANDNDZ128rr %xmm0, %xmm1
1145 ; CHECK: %xmm0 = VPANDNrm %xmm0, %rip, 1, _, %rax, _
1146 %xmm0 = VPANDNQZ128rm %xmm0, %rip, 1, _, %rax, _
1147 ; CHECK: %xmm0 = VPANDNrr %xmm0, %xmm1
1148 %xmm0 = VPANDNQZ128rr %xmm0, %xmm1
11211149 ; CHECK: %xmm0 = VPAVGBrm %xmm0, %rip, 1, _, %rax, _
11221150 %xmm0 = VPAVGBZ128rm %xmm0, %rip, 1, _, %rax, _
11231151 ; CHECK: %xmm0 = VPAVGBrr %xmm0, %xmm1
17061734 %xmm0 = VPBROADCASTWZ128m %rip, _, _, _, _
17071735 ; CHECK: %xmm0 = VPBROADCASTWrr %xmm0
17081736 %xmm0 = VPBROADCASTWZ128r %xmm0
1737 ; CHECK: %xmm0 = VPBROADCASTQrm %rip, _, _, _, _
1738 %xmm0 = VBROADCASTI32X2Z128m %rip, _, _, _, _
1739 ; CHECK: %xmm0 = VPBROADCASTQrr %xmm0
1740 %xmm0 = VBROADCASTI32X2Z128r %xmm0
17091741 ; CHECK: %xmm0 = VCVTPS2PHrr %xmm0, 2
17101742 %xmm0 = VCVTPS2PHZ128rr %xmm0, 2
17111743 ; CHECK: VCVTPS2PHmr %rdi, %xmm0, 1, _, 0, _, _
17771809 %xmm0 = VMAXCSSZrm %xmm0, %rip, 1, _, %rax, _
17781810 ; CHECK: %xmm0 = VMAXCSSrr %xmm0, %xmm1
17791811 %xmm0 = VMAXCSSZrr %xmm0, %xmm1
1780 ; CHECK: %xmm0 = VMAXSDrm %xmm0, %rip, 1, _, %rax, _
1812 ; CHECK: %xmm0 = VMAXCSDrm %xmm0, %rip, 1, _, %rax, _
17811813 %xmm0 = VMAXSDZrm %xmm0, %rip, 1, _, %rax, _
17821814 ; CHECK: %xmm0 = VMAXSDrm_Int %xmm0, %rip, 1, _, %rax, _
17831815 %xmm0 = VMAXSDZrm_Int %xmm0, %rip, 1, _, %rax, _
1784 ; CHECK: %xmm0 = VMAXSDrr %xmm0, %xmm1
1816 ; CHECK: %xmm0 = VMAXCSDrr %xmm0, %xmm1
17851817 %xmm0 = VMAXSDZrr %xmm0, %xmm1
17861818 ; CHECK: %xmm0 = VMAXSDrr_Int %xmm0, %xmm1
17871819 %xmm0 = VMAXSDZrr_Int %xmm0, %xmm1
1788 ; CHECK: %xmm0 = VMAXSSrm %xmm0, %rip, 1, _, %rax, _
1820 ; CHECK: %xmm0 = VMAXCSSrm %xmm0, %rip, 1, _, %rax, _
17891821 %xmm0 = VMAXSSZrm %xmm0, %rip, 1, _, %rax, _
17901822 ; CHECK: %xmm0 = VMAXSSrm_Int %xmm0, %rip, 1, _, %rax, _
17911823 %xmm0 = VMAXSSZrm_Int %xmm0, %rip, 1, _, %rax, _
1792 ; CHECK: %xmm0 = VMAXSSrr %xmm0, %xmm1
1824 ; CHECK: %xmm0 = VMAXCSSrr %xmm0, %xmm1
17931825 %xmm0 = VMAXSSZrr %xmm0, %xmm1
17941826 ; CHECK: %xmm0 = VMAXSSrr_Int %xmm0, %xmm1
17951827 %xmm0 = VMAXSSZrr_Int %xmm0, %xmm1
18011833 %xmm0 = VMINCSSZrm %xmm0, %rip, 1, _, %rax, _
18021834 ; CHECK: %xmm0 = VMINCSSrr %xmm0, %xmm1
18031835 %xmm0 = VMINCSSZrr %xmm0, %xmm1
1804 ; CHECK: %xmm0 = VMINSDrm %xmm0, %rip, 1, _, %rax, _
1836 ; CHECK: %xmm0 = VMINCSDrm %xmm0, %rip, 1, _, %rax, _
18051837 %xmm0 = VMINSDZrm %xmm0, %rip, 1, _, %rax, _
18061838 ; CHECK: %xmm0 = VMINSDrm_Int %xmm0, %rip, 1, _, %rax, _
18071839 %xmm0 = VMINSDZrm_Int %xmm0, %rip, 1, _, %rax, _
1808 ; CHECK: %xmm0 = VMINSDrr %xmm0, %xmm1
1840 ; CHECK: %xmm0 = VMINCSDrr %xmm0, %xmm1
18091841 %xmm0 = VMINSDZrr %xmm0, %xmm1
18101842 ; CHECK: %xmm0 = VMINSDrr_Int %xmm0, %xmm1
18111843 %xmm0 = VMINSDZrr_Int %xmm0, %xmm1
1812 ; CHECK: %xmm0 = VMINSSrm %xmm0, %rip, 1, _, %rax, _
1844 ; CHECK: %xmm0 = VMINCSSrm %xmm0, %rip, 1, _, %rax, _
18131845 %xmm0 = VMINSSZrm %xmm0, %rip, 1, _, %rax, _
18141846 ; CHECK: %xmm0 = VMINSSrm_Int %xmm0, %rip, 1, _, %rax, _
18151847 %xmm0 = VMINSSZrm_Int %xmm0, %rip, 1, _, %rax, _
1816 ; CHECK: %xmm0 = VMINSSrr %xmm0, %xmm1
1848 ; CHECK: %xmm0 = VMINCSSrr %xmm0, %xmm1
18171849 %xmm0 = VMINSSZrr %xmm0, %xmm1
18181850 ; CHECK: %xmm0 = VMINSSrr_Int %xmm0, %xmm1
18191851 %xmm0 = VMINSSZrr_Int %xmm0, %xmm1
20572089 VPEXTRWZmr %rdi, 1, _, 0, _, %xmm0, 3
20582090 ; CHECK: %eax = VPEXTRWri %xmm0, 1
20592091 %eax = VPEXTRWZrr %xmm0, 1
2092 ; CHECK: %eax = VPEXTRWrr_REV %xmm0, 1
2093 %eax = VPEXTRWZrr_REV %xmm0, 1
20602094 ; CHECK: %xmm0 = VPINSRBrm %xmm0, %rsi, 1, _, 0, _, 3
20612095 %xmm0 = VPINSRBZrm %xmm0, %rsi, 1, _, 0, _, 3
20622096 ; CHECK: %xmm0 = VPINSRBrr %xmm0, %edi, 5
20892123 %xmm0 = VSQRTSSZr %xmm0, _
20902124 ; CHECK: %xmm0 = VSQRTSSr_Int %xmm0, _
20912125 %xmm0 = VSQRTSSZr_Int %xmm0, _
2092 ; CHECK: %rdi = VCVTSD2SI64rm %rdi, %xmm0, 1, _, 0
2093 %rdi = VCVTSD2SI64Zrm %rdi, %xmm0, 1, _, 0
20942126 ; CHECK: %rdi = VCVTSD2SI64rr %xmm0
20952127 %rdi = VCVTSD2SI64Zrr %xmm0
2096 ; CHECK: %edi = VCVTSD2SIrm %rdi, %xmm0, 1, _, 0
2097 %edi = VCVTSD2SIZrm %rdi, %xmm0, 1, _, 0
20982128 ; CHECK: %edi = VCVTSD2SIrr %xmm0
20992129 %edi = VCVTSD2SIZrr %xmm0
21002130 ; CHECK: %xmm0 = VCVTSD2SSrm %xmm0, %rdi, 1, _, 0, _
21172147 %xmm0 = VCVTSI2SSZrr %xmm0, _
21182148 ; CHECK: %xmm0 = Int_VCVTSI2SSrr %xmm0, _
21192149 %xmm0 = VCVTSI2SSZrr_Int %xmm0, _
2150 ; CHECK: %xmm0 = VCVTSI2SD64rm %xmm0, %rdi, 1, _, 0, _
2151 %xmm0 = VCVTSI642SDZrm %xmm0, %rdi, 1, _, 0, _
2152 ; CHECK: %xmm0 = Int_VCVTSI2SD64rm %xmm0, %rdi, 1, _, 0, _
2153 %xmm0 = VCVTSI642SDZrm_Int %xmm0, %rdi, 1, _, 0, _
2154 ; CHECK: %xmm0 = VCVTSI2SD64rr %xmm0, _
2155 %xmm0 = VCVTSI642SDZrr %xmm0, _
2156 ; CHECK: %xmm0 = Int_VCVTSI2SD64rr %xmm0, _
2157 %xmm0 = VCVTSI642SDZrr_Int %xmm0, _
2158 ; CHECK: %xmm0 = VCVTSI2SS64rm %xmm0, %rdi, 1, _, 0, _
2159 %xmm0 = VCVTSI642SSZrm %xmm0, %rdi, 1, _, 0, _
2160 ; CHECK: %xmm0 = Int_VCVTSI2SS64rm %xmm0, %rdi, 1, _, 0, _
2161 %xmm0 = VCVTSI642SSZrm_Int %xmm0, %rdi, 1, _, 0, _
2162 ; CHECK: %xmm0 = VCVTSI2SS64rr %xmm0, _
2163 %xmm0 = VCVTSI642SSZrr %xmm0, _
2164 ; CHECK: %xmm0 = Int_VCVTSI2SS64rr %xmm0, _
2165 %xmm0 = VCVTSI642SSZrr_Int %xmm0, _
21202166 ; CHECK: %xmm0 = VCVTSS2SDrm %xmm0, %rdi, 1, _, 0, _
21212167 %xmm0 = VCVTSS2SDZrm %xmm0, %rdi, 1, _, 0, _
21222168 ; CHECK: %xmm0 = VCVTSS2SDrr %xmm0, _
21232169 %xmm0 = VCVTSS2SDZrr %xmm0, _
2124 ; CHECK: %rdi = VCVTSS2SI64rm %rdi, %xmm0, 1, _, 0
2125 %rdi = VCVTSS2SI64Zrm %rdi, %xmm0, 1, _, 0
21262170 ; CHECK: %rdi = VCVTSS2SI64rr %xmm0
21272171 %rdi = VCVTSS2SI64Zrr %xmm0
2128 ; CHECK: %edi = VCVTSS2SIrm %rdi, %xmm0, 1, _, 0
2129 %edi = VCVTSS2SIZrm %rdi, %xmm0, 1, _, 0
21302172 ; CHECK: %edi = VCVTSS2SIrr %xmm0
21312173 %edi = VCVTSS2SIZrr %xmm0
21322174 ; CHECK: %rdi = VCVTTSD2SI64rm %rdi, %xmm0, 1, _, 0
21732215 %xmm0 = VMOVSDZrm %rip, _, _, _, _
21742216 ; CHECK: %xmm0 = VMOVSDrr %xmm0, _
21752217 %xmm0 = VMOVSDZrr %xmm0, _
2218 ; CHECK: %xmm0 = VMOVSDrr_REV %xmm0, _
2219 %xmm0 = VMOVSDZrr_REV %xmm0, _
2220 ; CHECK: %rax = VMOVSDto64rr %xmm0
2221 %rax = VMOVSDto64Zrr %xmm0
2222 ; CHECK: VMOVSDto64mr %rdi, %xmm0, _, _, _, _
2223 VMOVSDto64Zmr %rdi, %xmm0, _, _, _, _
21762224 ; CHECK: VMOVSSmr %rdi, %xmm0, _, _, _, _
21772225 VMOVSSZmr %rdi, %xmm0, _, _, _, _
21782226 ; CHECK: %xmm0 = VMOVSSrm %rip, _, _, _, _
21812229 %xmm0 = VMOVSSZrr %xmm0, _
21822230 ; CHECK: %xmm0 = VMOVSSrr_REV %xmm0, _
21832231 %xmm0 = VMOVSSZrr_REV %xmm0, _
2232 ; CHECK: VMOVSS2DImr %rdi, %xmm0, _, _, _, _
2233 VMOVSS2DIZmr %rdi, %xmm0, _, _, _, _
2234 ; CHECK: %eax = VMOVSS2DIrr %xmm0
2235 %eax = VMOVSS2DIZrr %xmm0
21842236 ; CHECK: %xmm0 = VMOV64toPQIrr %rdi
21852237 %xmm0 = VMOV64toPQIZrr %rdi
2238 ; CHECK: %xmm0 = VMOV64toPQIrm %rdi, _, _, _, _
2239 %xmm0 = VMOV64toPQIZrm %rdi, _, _, _, _
21862240 ; CHECK: %xmm0 = VMOV64toSDrr %rdi
21872241 %xmm0 = VMOV64toSDZrr %rdi
21882242 ; CHECK: %xmm0 = VMOVDI2PDIrm %rip, _, _, _, _
21962250 ; CHECK: VMOVPDI2DImr %rdi, %xmm0, _, _, _, _
21972251 VMOVPDI2DIZmr %rdi, %xmm0, _, _, _, _
21982252 ; CHECK: %edi = VMOVPDI2DIrr %xmm0
2199 %edi = VMOVPDI2DIZrr %xmm0
2253 %edi = VMOVPDI2DIZrr %xmm0
2254 ; CHECK: %xmm0 = VMOVPQI2QIrr %xmm0
2255 %xmm0 = VMOVPQI2QIZrr %xmm0
22002256 ; CHECK: VMOVPQI2QImr %rdi, %xmm0, _, _, _, _
22012257 VMOVPQI2QIZmr %rdi, %xmm0, _, _, _, _
22022258 ; CHECK: %rdi = VMOVPQIto64rr %xmm0
22032259 %rdi = VMOVPQIto64Zrr %xmm0
2260 ; CHECK: VMOVPQIto64mr %rdi, %xmm0, _, _, _, _
2261 VMOVPQIto64Zmr %rdi, %xmm0, _, _, _, _
22042262 ; CHECK: %xmm0 = VMOVQI2PQIrm %rip, _, _, _, _
22052263 %xmm0 = VMOVQI2PQIZrm %rip, _, _, _, _
22062264 ; CHECK: %xmm0 = VMOVZPQILo2PQIrr %xmm0
22372295 VUCOMISSZrm %xmm0, %rdi, _, _, _, _, implicit-def %eflags
22382296 ; CHECK: VUCOMISSrr %xmm0, %xmm1, implicit-def %eflags
22392297 VUCOMISSZrr %xmm0, %xmm1, implicit-def %eflags
2298 ; CHECK: VEXTRACTPSmr %rdi, 1, _, 0, _, %xmm0, _
2299 VEXTRACTPSZmr %rdi, 1, _, 0, _, %xmm0, _
2300 ; CHECK: %eax = VEXTRACTPSrr %xmm0, _
2301 %eax = VEXTRACTPSZrr %xmm0, _
2302 ; CHECK: %xmm0 = VINSERTPSrm %xmm0, %rdi, _, _, _, _, _
2303 %xmm0 = VINSERTPSZrm %xmm0, %rdi, _, _, _, _, _
2304 ; CHECK: %xmm0 = VINSERTPSrr %xmm0, %xmm0, _
2305 %xmm0 = VINSERTPSZrr %xmm0, %xmm0, _
22402306
22412307 RET 0, %zmm0, %zmm1
22422308 ...
23492415 %ymm16 = VPANDQZ256rm %ymm16, %rip, 1, _, %rax, _
23502416 ; CHECK: %ymm16 = VPANDQZ256rr %ymm16, %ymm1
23512417 %ymm16 = VPANDQZ256rr %ymm16, %ymm1
2418 ; CHECK: %ymm16 = VPANDNDZ256rm %ymm16, %rip, 1, _, %rax, _
2419 %ymm16 = VPANDNDZ256rm %ymm16, %rip, 1, _, %rax, _
2420 ; CHECK: %ymm16 = VPANDNDZ256rr %ymm16, %ymm1
2421 %ymm16 = VPANDNDZ256rr %ymm16, %ymm1
2422 ; CHECK: %ymm16 = VPANDNQZ256rm %ymm16, %rip, 1, _, %rax, _
2423 %ymm16 = VPANDNQZ256rm %ymm16, %rip, 1, _, %rax, _
2424 ; CHECK: %ymm16 = VPANDNQZ256rr %ymm16, %ymm1
2425 %ymm16 = VPANDNQZ256rr %ymm16, %ymm1
23522426 ; CHECK: %ymm16 = VPAVGBZ256rm %ymm16, %rip, 1, _, %rax, _
23532427 %ymm16 = VPAVGBZ256rm %ymm16, %rip, 1, _, %rax, _
23542428 ; CHECK: %ymm16 = VPAVGBZ256rr %ymm16, %ymm1
29172991 %ymm16 = VPMOVZXWQZ256rm %rip, 1, _, %rax, _
29182992 ; CHECK: %ymm16 = VPMOVZXWQZ256rr %xmm0
29192993 %ymm16 = VPMOVZXWQZ256rr %xmm0
2994 ; CHECK: %ymm16 = VBROADCASTF32X2Z256m %rip, 1, _, %rax, _
2995 %ymm16 = VBROADCASTF32X2Z256m %rip, 1, _, %rax, _
2996 ; CHECK: %ymm16 = VBROADCASTF32X2Z256r %xmm16
2997 %ymm16 = VBROADCASTF32X2Z256r %xmm16
2998 ; CHECK: %ymm16 = VBROADCASTF32X4Z256rm %rip, 1, _, %rax, _
2999 %ymm16 = VBROADCASTF32X4Z256rm %rip, 1, _, %rax, _
29203000 ; CHECK: %ymm16 = VBROADCASTSDZ256m %rip, 1, _, %rax, _
29213001 %ymm16 = VBROADCASTSDZ256m %rip, 1, _, %rax, _
29223002 ; CHECK: %ymm16 = VBROADCASTSDZ256r %xmm0
29373017 %ymm16 = VPBROADCASTWZ256m %rip, 1, _, %rax, _
29383018 ; CHECK: %ymm16 = VPBROADCASTWZ256r %xmm0
29393019 %ymm16 = VPBROADCASTWZ256r %xmm0
3020 ; CHECK: %ymm16 = VBROADCASTI32X4Z256rm %rip, 1, _, %rax, _
3021 %ymm16 = VBROADCASTI32X4Z256rm %rip, 1, _, %rax, _
3022 ; CHECK: %ymm16 = VBROADCASTI32X2Z256m %rip, 1, _, %rax, _
3023 %ymm16 = VBROADCASTI32X2Z256m %rip, 1, _, %rax, _
3024 ; CHECK: %ymm16 = VBROADCASTI32X2Z256r %xmm16
3025 %ymm16 = VBROADCASTI32X2Z256r %xmm16
29403026 ; CHECK: %ymm16 = VPBROADCASTQZ256m %rip, 1, _, %rax, _
29413027 %ymm16 = VPBROADCASTQZ256m %rip, 1, _, %rax, _
29423028 ; CHECK: %ymm16 = VPBROADCASTQZ256r %xmm0
33493435 %xmm16 = VPANDQZ128rm %xmm16, %rip, 1, _, %rax, _
33503436 ; CHECK: %xmm16 = VPANDQZ128rr %xmm16, %xmm1
33513437 %xmm16 = VPANDQZ128rr %xmm16, %xmm1
3438 ; CHECK: %xmm16 = VPANDNDZ128rm %xmm16, %rip, 1, _, %rax, _
3439 %xmm16 = VPANDNDZ128rm %xmm16, %rip, 1, _, %rax, _
3440 ; CHECK: %xmm16 = VPANDNDZ128rr %xmm16, %xmm1
3441 %xmm16 = VPANDNDZ128rr %xmm16, %xmm1
3442 ; CHECK: %xmm16 = VPANDNQZ128rm %xmm16, %rip, 1, _, %rax, _
3443 %xmm16 = VPANDNQZ128rm %xmm16, %rip, 1, _, %rax, _
3444 ; CHECK: %xmm16 = VPANDNQZ128rr %xmm16, %xmm1
3445 %xmm16 = VPANDNQZ128rr %xmm16, %xmm1
33523446 ; CHECK: %xmm16 = VPAVGBZ128rm %xmm16, %rip, 1, _, %rax, _
33533447 %xmm16 = VPAVGBZ128rm %xmm16, %rip, 1, _, %rax, _
33543448 ; CHECK: %xmm16 = VPAVGBZ128rr %xmm16, %xmm1
39374031 %xmm16 = VPBROADCASTWZ128m %rip, _, _, _, _
39384032 ; CHECK: %xmm16 = VPBROADCASTWZ128r %xmm16
39394033 %xmm16 = VPBROADCASTWZ128r %xmm16
4034 ; CHECK: %xmm16 = VBROADCASTI32X2Z128m %rip, _, _, _, _
4035 %xmm16 = VBROADCASTI32X2Z128m %rip, _, _, _, _
4036 ; CHECK: %xmm16 = VBROADCASTI32X2Z128r %xmm0
4037 %xmm16 = VBROADCASTI32X2Z128r %xmm0
39404038 ; CHECK: %xmm16 = VCVTPS2PHZ128rr %xmm16, 2
39414039 %xmm16 = VCVTPS2PHZ128rr %xmm16, 2
39424040 ; CHECK: VCVTPS2PHZ128mr %rdi, %xmm16, 1, _, 0, _, _
39574055 %xmm16 = VPALIGNRZ128rmi %xmm16, _, _, _, _, _, _
39584056 ; CHECK: %xmm16 = VPALIGNRZ128rri %xmm16, %xmm1, 15
39594057 %xmm16 = VPALIGNRZ128rri %xmm16, %xmm1, 15
4058 ; CHECK: VEXTRACTPSZmr %rdi, 1, _, 0, _, %xmm16, _
4059 VEXTRACTPSZmr %rdi, 1, _, 0, _, %xmm16, _
4060 ; CHECK: %eax = VEXTRACTPSZrr %xmm16, _
4061 %eax = VEXTRACTPSZrr %xmm16, _
4062 ; CHECK: %xmm16 = VINSERTPSZrm %xmm16, %rdi, _, _, _, _, _
4063 %xmm16 = VINSERTPSZrm %xmm16, %rdi, _, _, _, _, _
4064 ; CHECK: %xmm16 = VINSERTPSZrr %xmm16, %xmm16, _
4065 %xmm16 = VINSERTPSZrr %xmm16, %xmm16, _
39604066
39614067 RET 0, %zmm0, %zmm1
39624068 ...
42874393 VPEXTRWZmr %rdi, 1, _, 0, _, %xmm16, 3
42884394 ; CHECK: %eax = VPEXTRWZrr %xmm16, 1
42894395 %eax = VPEXTRWZrr %xmm16, 1
4396 ; CHECK: %eax = VPEXTRWZrr_REV %xmm16, 1
4397 %eax = VPEXTRWZrr_REV %xmm16, 1
42904398 ; CHECK: %xmm16 = VPINSRBZrm %xmm16, %rsi, 1, _, 0, _, 3
42914399 %xmm16 = VPINSRBZrm %xmm16, %rsi, 1, _, 0, _, 3
42924400 ; CHECK: %xmm16 = VPINSRBZrr %xmm16, %edi, 5
43474455 %xmm16 = VCVTSI2SSZrr %xmm16, _
43484456 ; CHECK: %xmm16 = VCVTSI2SSZrr_Int %xmm16, _
43494457 %xmm16 = VCVTSI2SSZrr_Int %xmm16, _
4458 ; CHECK: %xmm16 = VCVTSI642SDZrm %xmm16, %rdi, 1, _, 0, _
4459 %xmm16 = VCVTSI642SDZrm %xmm16, %rdi, 1, _, 0, _
4460 ; CHECK: %xmm16 = VCVTSI642SDZrm_Int %xmm16, %rdi, 1, _, 0, _
4461 %xmm16 = VCVTSI642SDZrm_Int %xmm16, %rdi, 1, _, 0, _
4462 ; CHECK: %xmm16 = VCVTSI642SDZrr %xmm16, _
4463 %xmm16 = VCVTSI642SDZrr %xmm16, _
4464 ; CHECK: %xmm16 = VCVTSI642SDZrr_Int %xmm16, _
4465 %xmm16 = VCVTSI642SDZrr_Int %xmm16, _
4466 ; CHECK: %xmm16 = VCVTSI642SSZrm %xmm16, %rdi, 1, _, 0, _
4467 %xmm16 = VCVTSI642SSZrm %xmm16, %rdi, 1, _, 0, _
4468 ; CHECK: %xmm16 = VCVTSI642SSZrm_Int %xmm16, %rdi, 1, _, 0, _
4469 %xmm16 = VCVTSI642SSZrm_Int %xmm16, %rdi, 1, _, 0, _
4470 ; CHECK: %xmm16 = VCVTSI642SSZrr %xmm16, _
4471 %xmm16 = VCVTSI642SSZrr %xmm16, _
4472 ; CHECK: %xmm16 = VCVTSI642SSZrr_Int %xmm16, _
4473 %xmm16 = VCVTSI642SSZrr_Int %xmm16, _
43504474 ; CHECK: %xmm16 = VCVTSS2SDZrm %xmm16, %rdi, 1, _, 0, _
43514475 %xmm16 = VCVTSS2SDZrm %xmm16, %rdi, 1, _, 0, _
43524476 ; CHECK: %xmm16 = VCVTSS2SDZrr %xmm16, _
44034527 %xmm16 = VMOVSDZrm %rip, _, _, _, _
44044528 ; CHECK: %xmm16 = VMOVSDZrr %xmm16, _
44054529 %xmm16 = VMOVSDZrr %xmm16, _
4530 ; CHECK: %xmm16 = VMOVSDZrr_REV %xmm16, _
4531 %xmm16 = VMOVSDZrr_REV %xmm16, _
4532 ; CHECK: %rax = VMOVSDto64Zrr %xmm16
4533 %rax = VMOVSDto64Zrr %xmm16
4534 ; CHECK: VMOVSDto64Zmr %rdi, %xmm16, _, _, _, _
4535 VMOVSDto64Zmr %rdi, %xmm16, _, _, _, _
44064536 ; CHECK: VMOVSSZmr %rdi, %xmm16, _, _, _, _
44074537 VMOVSSZmr %rdi, %xmm16, _, _, _, _
44084538 ; CHECK: %xmm16 = VMOVSSZrm %rip, _, _, _, _
44114541 %xmm16 = VMOVSSZrr %xmm16, _
44124542 ; CHECK: %xmm16 = VMOVSSZrr_REV %xmm16, _
44134543 %xmm16 = VMOVSSZrr_REV %xmm16, _
4544 ; CHECK: VMOVSS2DIZmr %rdi, %xmm16, _, _, _, _
4545 VMOVSS2DIZmr %rdi, %xmm16, _, _, _, _
4546 ; CHECK: %eax = VMOVSS2DIZrr %xmm16
4547 %eax = VMOVSS2DIZrr %xmm16
44144548 ; CHECK: %xmm16 = VMOV64toPQIZrr %rdi
44154549 %xmm16 = VMOV64toPQIZrr %rdi
4550 ; CHECK: %xmm16 = VMOV64toPQIZrm %rdi, _, _, _, _
4551 %xmm16 = VMOV64toPQIZrm %rdi, _, _, _, _
44164552 ; CHECK: %xmm16 = VMOV64toSDZrr %rdi
44174553 %xmm16 = VMOV64toSDZrr %rdi
44184554 ; CHECK: %xmm16 = VMOVDI2PDIZrm %rip, _, _, _, _
44274563 VMOVPDI2DIZmr %rdi, %xmm16, _, _, _, _
44284564 ; CHECK: %edi = VMOVPDI2DIZrr %xmm16
44294565 %edi = VMOVPDI2DIZrr %xmm16
4566 ; CHECK: %xmm16 = VMOVPQI2QIZrr %xmm16
4567 %xmm16 = VMOVPQI2QIZrr %xmm16
44304568 ; CHECK: VMOVPQI2QIZmr %rdi, %xmm16, _, _, _, _
44314569 VMOVPQI2QIZmr %rdi, %xmm16, _, _, _, _
44324570 ; CHECK: %rdi = VMOVPQIto64Zrr %xmm16
44334571 %rdi = VMOVPQIto64Zrr %xmm16
4572 ; CHECK: VMOVPQIto64Zmr %rdi, %xmm16, _, _, _, _
4573 VMOVPQIto64Zmr %rdi, %xmm16, _, _, _, _
44344574 ; CHECK: %xmm16 = VMOVQI2PQIZrm %rip, _, _, _, _
44354575 %xmm16 = VMOVQI2PQIZrm %rip, _, _, _, _
44364576 ; CHECK: %xmm16 = VMOVZPQILo2PQIZrr %xmm16
4444 ;
4545 ; SKX-LABEL: test_x86_sse_cvtsi642ss:
4646 ; SKX: ## BB#0:
47 ; SKX-NEXT: vcvtsi2ssq %rdi, %xmm0, %xmm0 ## encoding: [0x62,0xf1,0xfe,0x08,0x2a,0xc7]
47 ; SKX-NEXT: vcvtsi2ssq %rdi, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe1,0xfa,0x2a,0xc7]
4848 ; SKX-NEXT: retq ## encoding: [0xc3]
4949 %res = call <4 x float> @llvm.x86.sse.cvtsi642ss(<4 x float> %a0, i64 %a1) ; <<4 x float>> [#uses=1]
5050 ret <4 x float> %res
4444 ;
4545 ; SKX-LABEL: test_x86_sse2_cvtsi642sd:
4646 ; SKX: ## BB#0:
47 ; SKX-NEXT: vcvtsi2sdq %rdi, %xmm0, %xmm0 ## encoding: [0x62,0xf1,0xff,0x08,0x2a,0xc7]
47 ; SKX-NEXT: vcvtsi2sdq %rdi, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe1,0xfb,0x2a,0xc7]
4848 ; SKX-NEXT: retq ## encoding: [0xc3]
4949 %res = call <2 x double> @llvm.x86.sse2.cvtsi642sd(<2 x double> %a0, i64 %a1) ; <<2 x double>> [#uses=1]
5050 ret <2 x double> %res
8787 ;
8888 ; SKX-LABEL: test_x86_sse41_insertps:
8989 ; SKX: ## BB#0:
90 ; SKX-NEXT: vinsertps $17, %xmm1, %xmm0, %xmm0 ## encoding: [0x62,0xf3,0x7d,0x08,0x21,0xc1,0x11]
90 ; SKX-NEXT: vinsertps $17, %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc4,0xe3,0x79,0x21,0xc1,0x11]
9191 ; SKX-NEXT: ## xmm0 = zero,xmm1[0],xmm0[2,3]
9292 ; SKX-NEXT: retl ## encoding: [0xc3]
9393 %res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a0, <4 x float> %a1, i8 17) ; <<4 x float>> [#uses=1]
2323 ; X32-AVX512F-LABEL: test_broadcast_2f64_4f64:
2424 ; X32-AVX512F: ## BB#0:
2525 ; X32-AVX512F-NEXT: movl {{[0-9]+}}(%esp), %eax
26 ; X32-AVX512F-NEXT: vbroadcastf32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
26 ; X32-AVX512F-NEXT: vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
2727 ; X32-AVX512F-NEXT: retl
2828 ;
2929 ; X32-AVX512BW-LABEL: test_broadcast_2f64_4f64:
3030 ; X32-AVX512BW: ## BB#0:
3131 ; X32-AVX512BW-NEXT: movl {{[0-9]+}}(%esp), %eax
32 ; X32-AVX512BW-NEXT: vbroadcastf32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
32 ; X32-AVX512BW-NEXT: vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
3333 ; X32-AVX512BW-NEXT: retl
3434 ;
3535 ; X32-AVX512DQ-LABEL: test_broadcast_2f64_4f64:
4545 ;
4646 ; X64-AVX512F-LABEL: test_broadcast_2f64_4f64:
4747 ; X64-AVX512F: ## BB#0:
48 ; X64-AVX512F-NEXT: vbroadcastf32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
48 ; X64-AVX512F-NEXT: vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
4949 ; X64-AVX512F-NEXT: retq
5050 ;
5151 ; X64-AVX512BW-LABEL: test_broadcast_2f64_4f64:
5252 ; X64-AVX512BW: ## BB#0:
53 ; X64-AVX512BW-NEXT: vbroadcastf32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
53 ; X64-AVX512BW-NEXT: vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
5454 ; X64-AVX512BW-NEXT: retq
5555 ;
5656 ; X64-AVX512DQ-LABEL: test_broadcast_2f64_4f64:
152152 ; X32-AVX512F-LABEL: test_broadcast_2i64_4i64:
153153 ; X32-AVX512F: ## BB#0:
154154 ; X32-AVX512F-NEXT: movl {{[0-9]+}}(%esp), %eax
155 ; X32-AVX512F-NEXT: vbroadcasti32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
155 ; X32-AVX512F-NEXT: vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
156156 ; X32-AVX512F-NEXT: retl
157157 ;
158158 ; X32-AVX512BW-LABEL: test_broadcast_2i64_4i64:
159159 ; X32-AVX512BW: ## BB#0:
160160 ; X32-AVX512BW-NEXT: movl {{[0-9]+}}(%esp), %eax
161 ; X32-AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
161 ; X32-AVX512BW-NEXT: vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
162162 ; X32-AVX512BW-NEXT: retl
163163 ;
164164 ; X32-AVX512DQ-LABEL: test_broadcast_2i64_4i64:
174174 ;
175175 ; X64-AVX512F-LABEL: test_broadcast_2i64_4i64:
176176 ; X64-AVX512F: ## BB#0:
177 ; X64-AVX512F-NEXT: vbroadcasti32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
177 ; X64-AVX512F-NEXT: vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
178178 ; X64-AVX512F-NEXT: retq
179179 ;
180180 ; X64-AVX512BW-LABEL: test_broadcast_2i64_4i64:
181181 ; X64-AVX512BW: ## BB#0:
182 ; X64-AVX512BW-NEXT: vbroadcasti32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
182 ; X64-AVX512BW-NEXT: vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
183183 ; X64-AVX512BW-NEXT: retq
184184 ;
185185 ; X64-AVX512DQ-LABEL: test_broadcast_2i64_4i64:
285285 }
286286
287287 define <8 x float> @test_broadcast_4f32_8f32(<4 x float> *%p) nounwind {
288 ; X32-AVX-LABEL: test_broadcast_4f32_8f32:
289 ; X32-AVX: ## BB#0:
290 ; X32-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
291 ; X32-AVX-NEXT: vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
292 ; X32-AVX-NEXT: retl
293 ;
294 ; X32-AVX512-LABEL: test_broadcast_4f32_8f32:
295 ; X32-AVX512: ## BB#0:
296 ; X32-AVX512-NEXT: movl {{[0-9]+}}(%esp), %eax
297 ; X32-AVX512-NEXT: vbroadcastf32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
298 ; X32-AVX512-NEXT: retl
299 ;
300 ; X64-AVX-LABEL: test_broadcast_4f32_8f32:
301 ; X64-AVX: ## BB#0:
302 ; X64-AVX-NEXT: vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
303 ; X64-AVX-NEXT: retq
304 ;
305 ; X64-AVX512-LABEL: test_broadcast_4f32_8f32:
306 ; X64-AVX512: ## BB#0:
307 ; X64-AVX512-NEXT: vbroadcastf32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
308 ; X64-AVX512-NEXT: retq
288 ; X32-LABEL: test_broadcast_4f32_8f32:
289 ; X32: ## BB#0:
290 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
291 ; X32-NEXT: vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
292 ; X32-NEXT: retl
293 ;
294 ; X64-LABEL: test_broadcast_4f32_8f32:
295 ; X64: ## BB#0:
296 ; X64-NEXT: vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
297 ; X64-NEXT: retq
309298 %1 = load <4 x float>, <4 x float> *%p
310299 %2 = shufflevector <4 x float> %1, <4 x float> undef, <8 x i32>
311300 ret <8 x float> %2
401390 ; X32-AVX512-LABEL: test_broadcast_4i32_8i32:
402391 ; X32-AVX512: ## BB#0:
403392 ; X32-AVX512-NEXT: movl {{[0-9]+}}(%esp), %eax
404 ; X32-AVX512-NEXT: vbroadcasti32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
393 ; X32-AVX512-NEXT: vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
405394 ; X32-AVX512-NEXT: retl
406395 ;
407396 ; X64-AVX-LABEL: test_broadcast_4i32_8i32:
411400 ;
412401 ; X64-AVX512-LABEL: test_broadcast_4i32_8i32:
413402 ; X64-AVX512: ## BB#0:
414 ; X64-AVX512-NEXT: vbroadcasti32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
403 ; X64-AVX512-NEXT: vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
415404 ; X64-AVX512-NEXT: retq
416405 %1 = load <4 x i32>, <4 x i32> *%p
417406 %2 = shufflevector <4 x i32> %1, <4 x i32> undef, <8 x i32>
521510 ; X32-AVX512-LABEL: test_broadcast_8i16_16i16:
522511 ; X32-AVX512: ## BB#0:
523512 ; X32-AVX512-NEXT: movl {{[0-9]+}}(%esp), %eax
524 ; X32-AVX512-NEXT: vbroadcasti32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
513 ; X32-AVX512-NEXT: vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
525514 ; X32-AVX512-NEXT: retl
526515 ;
527516 ; X64-AVX-LABEL: test_broadcast_8i16_16i16:
531520 ;
532521 ; X64-AVX512-LABEL: test_broadcast_8i16_16i16:
533522 ; X64-AVX512: ## BB#0:
534 ; X64-AVX512-NEXT: vbroadcasti32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
523 ; X64-AVX512-NEXT: vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
535524 ; X64-AVX512-NEXT: retq
536525 %1 = load <8 x i16>, <8 x i16> *%p
537526 %2 = shufflevector <8 x i16> %1, <8 x i16> undef, <16 x i32>
556545 ; X32-AVX512F-LABEL: test_broadcast_8i16_32i16:
557546 ; X32-AVX512F: ## BB#0:
558547 ; X32-AVX512F-NEXT: movl {{[0-9]+}}(%esp), %eax
559 ; X32-AVX512F-NEXT: vbroadcasti32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
548 ; X32-AVX512F-NEXT: vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
560549 ; X32-AVX512F-NEXT: vmovdqa %ymm0, %ymm1
561550 ; X32-AVX512F-NEXT: retl
562551 ;
569558 ; X32-AVX512DQ-LABEL: test_broadcast_8i16_32i16:
570559 ; X32-AVX512DQ: ## BB#0:
571560 ; X32-AVX512DQ-NEXT: movl {{[0-9]+}}(%esp), %eax
572 ; X32-AVX512DQ-NEXT: vbroadcasti32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
561 ; X32-AVX512DQ-NEXT: vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
573562 ; X32-AVX512DQ-NEXT: vmovdqa %ymm0, %ymm1
574563 ; X32-AVX512DQ-NEXT: retl
575564 ;
587576 ;
588577 ; X64-AVX512F-LABEL: test_broadcast_8i16_32i16:
589578 ; X64-AVX512F: ## BB#0:
590 ; X64-AVX512F-NEXT: vbroadcasti32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
579 ; X64-AVX512F-NEXT: vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
591580 ; X64-AVX512F-NEXT: vmovdqa %ymm0, %ymm1
592581 ; X64-AVX512F-NEXT: retq
593582 ;
598587 ;
599588 ; X64-AVX512DQ-LABEL: test_broadcast_8i16_32i16:
600589 ; X64-AVX512DQ: ## BB#0:
601 ; X64-AVX512DQ-NEXT: vbroadcasti32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
590 ; X64-AVX512DQ-NEXT: vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
602591 ; X64-AVX512DQ-NEXT: vmovdqa %ymm0, %ymm1
603592 ; X64-AVX512DQ-NEXT: retq
604593 %1 = load <8 x i16>, <8 x i16> *%p
671660 ; X32-AVX512-LABEL: test_broadcast_16i8_32i8:
672661 ; X32-AVX512: ## BB#0:
673662 ; X32-AVX512-NEXT: movl {{[0-9]+}}(%esp), %eax
674 ; X32-AVX512-NEXT: vbroadcasti32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
663 ; X32-AVX512-NEXT: vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
675664 ; X32-AVX512-NEXT: retl
676665 ;
677666 ; X64-AVX-LABEL: test_broadcast_16i8_32i8:
681670 ;
682671 ; X64-AVX512-LABEL: test_broadcast_16i8_32i8:
683672 ; X64-AVX512: ## BB#0:
684 ; X64-AVX512-NEXT: vbroadcasti32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
673 ; X64-AVX512-NEXT: vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
685674 ; X64-AVX512-NEXT: retq
686675 %1 = load <16 x i8>, <16 x i8> *%p
687676 %2 = shufflevector <16 x i8> %1, <16 x i8> undef, <32 x i32>
706695 ; X32-AVX512F-LABEL: test_broadcast_16i8_64i8:
707696 ; X32-AVX512F: ## BB#0:
708697 ; X32-AVX512F-NEXT: movl {{[0-9]+}}(%esp), %eax
709 ; X32-AVX512F-NEXT: vbroadcasti32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
698 ; X32-AVX512F-NEXT: vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
710699 ; X32-AVX512F-NEXT: vmovdqa %ymm0, %ymm1
711700 ; X32-AVX512F-NEXT: retl
712701 ;
719708 ; X32-AVX512DQ-LABEL: test_broadcast_16i8_64i8:
720709 ; X32-AVX512DQ: ## BB#0:
721710 ; X32-AVX512DQ-NEXT: movl {{[0-9]+}}(%esp), %eax
722 ; X32-AVX512DQ-NEXT: vbroadcasti32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
711 ; X32-AVX512DQ-NEXT: vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
723712 ; X32-AVX512DQ-NEXT: vmovdqa %ymm0, %ymm1
724713 ; X32-AVX512DQ-NEXT: retl
725714 ;
737726 ;
738727 ; X64-AVX512F-LABEL: test_broadcast_16i8_64i8:
739728 ; X64-AVX512F: ## BB#0:
740 ; X64-AVX512F-NEXT: vbroadcasti32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
729 ; X64-AVX512F-NEXT: vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
741730 ; X64-AVX512F-NEXT: vmovdqa %ymm0, %ymm1
742731 ; X64-AVX512F-NEXT: retq
743732 ;
748737 ;
749738 ; X64-AVX512DQ-LABEL: test_broadcast_16i8_64i8:
750739 ; X64-AVX512DQ: ## BB#0:
751 ; X64-AVX512DQ-NEXT: vbroadcasti32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
740 ; X64-AVX512DQ-NEXT: vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
752741 ; X64-AVX512DQ-NEXT: vmovdqa %ymm0, %ymm1
753742 ; X64-AVX512DQ-NEXT: retq
754743 %1 = load <16 x i8>, <16 x i8> *%p
13751375 ;
13761376 ; AVX512VL-LABEL: splat128_mem_v4i64_from_v2i64:
13771377 ; AVX512VL: # BB#0:
1378 ; AVX512VL-NEXT: vbroadcasti32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
1378 ; AVX512VL-NEXT: vbroadcasti128 {{.*#+}} ymm0 = mem[0,1,0,1]
13791379 ; AVX512VL-NEXT: retq
13801380 %v = load <2 x i64>, <2 x i64>* %ptr
13811381 %shuffle = shufflevector <2 x i64> %v, <2 x i64> undef, <4 x i32>
13831383 }
13841384
13851385 define <4 x double> @splat128_mem_v4f64_from_v2f64(<2 x double>* %ptr) {
1386 ; AVX1-LABEL: splat128_mem_v4f64_from_v2f64:
1387 ; AVX1: # BB#0:
1388 ; AVX1-NEXT: vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
1389 ; AVX1-NEXT: retq
1390 ;
1391 ; AVX2-LABEL: splat128_mem_v4f64_from_v2f64:
1392 ; AVX2: # BB#0:
1393 ; AVX2-NEXT: vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
1394 ; AVX2-NEXT: retq
1395 ;
1396 ; AVX512VL-LABEL: splat128_mem_v4f64_from_v2f64:
1397 ; AVX512VL: # BB#0:
1398 ; AVX512VL-NEXT: vbroadcastf32x4 {{.*#+}} ymm0 = mem[0,1,2,3,0,1,2,3]
1399 ; AVX512VL-NEXT: retq
1386 ; ALL-LABEL: splat128_mem_v4f64_from_v2f64:
1387 ; ALL: # BB#0:
1388 ; ALL-NEXT: vbroadcastf128 {{.*#+}} ymm0 = mem[0,1,0,1]
1389 ; ALL-NEXT: retq
14001390 %v = load <2 x double>, <2 x double>* %ptr
14011391 %shuffle = shufflevector <2 x double> %v, <2 x double> undef, <4 x i32>
14021392 ret <4 x double> %shuffle
3030 ; Sorry 16-bit, you're not important enough to support?
3131
3232 define <8 x i16> @signbit_sel_v8i16(<8 x i16> %x, <8 x i16> %y, <8 x i16> %mask) {
33 ; AVX12F-LABEL: signbit_sel_v8i16:
34 ; AVX12F: # BB#0:
35 ; AVX12F-NEXT: vpxor %xmm3, %xmm3, %xmm3
36 ; AVX12F-NEXT: vpcmpgtw %xmm2, %xmm3, %xmm2
37 ; AVX12F-NEXT: vpandn %xmm1, %xmm2, %xmm1
38 ; AVX12F-NEXT: vpand %xmm2, %xmm0, %xmm0
39 ; AVX12F-NEXT: vpor %xmm1, %xmm0, %xmm0
40 ; AVX12F-NEXT: retq
41 ;
42 ; AVX512VL-LABEL: signbit_sel_v8i16:
43 ; AVX512VL: # BB#0:
44 ; AVX512VL-NEXT: vpxor %xmm3, %xmm3, %xmm3
45 ; AVX512VL-NEXT: vpcmpgtw %xmm2, %xmm3, %xmm2
46 ; AVX512VL-NEXT: vpandnq %xmm1, %xmm2, %xmm1
47 ; AVX512VL-NEXT: vpand %xmm2, %xmm0, %xmm0
48 ; AVX512VL-NEXT: vpor %xmm1, %xmm0, %xmm0
49 ; AVX512VL-NEXT: retq
33 ; AVX-LABEL: signbit_sel_v8i16:
34 ; AVX: # BB#0:
35 ; AVX-NEXT: vpxor %xmm3, %xmm3, %xmm3
36 ; AVX-NEXT: vpcmpgtw %xmm2, %xmm3, %xmm2
37 ; AVX-NEXT: vpandn %xmm1, %xmm2, %xmm1
38 ; AVX-NEXT: vpand %xmm2, %xmm0, %xmm0
39 ; AVX-NEXT: vpor %xmm1, %xmm0, %xmm0
40 ; AVX-NEXT: retq
5041 %tr = icmp slt <8 x i16> %mask, zeroinitializer
5142 %z = select <8 x i1> %tr, <8 x i16> %x, <8 x i16> %y
5243 ret <8 x i16> %z
175166 ; AVX2-NEXT: vpor %ymm1, %ymm0, %ymm0
176167 ; AVX2-NEXT: retq
177168 ;
178 ; AVX512F-LABEL: signbit_sel_v16i16:
179 ; AVX512F: # BB#0:
180 ; AVX512F-NEXT: vpxor %ymm3, %ymm3, %ymm3
181 ; AVX512F-NEXT: vpcmpgtw %ymm2, %ymm3, %ymm2
182 ; AVX512F-NEXT: vpandn %ymm1, %ymm2, %ymm1
183 ; AVX512F-NEXT: vpand %ymm2, %ymm0, %ymm0
184 ; AVX512F-NEXT: vpor %ymm1, %ymm0, %ymm0
185 ; AVX512F-NEXT: retq
186 ;
187 ; AVX512VL-LABEL: signbit_sel_v16i16:
188 ; AVX512VL: # BB#0:
189 ; AVX512VL-NEXT: vpxor %ymm3, %ymm3, %ymm3
190 ; AVX512VL-NEXT: vpcmpgtw %ymm2, %ymm3, %ymm2
191 ; AVX512VL-NEXT: vpandnq %ymm1, %ymm2, %ymm1
192 ; AVX512VL-NEXT: vpand %ymm2, %ymm0, %ymm0
193 ; AVX512VL-NEXT: vpor %ymm1, %ymm0, %ymm0
194 ; AVX512VL-NEXT: retq
169 ; AVX512-LABEL: signbit_sel_v16i16:
170 ; AVX512: # BB#0:
171 ; AVX512-NEXT: vpxor %ymm3, %ymm3, %ymm3
172 ; AVX512-NEXT: vpcmpgtw %ymm2, %ymm3, %ymm2
173 ; AVX512-NEXT: vpandn %ymm1, %ymm2, %ymm1
174 ; AVX512-NEXT: vpand %ymm2, %ymm0, %ymm0
175 ; AVX512-NEXT: vpor %ymm1, %ymm0, %ymm0
176 ; AVX512-NEXT: retq
195177 %tr = icmp slt <16 x i16> %mask, zeroinitializer
196178 %z = select <16 x i1> %tr, <16 x i16> %x, <16 x i16> %y
197179 ret <16 x i16> %z