llvm.org GIT mirror llvm / 825b72b
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while the latter is capable of representing either a primitive or an extended type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78713 91177308-0d34-0410-b5e6-96231b3b80d8 Owen Anderson 10 years ago
86 changed file(s) with 5846 addition(s) and 5744 deletion(s). Raw diff Collapse all Expand all
3434 return false;
3535 if (Chain->getNumOperands() > 0) {
3636 SDValue C0 = Chain->getOperand(0);
37 if (C0.getValueType() == EVT::Other)
37 if (C0.getValueType() == MVT::Other)
3838 return C0.getNode() != Op && IsChainCompatible(C0.getNode(), Op);
3939 }
4040 return true;
136136 /// FastEmit_r - This method is called by target-independent code
137137 /// to request that an instruction with the given type and opcode
138138 /// be emitted.
139 virtual unsigned FastEmit_(EVT::SimpleValueType VT,
140 EVT::SimpleValueType RetVT,
139 virtual unsigned FastEmit_(MVT VT,
140 MVT RetVT,
141141 ISD::NodeType Opcode);
142142
143143 /// FastEmit_r - This method is called by target-independent code
144144 /// to request that an instruction with the given type, opcode, and
145145 /// register operand be emitted.
146146 ///
147 virtual unsigned FastEmit_r(EVT::SimpleValueType VT,
148 EVT::SimpleValueType RetVT,
147 virtual unsigned FastEmit_r(MVT VT,
148 MVT RetVT,
149149 ISD::NodeType Opcode, unsigned Op0);
150150
151151 /// FastEmit_rr - This method is called by target-independent code
152152 /// to request that an instruction with the given type, opcode, and
153153 /// register operands be emitted.
154154 ///
155 virtual unsigned FastEmit_rr(EVT::SimpleValueType VT,
156 EVT::SimpleValueType RetVT,
155 virtual unsigned FastEmit_rr(MVT VT,
156 MVT RetVT,
157157 ISD::NodeType Opcode,
158158 unsigned Op0, unsigned Op1);
159159
161161 /// to request that an instruction with the given type, opcode, and
162162 /// register and immediate operands be emitted.
163163 ///
164 virtual unsigned FastEmit_ri(EVT::SimpleValueType VT,
165 EVT::SimpleValueType RetVT,
164 virtual unsigned FastEmit_ri(MVT VT,
165 MVT RetVT,
166166 ISD::NodeType Opcode,
167167 unsigned Op0, uint64_t Imm);
168168
170170 /// to request that an instruction with the given type, opcode, and
171171 /// register and floating-point immediate operands be emitted.
172172 ///
173 virtual unsigned FastEmit_rf(EVT::SimpleValueType VT,
174 EVT::SimpleValueType RetVT,
173 virtual unsigned FastEmit_rf(MVT VT,
174 MVT RetVT,
175175 ISD::NodeType Opcode,
176176 unsigned Op0, ConstantFP *FPImm);
177177
179179 /// to request that an instruction with the given type, opcode, and
180180 /// register and immediate operands be emitted.
181181 ///
182 virtual unsigned FastEmit_rri(EVT::SimpleValueType VT,
183 EVT::SimpleValueType RetVT,
182 virtual unsigned FastEmit_rri(MVT VT,
183 MVT RetVT,
184184 ISD::NodeType Opcode,
185185 unsigned Op0, unsigned Op1, uint64_t Imm);
186186
188188 /// to emit an instruction with an immediate operand using FastEmit_ri.
189189 /// If that fails, it materializes the immediate into a register and try
190190 /// FastEmit_rr instead.
191 unsigned FastEmit_ri_(EVT::SimpleValueType VT,
191 unsigned FastEmit_ri_(MVT VT,
192192 ISD::NodeType Opcode,
193193 unsigned Op0, uint64_t Imm,
194 EVT::SimpleValueType ImmType);
194 MVT ImmType);
195195
196196 /// FastEmit_rf_ - This method is a wrapper of FastEmit_rf. It first tries
197197 /// to emit an instruction with an immediate operand using FastEmit_rf.
198198 /// If that fails, it materializes the immediate into a register and try
199199 /// FastEmit_rr instead.
200 unsigned FastEmit_rf_(EVT::SimpleValueType VT,
200 unsigned FastEmit_rf_(MVT VT,
201201 ISD::NodeType Opcode,
202202 unsigned Op0, ConstantFP *FPImm,
203 EVT::SimpleValueType ImmType);
203 MVT ImmType);
204204
205205 /// FastEmit_i - This method is called by target-independent code
206206 /// to request that an instruction with the given type, opcode, and
207207 /// immediate operand be emitted.
208 virtual unsigned FastEmit_i(EVT::SimpleValueType VT,
209 EVT::SimpleValueType RetVT,
208 virtual unsigned FastEmit_i(MVT VT,
209 MVT RetVT,
210210 ISD::NodeType Opcode,
211211 uint64_t Imm);
212212
213213 /// FastEmit_f - This method is called by target-independent code
214214 /// to request that an instruction with the given type, opcode, and
215215 /// floating-point immediate operand be emitted.
216 virtual unsigned FastEmit_f(EVT::SimpleValueType VT,
217 EVT::SimpleValueType RetVT,
216 virtual unsigned FastEmit_f(MVT VT,
217 MVT RetVT,
218218 ISD::NodeType Opcode,
219219 ConstantFP *FPImm);
220220
267267
268268 /// FastEmitInst_extractsubreg - Emit a MachineInstr for an extract_subreg
269269 /// from a specified index of a superregister to a specified type.
270 unsigned FastEmitInst_extractsubreg(EVT::SimpleValueType RetVT,
270 unsigned FastEmitInst_extractsubreg(MVT RetVT,
271271 unsigned Op0, uint32_t Idx);
272272
273273 /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
274274 /// with all but the least significant bit set to zero.
275 unsigned FastEmitZExtFromI1(EVT::SimpleValueType VT,
275 unsigned FastEmitZExtFromI1(MVT VT,
276276 unsigned Op);
277277
278278 /// FastEmitBranch - Emit an unconditional branch to the given block,
192192 /// setRoot - Set the current root tag of the SelectionDAG.
193193 ///
194194 const SDValue &setRoot(SDValue N) {
195 assert((!N.getNode() || N.getValueType() == EVT::Other) &&
195 assert((!N.getNode() || N.getValueType() == MVT::Other) &&
196196 "DAG root value is not a chain!");
197197 return Root = N;
198198 }
326326 unsigned LabelID);
327327
328328 SDValue getCopyToReg(SDValue Chain, DebugLoc dl, unsigned Reg, SDValue N) {
329 return getNode(ISD::CopyToReg, dl, EVT::Other, Chain,
329 return getNode(ISD::CopyToReg, dl, MVT::Other, Chain,
330330 getRegister(Reg, N.getValueType()), N);
331331 }
332332
335335 // null) and that there should be a flag result.
336336 SDValue getCopyToReg(SDValue Chain, DebugLoc dl, unsigned Reg, SDValue N,
337337 SDValue Flag) {
338 SDVTList VTs = getVTList(EVT::Other, EVT::Flag);
338 SDVTList VTs = getVTList(MVT::Other, MVT::Flag);
339339 SDValue Ops[] = { Chain, getRegister(Reg, N.getValueType()), N, Flag };
340340 return getNode(ISD::CopyToReg, dl, VTs, Ops, Flag.getNode() ? 4 : 3);
341341 }
343343 // Similar to last getCopyToReg() except parameter Reg is a SDValue
344344 SDValue getCopyToReg(SDValue Chain, DebugLoc dl, SDValue Reg, SDValue N,
345345 SDValue Flag) {
346 SDVTList VTs = getVTList(EVT::Other, EVT::Flag);
346 SDVTList VTs = getVTList(MVT::Other, MVT::Flag);
347347 SDValue Ops[] = { Chain, Reg, N, Flag };
348348 return getNode(ISD::CopyToReg, dl, VTs, Ops, Flag.getNode() ? 4 : 3);
349349 }
350350
351351 SDValue getCopyFromReg(SDValue Chain, DebugLoc dl, unsigned Reg, EVT VT) {
352 SDVTList VTs = getVTList(VT, EVT::Other);
352 SDVTList VTs = getVTList(VT, MVT::Other);
353353 SDValue Ops[] = { Chain, getRegister(Reg, VT) };
354354 return getNode(ISD::CopyFromReg, dl, VTs, Ops, 2);
355355 }
359359 // null) and that there should be a flag result.
360360 SDValue getCopyFromReg(SDValue Chain, DebugLoc dl, unsigned Reg, EVT VT,
361361 SDValue Flag) {
362 SDVTList VTs = getVTList(VT, EVT::Other, EVT::Flag);
362 SDVTList VTs = getVTList(VT, MVT::Other, MVT::Flag);
363363 SDValue Ops[] = { Chain, getRegister(Reg, VT), Flag };
364364 return getNode(ISD::CopyFromReg, dl, VTs, Ops, Flag.getNode() ? 3 : 2);
365365 }
390390 /// a flag result (to ensure it's not CSE'd). CALLSEQ_START does not have a
391391 /// useful DebugLoc.
392392 SDValue getCALLSEQ_START(SDValue Chain, SDValue Op) {
393 SDVTList VTs = getVTList(EVT::Other, EVT::Flag);
393 SDVTList VTs = getVTList(MVT::Other, MVT::Flag);
394394 SDValue Ops[] = { Chain, Op };
395395 return getNode(ISD::CALLSEQ_START, DebugLoc::getUnknownLoc(),
396396 VTs, Ops, 2);
401401 /// a useful DebugLoc.
402402 SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2,
403403 SDValue InFlag) {
404 SDVTList NodeTys = getVTList(EVT::Other, EVT::Flag);
404 SDVTList NodeTys = getVTList(MVT::Other, MVT::Flag);
405405 SmallVector Ops;
406406 Ops.push_back(Chain);
407407 Ops.push_back(Op1);
12441244 /// to which the flag operand points. Otherwise return NULL.
12451245 SDNode *getFlaggedNode() const {
12461246 if (getNumOperands() != 0 &&
1247 getOperand(getNumOperands()-1).getValueType() == EVT::Flag)
1247 getOperand(getNumOperands()-1).getValueType().getSimpleVT() == MVT::Flag)
12481248 return getOperand(getNumOperands()-1).getNode();
12491249 return 0;
12501250 }
12771277 return ValueList[ResNo];
12781278 }
12791279
1280 /// getValueSizeInBits - Returns EVT::getSizeInBits(getValueType(ResNo)).
1280 /// getValueSizeInBits - Returns MVT::getSizeInBits(getValueType(ResNo)).
12811281 ///
12821282 unsigned getValueSizeInBits(unsigned ResNo) const {
12831283 return getValueType(ResNo).getSizeInBits();
15041504 explicit HandleSDNode(SDValue X)
15051505 #endif
15061506 : SDNode(ISD::HANDLENODE, DebugLoc::getUnknownLoc(),
1507 getSDVTList(EVT::Other)) {
1507 getSDVTList(MVT::Other)) {
15081508 InitOperands(&Op, X);
15091509 }
15101510 ~HandleSDNode();
19131913 /// harder. Let's see if we need it first.
19141914 explicit BasicBlockSDNode(MachineBasicBlock *mbb)
19151915 : SDNode(ISD::BasicBlock, DebugLoc::getUnknownLoc(),
1916 getSDVTList(EVT::Other)), MBB(mbb) {
1916 getSDVTList(MVT::Other)), MBB(mbb) {
19171917 }
19181918 public:
19191919
19641964 /// Create a SrcValue for a general value.
19651965 explicit SrcValueSDNode(const Value *v)
19661966 : SDNode(ISD::SRCVALUE, DebugLoc::getUnknownLoc(),
1967 getSDVTList(EVT::Other)), V(v) {}
1967 getSDVTList(MVT::Other)), V(v) {}
19681968
19691969 public:
19701970 /// getValue - return the contained Value.
19861986 /// Create a MachineMemOperand node
19871987 explicit MemOperandSDNode(const MachineMemOperand &mo)
19881988 : SDNode(ISD::MEMOPERAND, DebugLoc::getUnknownLoc(),
1989 getSDVTList(EVT::Other)), MO(mo) {}
1989 getSDVTList(MVT::Other)), MO(mo) {}
19901990
19911991 public:
19921992 /// MO - The contained MachineMemOperand.
20252025 DbgStopPointSDNode(SDValue ch, unsigned l, unsigned c,
20262026 Value *cu)
20272027 : SDNode(ISD::DBG_STOPPOINT, DebugLoc::getUnknownLoc(),
2028 getSDVTList(EVT::Other)), Line(l), Column(c), CU(cu) {
2028 getSDVTList(MVT::Other)), Line(l), Column(c), CU(cu) {
20292029 InitOperands(&Chain, ch);
20302030 }
20312031 public:
20442044 unsigned LabelID;
20452045 friend class SelectionDAG;
20462046 LabelSDNode(unsigned NodeTy, DebugLoc dl, SDValue ch, unsigned id)
2047 : SDNode(NodeTy, dl, getSDVTList(EVT::Other)), LabelID(id) {
2047 : SDNode(NodeTy, dl, getSDVTList(MVT::Other)), LabelID(id) {
20482048 InitOperands(&Chain, ch);
20492049 }
20502050 public:
20842084 friend class SelectionDAG;
20852085 explicit CondCodeSDNode(ISD::CondCode Cond)
20862086 : SDNode(ISD::CONDCODE, DebugLoc::getUnknownLoc(),
2087 getSDVTList(EVT::Other)), Condition(Cond) {
2087 getSDVTList(MVT::Other)), Condition(Cond) {
20882088 }
20892089 public:
20902090
22092209 EVT VT;
22102210 bool Used;
22112211
2212 InputArg() : VT(EVT::Other), Used(false) {}
2212 InputArg() : VT(MVT::Other), Used(false) {}
22132213 InputArg(ISD::ArgFlagsTy flags, EVT vt, bool used)
22142214 : Flags(flags), VT(vt), Used(used) {
22152215 assert(VT.isSimple() &&
22422242 friend class SelectionDAG;
22432243 explicit VTSDNode(EVT VT)
22442244 : SDNode(ISD::VALUETYPE, DebugLoc::getUnknownLoc(),
2245 getSDVTList(EVT::Other)), ValueType(VT) {
2245 getSDVTList(MVT::Other)), ValueType(VT) {
22462246 }
22472247 public:
22482248
2323 namespace llvm {
2424 class Type;
2525 class LLVMContext;
26
27 struct EVT { // EVT = Machine Value Type
28 public:
26 struct EVT;
27
28 struct MVT { // MVT = Machine Value Type
2929 enum SimpleValueType {
3030 // If you change this numbering, you must change the values in
3131 // ValueTypes.td as well!
112112 LastSimpleValueType = 255
113113 };
114114
115 private:
116 /// This union holds low-level value types. Valid values include any of
117 /// the values in the SimpleValueType enum, or any value returned from one
118 /// of the EVT methods. Any value type equal to one of the SimpleValueType
119 /// enum values is a "simple" value type. All others are "extended".
120 ///
121 /// Note that simple doesn't necessary mean legal for the target machine.
122 /// All legal value types must be simple, but often there are some simple
123 /// value types that are not legal.
124 ///
125 union {
126 uintptr_t V;
127 const Type *LLVMTy;
128 };
129
130 public:
131 EVT() {}
132 EVT(SimpleValueType S) : V(S) {}
133
134 bool operator==(const EVT VT) const {
135 return getRawBits() == VT.getRawBits();
136 }
137 bool operator!=(const EVT VT) const {
138 return getRawBits() != VT.getRawBits();
139 }
140
141 /// getFloatingPointVT - Returns the EVT that represents a floating point
142 /// type with the given number of bits. There are two floating point types
143 /// with 128 bits - this returns f128 rather than ppcf128.
144 static EVT getFloatingPointVT(unsigned BitWidth) {
145 switch (BitWidth) {
146 default:
147 assert(false && "Bad bit width!");
148 case 32:
149 return f32;
150 case 64:
151 return f64;
152 case 80:
153 return f80;
154 case 128:
155 return f128;
156 }
157 }
158
159 /// getIntegerVT - Returns the EVT that represents an integer with the given
160 /// number of bits.
161 static EVT getIntegerVT(unsigned BitWidth) {
162 switch (BitWidth) {
163 default:
164 break;
165 case 1:
166 return i1;
167 case 8:
168 return i8;
169 case 16:
170 return i16;
171 case 32:
172 return i32;
173 case 64:
174 return i64;
175 case 128:
176 return i128;
177 }
178 return getExtendedIntegerVT(BitWidth);
179 }
180
181 /// getVectorVT - Returns the EVT that represents a vector NumElements in
182 /// length, where each element is of type VT.
183 static EVT getVectorVT(EVT VT, unsigned NumElements) {
184 switch (VT.V) {
185 default:
186 break;
187 case i8:
188 if (NumElements == 2) return v2i8;
189 if (NumElements == 4) return v4i8;
190 if (NumElements == 8) return v8i8;
191 if (NumElements == 16) return v16i8;
192 if (NumElements == 32) return v32i8;
193 break;
194 case i16:
195 if (NumElements == 2) return v2i16;
196 if (NumElements == 4) return v4i16;
197 if (NumElements == 8) return v8i16;
198 if (NumElements == 16) return v16i16;
199 break;
200 case i32:
201 if (NumElements == 2) return v2i32;
202 if (NumElements == 4) return v4i32;
203 if (NumElements == 8) return v8i32;
204 break;
205 case i64:
206 if (NumElements == 1) return v1i64;
207 if (NumElements == 2) return v2i64;
208 if (NumElements == 4) return v4i64;
209 break;
210 case f32:
211 if (NumElements == 2) return v2f32;
212 if (NumElements == 4) return v4f32;
213 if (NumElements == 8) return v8f32;
214 break;
215 case f64:
216 if (NumElements == 2) return v2f64;
217 if (NumElements == 4) return v4f64;
218 break;
219 }
220 return getExtendedVectorVT(VT, NumElements);
221 }
222
223 /// getIntVectorWithNumElements - Return any integer vector type that has
224 /// the specified number of elements.
225 static EVT getIntVectorWithNumElements(unsigned NumElts) {
226 switch (NumElts) {
227 default: return getVectorVT(i8, NumElts);
228 case 1: return v1i64;
229 case 2: return v2i32;
230 case 4: return v4i16;
231 case 8: return v8i8;
232 case 16: return v16i8;
233 }
234 }
235
236 /// isSimple - Test if the given EVT is simple (as opposed to being
237 /// extended).
238 bool isSimple() const {
239 return V <= LastSimpleValueType;
240 }
241
242 /// isExtended - Test if the given EVT is extended (as opposed to
243 /// being simple).
244 bool isExtended() const {
245 return !isSimple();
246 }
247
115 SimpleValueType SimpleTy;
116
117 MVT() : SimpleTy((SimpleValueType)(LastSimpleValueType+1)) {}
118 MVT(SimpleValueType SVT) : SimpleTy(SVT) { }
119
120 bool operator>(const MVT& S) const { return SimpleTy > S.SimpleTy; }
121 bool operator<(const MVT& S) const { return SimpleTy < S.SimpleTy; }
122 bool operator==(const MVT& S) const { return SimpleTy == S.SimpleTy; }
123 bool operator>=(const MVT& S) const { return SimpleTy >= S.SimpleTy; }
124 bool operator<=(const MVT& S) const { return SimpleTy <= S.SimpleTy; }
125
248126 /// isFloatingPoint - Return true if this is a FP, or a vector FP type.
249127 bool isFloatingPoint() const {
250 return isSimple() ?
251 ((V >= f32 && V <= ppcf128) ||
252 (V >= v2f32 && V <= v4f64)) : isExtendedFloatingPoint();
128 return ((SimpleTy >= MVT::f32 && SimpleTy <= MVT::ppcf128) ||
129 (SimpleTy >= MVT::v2f32 && SimpleTy <= MVT::v4f64));
253130 }
254131
255132 /// isInteger - Return true if this is an integer, or a vector integer type.
256133 bool isInteger() const {
257 return isSimple() ?
258 ((V >= FIRST_INTEGER_VALUETYPE && V <= LAST_INTEGER_VALUETYPE) ||
259 (V >= v2i8 && V <= v4i64)) : isExtendedInteger();
134 return ((SimpleTy >= MVT::FIRST_INTEGER_VALUETYPE &&
135 SimpleTy <= MVT::LAST_INTEGER_VALUETYPE) ||
136 (SimpleTy >= MVT::v2i8 && SimpleTy <= MVT::v4i64));
260137 }
261138
262139 /// isVector - Return true if this is a vector value type.
263140 bool isVector() const {
264 return isSimple() ?
265 (V >= FIRST_VECTOR_VALUETYPE && V <= LAST_VECTOR_VALUETYPE) :
266 isExtendedVector();
267 }
268
269 /// is64BitVector - Return true if this is a 64-bit vector type.
270 bool is64BitVector() const {
271 return isSimple() ?
272 (V==v8i8 || V==v4i16 || V==v2i32 || V==v1i64 || V==v2f32) :
273 isExtended64BitVector();
274 }
275
276 /// is128BitVector - Return true if this is a 128-bit vector type.
277 bool is128BitVector() const {
278 return isSimple() ?
279 (V==v16i8 || V==v8i16 || V==v4i32 ||
280 V==v2i64 || V==v4f32 || V==v2f64) :
281 isExtended128BitVector();
282 }
283
284 /// is256BitVector - Return true if this is a 256-bit vector type.
285 inline bool is256BitVector() const {
286 return isSimple() ?
287 (V==v8f32 || V==v4f64 || V==v32i8 || V==v16i16 || V==v8i32 ||
288 V==v4i64) : isExtended256BitVector();
289 }
290
291 /// isOverloaded - Return true if this is an overloaded type for TableGen.
292 bool isOverloaded() const {
293 return (V==iAny || V==fAny || V==vAny || V==iPTRAny);
294 }
295
296 /// isByteSized - Return true if the bit size is a multiple of 8.
297 bool isByteSized() const {
298 return (getSizeInBits() & 7) == 0;
299 }
300
301 /// isRound - Return true if the size is a power-of-two number of bytes.
302 bool isRound() const {
303 unsigned BitSize = getSizeInBits();
304 return BitSize >= 8 && !(BitSize & (BitSize - 1));
305 }
306
307 /// bitsEq - Return true if this has the same number of bits as VT.
308 bool bitsEq(EVT VT) const {
309 return getSizeInBits() == VT.getSizeInBits();
310 }
311
312 /// bitsGT - Return true if this has more bits than VT.
313 bool bitsGT(EVT VT) const {
314 return getSizeInBits() > VT.getSizeInBits();
315 }
316
317 /// bitsGE - Return true if this has no less bits than VT.
318 bool bitsGE(EVT VT) const {
319 return getSizeInBits() >= VT.getSizeInBits();
320 }
321
322 /// bitsLT - Return true if this has less bits than VT.
323 bool bitsLT(EVT VT) const {
324 return getSizeInBits() < VT.getSizeInBits();
325 }
326
327 /// bitsLE - Return true if this has no more bits than VT.
328 bool bitsLE(EVT VT) const {
329 return getSizeInBits() <= VT.getSizeInBits();
330 }
331
332
333 /// getSimpleVT - Return the SimpleValueType held in the specified
334 /// simple EVT.
335 SimpleValueType getSimpleVT() const {
336 assert(isSimple() && "Expected a SimpleValueType!");
337 return SimpleValueType(V);
338 }
339
340 /// getVectorElementType - Given a vector type, return the type of
341 /// each element.
342 EVT getVectorElementType() const {
343 assert(isVector() && "Invalid vector type!");
344 switch (V) {
141 return (SimpleTy >= MVT::FIRST_VECTOR_VALUETYPE &&
142 SimpleTy <= MVT::LAST_VECTOR_VALUETYPE);
143 }
144
145 MVT getVectorElementType() const {
146 switch (SimpleTy) {
345147 default:
346 return getExtendedVectorElementType();
148 return (MVT::SimpleValueType)(MVT::LastSimpleValueType+1);
347149 case v2i8 :
348150 case v4i8 :
349151 case v8i8 :
366168 case v4f64: return f64;
367169 }
368170 }
369
370 /// getVectorNumElements - Given a vector type, return the number of
371 /// elements it contains.
171
372172 unsigned getVectorNumElements() const {
373 assert(isVector() && "Invalid vector type!");
374 switch (V) {
173 switch (SimpleTy) {
375174 default:
376 return getExtendedVectorNumElements();
175 return ~0U;
377176 case v32i8: return 32;
378177 case v16i8:
379178 case v16i16: return 16;
396195 case v1i64: return 1;
397196 }
398197 }
399
400 /// getSizeInBits - Return the size of the specified value type in bits.
198
401199 unsigned getSizeInBits() const {
402 switch (V) {
200 switch (SimpleTy) {
403201 case iPTR:
404202 assert(0 && "Value type size is target-dependent. Ask TLI.");
405203 case iPTRAny:
406204 case iAny:
407205 case fAny:
408 case vAny:
409206 assert(0 && "Value type is overloaded.");
410207 default:
411 return getExtendedSizeInBits();
208 assert(0 && "getSizeInBits called on extended MVT.");
412209 case i1 : return 1;
413210 case i8 : return 8;
414211 case i16 :
442239 case v4f64: return 256;
443240 }
444241 }
242
243 static MVT getFloatingPointVT(unsigned BitWidth) {
244 switch (BitWidth) {
245 default:
246 assert(false && "Bad bit width!");
247 case 32:
248 return MVT::f32;
249 case 64:
250 return MVT::f64;
251 case 80:
252 return MVT::f80;
253 case 128:
254 return MVT::f128;
255 }
256 }
257
258 static MVT getIntegerVT(unsigned BitWidth) {
259 switch (BitWidth) {
260 default:
261 return (MVT::SimpleValueType)(MVT::LastSimpleValueType+1);
262 case 1:
263 return MVT::i1;
264 case 8:
265 return MVT::i8;
266 case 16:
267 return MVT::i16;
268 case 32:
269 return MVT::i32;
270 case 64:
271 return MVT::i64;
272 case 128:
273 return MVT::i128;
274 }
275 }
276
277 static MVT getVectorVT(MVT VT, unsigned NumElements) {
278 switch (VT.SimpleTy) {
279 default:
280 break;
281 case MVT::i8:
282 if (NumElements == 2) return MVT::v2i8;
283 if (NumElements == 4) return MVT::v4i8;
284 if (NumElements == 8) return MVT::v8i8;
285 if (NumElements == 16) return MVT::v16i8;
286 if (NumElements == 32) return MVT::v32i8;
287 break;
288 case MVT::i16:
289 if (NumElements == 2) return MVT::v2i16;
290 if (NumElements == 4) return MVT::v4i16;
291 if (NumElements == 8) return MVT::v8i16;
292 if (NumElements == 16) return MVT::v16i16;
293 break;
294 case MVT::i32:
295 if (NumElements == 2) return MVT::v2i32;
296 if (NumElements == 4) return MVT::v4i32;
297 if (NumElements == 8) return MVT::v8i32;
298 break;
299 case MVT::i64:
300 if (NumElements == 1) return MVT::v1i64;
301 if (NumElements == 2) return MVT::v2i64;
302 if (NumElements == 4) return MVT::v4i64;
303 break;
304 case MVT::f32:
305 if (NumElements == 2) return MVT::v2f32;
306 if (NumElements == 4) return MVT::v4f32;
307 if (NumElements == 8) return MVT::v8f32;
308 break;
309 case MVT::f64:
310 if (NumElements == 2) return MVT::v2f64;
311 if (NumElements == 4) return MVT::v4f64;
312 break;
313 }
314 return (MVT::SimpleValueType)(MVT::LastSimpleValueType+1);
315 }
316
317 static MVT getIntVectorWithNumElements(unsigned NumElts) {
318 switch (NumElts) {
319 default: return (MVT::SimpleValueType)(MVT::LastSimpleValueType+1);
320 case 1: return MVT::v1i64;
321 case 2: return MVT::v2i32;
322 case 4: return MVT::v4i16;
323 case 8: return MVT::v8i8;
324 case 16: return MVT::v16i8;
325 }
326 }
327 };
328
329 struct EVT { // EVT = Extended Value Type
330 private:
331 MVT V;
332 const Type *LLVMTy;
333
334 public:
335 EVT() : V((MVT::SimpleValueType)(MVT::LastSimpleValueType+1)) {}
336 EVT(MVT::SimpleValueType SVT) : V(SVT) { }
337 EVT(MVT S) : V(S) {}
338
339 bool operator==(const EVT VT) const {
340 if (V.SimpleTy == VT.V.SimpleTy) {
341 if (V.SimpleTy == MVT::LastSimpleValueType+1)
342 return LLVMTy == VT.LLVMTy;
343 return true;
344 }
345 return false;
346 }
347 bool operator!=(const EVT VT) const {
348 if (V.SimpleTy == VT.V.SimpleTy) {
349 if (V.SimpleTy == MVT::LastSimpleValueType+1)
350 return LLVMTy != VT.LLVMTy;
351 return false;
352 }
353 return true;
354 }
355
356 /// getFloatingPointVT - Returns the EVT that represents a floating point
357 /// type with the given number of bits. There are two floating point types
358 /// with 128 bits - this returns f128 rather than ppcf128.
359 static EVT getFloatingPointVT(unsigned BitWidth) {
360 return MVT::getFloatingPointVT(BitWidth);
361 }
362
363 /// getIntegerVT - Returns the EVT that represents an integer with the given
364 /// number of bits.
365 static EVT getIntegerVT(unsigned BitWidth) {
366 MVT M = MVT::getIntegerVT(BitWidth);
367 if (M.SimpleTy == MVT::LastSimpleValueType+1)
368 return getExtendedIntegerVT(BitWidth);
369 else
370 return M;
371 }
372
373 /// getVectorVT - Returns the EVT that represents a vector NumElements in
374 /// length, where each element is of type VT.
375 static EVT getVectorVT(EVT VT, unsigned NumElements) {
376 MVT M = MVT::getVectorVT(VT.V, NumElements);
377 if (M.SimpleTy == MVT::LastSimpleValueType+1)
378 return getExtendedVectorVT(VT, NumElements);
379 else
380 return M;
381 }
382
383 /// getIntVectorWithNumElements - Return any integer vector type that has
384 /// the specified number of elements.
385 static EVT getIntVectorWithNumElements(unsigned NumElts) {
386 MVT M = MVT::getIntVectorWithNumElements(NumElts);
387 if (M.SimpleTy == MVT::LastSimpleValueType+1)
388 return getVectorVT(EVT(MVT::i8), NumElts);
389 else
390 return M;
391 }
392
393 /// isSimple - Test if the given EVT is simple (as opposed to being
394 /// extended).
395 bool isSimple() const {
396 return V.SimpleTy <= MVT::LastSimpleValueType;
397 }
398
399 /// isExtended - Test if the given EVT is extended (as opposed to
400 /// being simple).
401 bool isExtended() const {
402 return !isSimple();
403 }
404
405 /// isFloatingPoint - Return true if this is a FP, or a vector FP type.
406 bool isFloatingPoint() const {
407 return isSimple() ?
408 ((V >= MVT::f32 && V <= MVT::ppcf128) ||
409 (V >= MVT::v2f32 && V <= MVT::v4f64)) : isExtendedFloatingPoint();
410 }
411
412 /// isInteger - Return true if this is an integer, or a vector integer type.
413 bool isInteger() const {
414 return isSimple() ?
415 ((V >= MVT::FIRST_INTEGER_VALUETYPE &&
416 V <= MVT::LAST_INTEGER_VALUETYPE) ||
417 (V >= MVT::v2i8 && V <= MVT::v4i64)) : isExtendedInteger();
418 }
419
420 /// isVector - Return true if this is a vector value type.
421 bool isVector() const {
422 return isSimple() ?
423 (V >= MVT::FIRST_VECTOR_VALUETYPE && V <=
424 MVT::LAST_VECTOR_VALUETYPE) :
425 isExtendedVector();
426 }
427
428 /// is64BitVector - Return true if this is a 64-bit vector type.
429 bool is64BitVector() const {
430 return isSimple() ?
431 (V==MVT::v8i8 || V==MVT::v4i16 || V==MVT::v2i32 ||
432 V==MVT::v1i64 || V==MVT::v2f32) :
433 isExtended64BitVector();
434 }
435
436 /// is128BitVector - Return true if this is a 128-bit vector type.
437 bool is128BitVector() const {
438 return isSimple() ?
439 (V==MVT::v16i8 || V==MVT::v8i16 || V==MVT::v4i32 ||
440 V==MVT::v2i64 || V==MVT::v4f32 || V==MVT::v2f64) :
441 isExtended128BitVector();
442 }
443
444 /// is256BitVector - Return true if this is a 256-bit vector type.
445 inline bool is256BitVector() const {
446 return isSimple() ?
447 (V==MVT::v8f32 || V==MVT::v4f64 || V==MVT::v32i8 ||
448 V==MVT::v16i16 || V==MVT::v8i32 || V==MVT::v4i64) :
449 isExtended256BitVector();
450 }
451
452 /// isOverloaded - Return true if this is an overloaded type for TableGen.
453 bool isOverloaded() const {
454 return (V==MVT::iAny || V==MVT::fAny || V==MVT::vAny || V==MVT::iPTRAny);
455 }
456
457 /// isByteSized - Return true if the bit size is a multiple of 8.
458 bool isByteSized() const {
459 return (getSizeInBits() & 7) == 0;
460 }
461
462 /// isRound - Return true if the size is a power-of-two number of bytes.
463 bool isRound() const {
464 unsigned BitSize = getSizeInBits();
465 return BitSize >= 8 && !(BitSize & (BitSize - 1));
466 }
467
468 /// bitsEq - Return true if this has the same number of bits as VT.
469 bool bitsEq(EVT VT) const {
470 return getSizeInBits() == VT.getSizeInBits();
471 }
472
473 /// bitsGT - Return true if this has more bits than VT.
474 bool bitsGT(EVT VT) const {
475 return getSizeInBits() > VT.getSizeInBits();
476 }
477
478 /// bitsGE - Return true if this has no less bits than VT.
479 bool bitsGE(EVT VT) const {
480 return getSizeInBits() >= VT.getSizeInBits();
481 }
482
483 /// bitsLT - Return true if this has less bits than VT.
484 bool bitsLT(EVT VT) const {
485 return getSizeInBits() < VT.getSizeInBits();
486 }
487
488 /// bitsLE - Return true if this has no more bits than VT.
489 bool bitsLE(EVT VT) const {
490 return getSizeInBits() <= VT.getSizeInBits();
491 }
492
493
494 /// getSimpleVT - Return the SimpleValueType held in the specified
495 /// simple EVT.
496 MVT getSimpleVT() const {
497 assert(isSimple() && "Expected a SimpleValueType!");
498 return V;
499 }
500
501 /// getVectorElementType - Given a vector type, return the type of
502 /// each element.
503 EVT getVectorElementType() const {
504 assert(isVector() && "Invalid vector type!");
505 if (isSimple())
506 return V.getVectorElementType();
507 else
508 return getExtendedVectorElementType();
509 }
510
511 /// getVectorNumElements - Given a vector type, return the number of
512 /// elements it contains.
513 unsigned getVectorNumElements() const {
514 assert(isVector() && "Invalid vector type!");
515 if (isSimple())
516 return V.getVectorNumElements();
517 else
518 return getExtendedVectorNumElements();
519 }
520
521 /// getSizeInBits - Return the size of the specified value type in bits.
522 unsigned getSizeInBits() const {
523 if (isSimple())
524 return V.getSizeInBits();
525 else
526 return getExtendedSizeInBits();
527 }
445528
446529 /// getStoreSizeInBits - Return the number of bits overwritten by a store
447530 /// of the specified value type.
456539 assert(isInteger() && !isVector() && "Invalid integer type!");
457540 unsigned BitWidth = getSizeInBits();
458541 if (BitWidth <= 8)
459 return i8;
542 return EVT(MVT::i8);
460543 else
461544 return getIntegerVT(1 << Log2_32_Ceil(BitWidth));
462545 }
494577 /// types are returned as Other, otherwise they are invalid.
495578 static EVT getEVT(const Type *Ty, bool HandleUnknown = false);
496579
497 /// getRawBits - Represent the type as a bunch of bits.
498 uintptr_t getRawBits() const { return V; }
580 intptr_t getRawBits() {
581 if (V.SimpleTy <= MVT::LastSimpleValueType)
582 return V.SimpleTy;
583 else
584 return (intptr_t)(LLVMTy);
585 }
499586
500587 /// compareRawBits - A meaningless but well-behaved order, useful for
501588 /// constructing containers.
502589 struct compareRawBits {
503590 bool operator()(EVT L, EVT R) const {
504 return L.getRawBits() < R.getRawBits();
591 if (L.V.SimpleTy == R.V.SimpleTy)
592 return L.LLVMTy < R.LLVMTy;
593 else
594 return L.V.SimpleTy < R.V.SimpleTy;
505595 }
506596 };
507597
110110
111111 bool isBigEndian() const { return !IsLittleEndian; }
112112 bool isLittleEndian() const { return IsLittleEndian; }
113 EVT::SimpleValueType getPointerTy() const { return PointerTy; }
114 EVT::SimpleValueType getShiftAmountTy() const { return ShiftAmountTy; }
113 MVT getPointerTy() const { return PointerTy; }
114 MVT getShiftAmountTy() const { return ShiftAmountTy; }
115115
116116 /// usesGlobalOffsetTable - Return true if this target uses a GOT for PIC
117117 /// codegen.
132132 /// getSetCCResultType - Return the ValueType of the result of SETCC
133133 /// operations. Also used to obtain the target's preferred type for
134134 /// the condition operand of SELECT and BRCOND nodes. In the case of
135 /// BRCOND the argument passed is EVT::Other since there are no other
135 /// BRCOND the argument passed is MVT::Other since there are no other
136136 /// operands to get a type hint from.
137137 virtual
138 EVT::SimpleValueType getSetCCResultType(EVT VT) const;
138 MVT::SimpleValueType getSetCCResultType(EVT VT) const;
139139
140140 /// getBooleanContents - For targets without i1 registers, this gives the
141141 /// nature of the high-bits of boolean values held in types wider than i1.
153153 /// specified value type. This may only be called on legal types.
154154 TargetRegisterClass *getRegClassFor(EVT VT) const {
155155 assert(VT.isSimple() && "getRegClassFor called on illegal type!");
156 TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT()];
156 TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy];
157157 assert(RC && "This value type is not natively supported!");
158158 return RC;
159159 }
163163 /// holds it without promotions or expansions.
164164 bool isTypeLegal(EVT VT) const {
165165 assert(!VT.isSimple() ||
166 (unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT));
167 return VT.isSimple() && RegClassForVT[VT.getSimpleVT()] != 0;
166 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
167 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != 0;
168168 }
169169
170170 class ValueTypeActionImpl {
171171 /// ValueTypeActions - This is a bitvector that contains two bits for each
172172 /// value type, where the two bits correspond to the LegalizeAction enum.
173173 /// This can be queried with "getTypeAction(VT)".
174 /// dimension by (EVT::MAX_ALLOWED_VALUETYPE/32) * 2
175 uint32_t ValueTypeActions[(EVT::MAX_ALLOWED_VALUETYPE/32)*2];
174 /// dimension by (MVT::MAX_ALLOWED_VALUETYPE/32) * 2
175 uint32_t ValueTypeActions[(MVT::MAX_ALLOWED_VALUETYPE/32)*2];
176176 public:
177177 ValueTypeActionImpl() {
178178 ValueTypeActions[0] = ValueTypeActions[1] = 0;
196196 assert(0 && "Unsupported extended type!");
197197 return Legal;
198198 }
199 unsigned I = VT.getSimpleVT();
199 unsigned I = VT.getSimpleVT().SimpleTy;
200200 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0]));
201201 return (LegalizeAction)((ValueTypeActions[I>>4] >> ((2*I) & 31)) & 3);
202202 }
203203 void setTypeAction(EVT VT, LegalizeAction Action) {
204 unsigned I = VT.getSimpleVT();
204 unsigned I = VT.getSimpleVT().SimpleTy;
205205 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0]));
206206 ValueTypeActions[I>>4] |= Action << ((I*2) & 31);
207207 }
227227 /// returns the integer type to transform to.
228228 EVT getTypeToTransformTo(EVT VT) const {
229229 if (VT.isSimple()) {
230 assert((unsigned)VT.getSimpleVT() < array_lengthof(TransformToType));
231 EVT NVT = TransformToType[VT.getSimpleVT()];
230 assert((unsigned)VT.getSimpleVT().SimpleTy <
231 array_lengthof(TransformToType));
232 EVT NVT = TransformToType[VT.getSimpleVT().SimpleTy];
232233 assert(getTypeAction(NVT) != Promote &&
233234 "Promote may not follow Expand or Promote");
234235 return NVT;
254255 return getTypeAction(NVT) == Promote ? getTypeToTransformTo(NVT) : NVT;
255256 }
256257 assert(0 && "Unsupported extended type!");
257 return EVT(EVT::Other); // Not reached
258 return MVT(MVT::Other); // Not reached
258259 }
259260
260261 /// getTypeToExpandTo - For types supported by the target, this is an
314315
315316 /// getWidenVectorType: given a vector type, returns the type to widen to
316317 /// (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
317 /// If there is no vector type that we want to widen to, returns EVT::Other
318 /// If there is no vector type that we want to widen to, returns MVT::Other
318319 /// When and were to widen is target dependent based on the cost of
319320 /// scalarizing vs using the wider vector type.
320321 virtual EVT getWidenVectorType(EVT VT) const;
352353 LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
353354 if (VT.isExtended()) return Expand;
354355 assert(Op < array_lengthof(OpActions[0]) &&
355 (unsigned)VT.getSimpleVT() < sizeof(OpActions[0][0])*8 &&
356 (unsigned)VT.getSimpleVT().SimpleTy < sizeof(OpActions[0][0])*8 &&
356357 "Table isn't big enough!");
357 unsigned I = (unsigned) VT.getSimpleVT();
358 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy;
358359 unsigned J = I & 31;
359360 I = I >> 5;
360361 return (LegalizeAction)((OpActions[I][Op] >> (J*2) ) & 3);
364365 /// legal on this target or can be made legal with custom lowering. This
365366 /// is used to help guide high-level lowering decisions.
366367 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
367 return (VT == EVT::Other || isTypeLegal(VT)) &&
368 return (VT == MVT::Other || isTypeLegal(VT)) &&
368369 (getOperationAction(Op, VT) == Legal ||
369370 getOperationAction(Op, VT) == Custom);
370371 }
372373 /// isOperationLegal - Return true if the specified operation is legal on this
373374 /// target.
374375 bool isOperationLegal(unsigned Op, EVT VT) const {
375 return (VT == EVT::Other || isTypeLegal(VT)) &&
376 return (VT == MVT::Other || isTypeLegal(VT)) &&
376377 getOperationAction(Op, VT) == Legal;
377378 }
378379
382383 /// for it.
383384 LegalizeAction getLoadExtAction(unsigned LType, EVT VT) const {
384385 assert(LType < array_lengthof(LoadExtActions) &&
385 (unsigned)VT.getSimpleVT() < sizeof(LoadExtActions[0])*4 &&
386 (unsigned)VT.getSimpleVT().SimpleTy < sizeof(LoadExtActions[0])*4 &&
386387 "Table isn't big enough!");
387 return (LegalizeAction)((LoadExtActions[LType] >> (2*VT.getSimpleVT())) & 3);
388 return (LegalizeAction)((LoadExtActions[LType] >>
389 (2*VT.getSimpleVT().SimpleTy)) & 3);
388390 }
389391
390392 /// isLoadExtLegal - Return true if the specified load with extension is legal
401403 /// expander for it.
402404 LegalizeAction getTruncStoreAction(EVT ValVT,
403405 EVT MemVT) const {
404 assert((unsigned)ValVT.getSimpleVT() < array_lengthof(TruncStoreActions) &&
405 (unsigned)MemVT.getSimpleVT() < sizeof(TruncStoreActions[0])*4 &&
406 assert((unsigned)ValVT.getSimpleVT().SimpleTy <
407 array_lengthof(TruncStoreActions) &&
408 (unsigned)MemVT.getSimpleVT().SimpleTy <
409 sizeof(TruncStoreActions[0])*4 &&
406410 "Table isn't big enough!");
407 return (LegalizeAction)((TruncStoreActions[ValVT.getSimpleVT()] >>
408 (2*MemVT.getSimpleVT())) & 3);
411 return (LegalizeAction)((TruncStoreActions[ValVT.getSimpleVT().SimpleTy] >>
412 (2*MemVT.getSimpleVT().SimpleTy)) & 3);
409413 }
410414
411415 /// isTruncStoreLegal - Return true if the specified store with truncation is
423427 LegalizeAction
424428 getIndexedLoadAction(unsigned IdxMode, EVT VT) const {
425429 assert( IdxMode < array_lengthof(IndexedModeActions[0][0]) &&
426 ((unsigned)VT.getSimpleVT()) < EVT::LAST_VALUETYPE &&
430 ((unsigned)VT.getSimpleVT().SimpleTy) < MVT::LAST_VALUETYPE &&
427431 "Table isn't big enough!");
428 return (LegalizeAction)((IndexedModeActions[(unsigned)VT.getSimpleVT()][0][IdxMode]));
432 return (LegalizeAction)((IndexedModeActions[
433 (unsigned)VT.getSimpleVT().SimpleTy][0][IdxMode]));
429434 }
430435
431436 /// isIndexedLoadLegal - Return true if the specified indexed load is legal
443448 LegalizeAction
444449 getIndexedStoreAction(unsigned IdxMode, EVT VT) const {
445450 assert(IdxMode < array_lengthof(IndexedModeActions[0][1]) &&
446 (unsigned)VT.getSimpleVT() < EVT::LAST_VALUETYPE &&
451 (unsigned)VT.getSimpleVT().SimpleTy < MVT::LAST_VALUETYPE &&
447452 "Table isn't big enough!");
448 return (LegalizeAction)((IndexedModeActions[(unsigned)VT.getSimpleVT()][1][IdxMode]));
453 return (LegalizeAction)((IndexedModeActions[
454 (unsigned)VT.getSimpleVT().SimpleTy][1][IdxMode]));
449455 }
450456
451457 /// isIndexedStoreLegal - Return true if the specified indexed load is legal
462468 /// for it.
463469 LegalizeAction
464470 getConvertAction(EVT FromVT, EVT ToVT) const {
465 assert((unsigned)FromVT.getSimpleVT() < array_lengthof(ConvertActions) &&
466 (unsigned)ToVT.getSimpleVT() < sizeof(ConvertActions[0])*4 &&
471 assert((unsigned)FromVT.getSimpleVT().SimpleTy <
472 array_lengthof(ConvertActions) &&
473 (unsigned)ToVT.getSimpleVT().SimpleTy <
474 sizeof(ConvertActions[0])*4 &&
467475 "Table isn't big enough!");
468 return (LegalizeAction)((ConvertActions[FromVT.getSimpleVT()] >>
469 (2*ToVT.getSimpleVT())) & 3);
476 return (LegalizeAction)((ConvertActions[FromVT.getSimpleVT().SimpleTy] >>
477 (2*ToVT.getSimpleVT().SimpleTy)) & 3);
470478 }
471479
472480 /// isConvertLegal - Return true if the specified conversion is legal
483491 LegalizeAction
484492 getCondCodeAction(ISD::CondCode CC, EVT VT) const {
485493 assert((unsigned)CC < array_lengthof(CondCodeActions) &&
486 (unsigned)VT.getSimpleVT() < sizeof(CondCodeActions[0])*4 &&
494 (unsigned)VT.getSimpleVT().SimpleTy < sizeof(CondCodeActions[0])*4 &&
487495 "Table isn't big enough!");
488496 LegalizeAction Action = (LegalizeAction)
489 ((CondCodeActions[CC] >> (2*VT.getSimpleVT())) & 3);
497 ((CondCodeActions[CC] >> (2*VT.getSimpleVT().SimpleTy)) & 3);
490498 assert(Action != Promote && "Can't promote condition code!");
491499 return Action;
492500 }
506514 "This operation isn't promoted!");
507515
508516 // See if this has an explicit type specified.
509 std::map,
510 EVT::SimpleValueType>::const_iterator PTTI =
511 PromoteToType.find(std::make_pair(Op, VT.getSimpleVT()));
517 std::map,
518 MVT::SimpleValueType>::const_iterator PTTI =
519 PromoteToType.find(std::make_pair(Op, VT.getSimpleVT().SimpleTy));
512520 if (PTTI != PromoteToType.end()) return PTTI->second;
513521
514522 assert((VT.isInteger() || VT.isFloatingPoint()) &&
516524
517525 EVT NVT = VT;
518526 do {
519 NVT = (EVT::SimpleValueType)(NVT.getSimpleVT()+1);
520 assert(NVT.isInteger() == VT.isInteger() && NVT != EVT::isVoid &&
527 NVT = (MVT::SimpleValueType)(NVT.getSimpleVT().SimpleTy+1);
528 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
521529 "Didn't find type to promote to!");
522530 } while (!isTypeLegal(NVT) ||
523531 getOperationAction(Op, NVT) == Promote);
526534
527535 /// getValueType - Return the EVT corresponding to this LLVM type.
528536 /// This is fixed by the LLVM operations except for the pointer size. If
529 /// AllowUnknown is true, this will return EVT::Other for types with no EVT
537 /// AllowUnknown is true, this will return MVT::Other for types with no EVT
530538 /// counterpart (e.g. structs), otherwise it will assert.
531539 EVT getValueType(const Type *Ty, bool AllowUnknown = false) const {
532540 EVT VT = EVT::getEVT(Ty, AllowUnknown);
533 return VT == EVT::iPTR ? PointerTy : VT;
541 return VT == MVT:: iPTR ? PointerTy : VT;
534542 }
535543
536544 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
542550 /// eventually require.
543551 EVT getRegisterType(EVT VT) const {
544552 if (VT.isSimple()) {
545 assert((unsigned)VT.getSimpleVT() < array_lengthof(RegisterTypeForVT));
546 return RegisterTypeForVT[VT.getSimpleVT()];
553 assert((unsigned)VT.getSimpleVT().SimpleTy <
554 array_lengthof(RegisterTypeForVT));
555 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
547556 }
548557 if (VT.isVector()) {
549558 EVT VT1, RegisterVT;
555564 return getRegisterType(getTypeToTransformTo(VT));
556565 }
557566 assert(0 && "Unsupported extended type!");
558 return EVT(EVT::Other); // Not reached
567 return EVT(MVT::Other); // Not reached
559568 }
560569
561570 /// getNumRegisters - Return the number of registers that this ValueType will
566575 /// type. For an i140 on a 32 bit machine this means 5 registers.
567576 unsigned getNumRegisters(EVT VT) const {
568577 if (VT.isSimple()) {
569 assert((unsigned)VT.getSimpleVT() < array_lengthof(NumRegistersForVT));
570 return NumRegistersForVT[VT.getSimpleVT()];
578 assert((unsigned)VT.getSimpleVT().SimpleTy <
579 array_lengthof(NumRegistersForVT));
580 return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
571581 }
572582 if (VT.isVector()) {
573583 EVT VT1, VT2;
637647 virtual EVT getOptimalMemOpType(uint64_t Size, unsigned Align,
638648 bool isSrcConst, bool isSrcStr,
639649 SelectionDAG &DAG) const {
640 return EVT::iAny;
650 return MVT::iAny;
641651 }
642652
643653 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp
868878
869879 /// setShiftAmountType - Describe the type that should be used for shift
870880 /// amounts. This type defaults to the pointer type.
871 void setShiftAmountType(EVT::SimpleValueType VT) { ShiftAmountTy = VT; }
881 void setShiftAmountType(MVT VT) { ShiftAmountTy = VT; }
872882
873883 /// setBooleanContents - Specify how the target extends the result of a
874884 /// boolean value from i1 to a wider type. See getBooleanContents.
932942 /// regclass for the specified value type. This indicates the selector can
933943 /// handle values of that class natively.
934944 void addRegisterClass(EVT VT, TargetRegisterClass *RC) {
935 assert((unsigned)VT.getSimpleVT() < array_lengthof(RegClassForVT));
945 assert((unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
936946 AvailableRegClasses.push_back(std::make_pair(VT, RC));
937 RegClassForVT[VT.getSimpleVT()] = RC;
947 RegClassForVT[VT.getSimpleVT().SimpleTy] = RC;
938948 }
939949
940950 /// computeRegisterProperties - Once all of the register classes are added,
943953
944954 /// setOperationAction - Indicate that the specified operation does not work
945955 /// with the specified type and indicate what to do about it.
946 void setOperationAction(unsigned Op, EVT::SimpleValueType VT,
956 void setOperationAction(unsigned Op, MVT VT,
947957 LegalizeAction Action) {
948 unsigned I = (unsigned)VT;
958 unsigned I = (unsigned)VT.SimpleTy;
949959 unsigned J = I & 31;
950960 I = I >> 5;
951961 OpActions[I][Op] &= ~(uint64_t(3UL) << (J*2));
954964
955965 /// setLoadExtAction - Indicate that the specified load with extension does
956966 /// not work with the with specified type and indicate what to do about it.
957 void setLoadExtAction(unsigned ExtType, EVT::SimpleValueType VT,
967 void setLoadExtAction(unsigned ExtType, MVT VT,
958968 LegalizeAction Action) {
959 assert((unsigned)VT < sizeof(LoadExtActions[0])*4 &&
969 assert((unsigned)VT.SimpleTy < sizeof(LoadExtActions[0])*4 &&
960970 ExtType < array_lengthof(LoadExtActions) &&
961971 "Table isn't big enough!");
962 LoadExtActions[ExtType] &= ~(uint64_t(3UL) << VT*2);
963 LoadExtActions[ExtType] |= (uint64_t)Action << VT*2;
972 LoadExtActions[ExtType] &= ~(uint64_t(3UL) << VT.SimpleTy*2);
973 LoadExtActions[ExtType] |= (uint64_t)Action << VT.SimpleTy*2;
964974 }
965975
966976 /// setTruncStoreAction - Indicate that the specified truncating store does
967977 /// not work with the with specified type and indicate what to do about it.
968 void setTruncStoreAction(EVT::SimpleValueType ValVT,
969 EVT::SimpleValueType MemVT,
978 void setTruncStoreAction(MVT ValVT, MVT MemVT,
970979 LegalizeAction Action) {
971 assert((unsigned)ValVT < array_lengthof(TruncStoreActions) &&
972 (unsigned)MemVT < sizeof(TruncStoreActions[0])*4 &&
980 assert((unsigned)ValVT.SimpleTy < array_lengthof(TruncStoreActions) &&
981 (unsigned)MemVT.SimpleTy < sizeof(TruncStoreActions[0])*4 &&
973982 "Table isn't big enough!");
974 TruncStoreActions[ValVT] &= ~(uint64_t(3UL) << MemVT*2);
975 TruncStoreActions[ValVT] |= (uint64_t)Action << MemVT*2;
983 TruncStoreActions[ValVT.SimpleTy] &= ~(uint64_t(3UL) << MemVT.SimpleTy*2);
984 TruncStoreActions[ValVT.SimpleTy] |= (uint64_t)Action << MemVT.SimpleTy*2;
976985 }
977986
978987 /// setIndexedLoadAction - Indicate that the specified indexed load does or
979988 /// does not work with the with specified type and indicate what to do abort
980989 /// it. NOTE: All indexed mode loads are initialized to Expand in
981990 /// TargetLowering.cpp
982 void setIndexedLoadAction(unsigned IdxMode, EVT::SimpleValueType VT,
991 void setIndexedLoadAction(unsigned IdxMode, MVT VT,
983992 LegalizeAction Action) {
984 assert((unsigned)VT < EVT::LAST_VALUETYPE &&
993 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE &&
985994 IdxMode < array_lengthof(IndexedModeActions[0][0]) &&
986995 "Table isn't big enough!");
987 IndexedModeActions[(unsigned)VT][0][IdxMode] = (uint8_t)Action;
996 IndexedModeActions[(unsigned)VT.SimpleTy][0][IdxMode] = (uint8_t)Action;
988997 }
989998
990999 /// setIndexedStoreAction - Indicate that the specified indexed store does or
9911000 /// does not work with the with specified type and indicate what to do about
9921001 /// it. NOTE: All indexed mode stores are initialized to Expand in
9931002 /// TargetLowering.cpp
994 void setIndexedStoreAction(unsigned IdxMode, EVT::SimpleValueType VT,
1003 void setIndexedStoreAction(unsigned IdxMode, MVT VT,
9951004 LegalizeAction Action) {
996 assert((unsigned)VT < EVT::LAST_VALUETYPE &&
1005 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE &&
9971006 IdxMode < array_lengthof(IndexedModeActions[0][1] ) &&
9981007 "Table isn't big enough!");
999 IndexedModeActions[(unsigned)VT][1][IdxMode] = (uint8_t)Action;
1008 IndexedModeActions[(unsigned)VT.SimpleTy][1][IdxMode] = (uint8_t)Action;
10001009 }
10011010
10021011 /// setConvertAction - Indicate that the specified conversion does or does
10031012 /// not work with the with specified type and indicate what to do about it.
1004 void setConvertAction(EVT::SimpleValueType FromVT, EVT::SimpleValueType ToVT,
1013 void setConvertAction(MVT FromVT, MVT ToVT,
10051014 LegalizeAction Action) {
1006 assert((unsigned)FromVT < array_lengthof(ConvertActions) &&
1007 (unsigned)ToVT < sizeof(ConvertActions[0])*4 &&
1015 assert((unsigned)FromVT.SimpleTy < array_lengthof(ConvertActions) &&
1016 (unsigned)ToVT.SimpleTy < sizeof(ConvertActions[0])*4 &&
10081017 "Table isn't big enough!");
1009 ConvertActions[FromVT] &= ~(uint64_t(3UL) << ToVT*2);
1010 ConvertActions[FromVT] |= (uint64_t)Action << ToVT*2;
1018 ConvertActions[FromVT.SimpleTy] &= ~(uint64_t(3UL) << ToVT.SimpleTy*2);
1019 ConvertActions[FromVT.SimpleTy] |= (uint64_t)Action << ToVT.SimpleTy*2;
10111020 }
10121021
10131022 /// setCondCodeAction - Indicate that the specified condition code is or isn't
10141023 /// supported on the target and indicate what to do about it.
1015 void setCondCodeAction(ISD::CondCode CC, EVT::SimpleValueType VT,
1024 void setCondCodeAction(ISD::CondCode CC, MVT VT,
10161025 LegalizeAction Action) {
1017 assert((unsigned)VT < sizeof(CondCodeActions[0])*4 &&
1026 assert((unsigned)VT.SimpleTy < sizeof(CondCodeActions[0])*4 &&
10181027 (unsigned)CC < array_lengthof(CondCodeActions) &&
10191028 "Table isn't big enough!");
1020 CondCodeActions[(unsigned)CC] &= ~(uint64_t(3UL) << VT*2);
1021 CondCodeActions[(unsigned)CC] |= (uint64_t)Action << VT*2;
1029 CondCodeActions[(unsigned)CC] &= ~(uint64_t(3UL) << VT.SimpleTy*2);
1030 CondCodeActions[(unsigned)CC] |= (uint64_t)Action << VT.SimpleTy*2;
10221031 }
10231032
10241033 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the
10251034 /// promotion code defaults to trying a larger integer/fp until it can find
10261035 /// one that works. If that default is insufficient, this method can be used
10271036 /// by the target to override the default.
1028 void AddPromotedToType(unsigned Opc, EVT::SimpleValueType OrigVT,
1029 EVT::SimpleValueType DestVT) {
1030 PromoteToType[std::make_pair(Opc, OrigVT)] = DestVT;
1037 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1038 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
10311039 }
10321040
10331041 /// addLegalFPImmediate - Indicate that this target can instruction select
13541362 AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
13551363 : InlineAsm::ConstraintInfo(info),
13561364 ConstraintType(TargetLowering::C_Unknown),
1357 CallOperandVal(0), ConstraintVT(EVT::Other) {
1365 CallOperandVal(0), ConstraintVT(MVT::Other) {
13581366 }
13591367 };
13601368
15261534
15271535 /// PointerTy - The type to use for pointers, usually i32 or i64.
15281536 ///
1529 EVT::SimpleValueType PointerTy;
1537 MVT PointerTy;
15301538
15311539 /// IsLittleEndian - True if this is a little endian target.
15321540 ///
15611569
15621570 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever
15631571 /// PointerTy is.
1564 EVT::SimpleValueType ShiftAmountTy;
1572 MVT ShiftAmountTy;
15651573
15661574 /// BooleanContents - Information about the contents of the high-bits in
15671575 /// boolean values held in a type wider than i1. See getBooleanContents.
16071615
16081616 /// RegClassForVT - This indicates the default register class to use for
16091617 /// each ValueType the target supports natively.
1610 TargetRegisterClass *RegClassForVT[EVT::LAST_VALUETYPE];
1611 unsigned char NumRegistersForVT[EVT::LAST_VALUETYPE];
1612 EVT RegisterTypeForVT[EVT::LAST_VALUETYPE];
1618 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1619 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1620 EVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
16131621
16141622 /// TransformToType - For any value types we are promoting or expanding, this
16151623 /// contains the value type that we are changing to. For Expanded types, this
16161624 /// contains one step of the expand (e.g. i64 -> i32), even if there are
16171625 /// multiple steps required (e.g. i64 -> i16). For types natively supported
16181626 /// by the system, this holds the same type (e.g. i32 -> i32).
1619 EVT TransformToType[EVT::LAST_VALUETYPE];
1627 EVT TransformToType[MVT::LAST_VALUETYPE];
16201628
16211629 /// OpActions - For each operation and each value type, keep a LegalizeAction
16221630 /// that indicates how instruction selection should deal with the operation.
16241632 /// operations that are not should be described. Note that operations on
16251633 /// non-legal value types are not described here.
16261634 /// This array is accessed using VT.getSimpleVT(), so it is subject to
1627 /// the EVT::MAX_ALLOWED_VALUETYPE * 2 bits.
1628 uint64_t OpActions[EVT::MAX_ALLOWED_VALUETYPE/(sizeof(uint64_t)*4)][ISD::BUILTIN_OP_END];
1635 /// the MVT::MAX_ALLOWED_VALUETYPE * 2 bits.
1636 uint64_t OpActions[MVT::MAX_ALLOWED_VALUETYPE/(sizeof(uint64_t)*4)][ISD::BUILTIN_OP_END];
16291637
16301638 /// LoadExtActions - For each load of load extension type and each value type,
16311639 /// keep a LegalizeAction that indicates how instruction selection should deal
16341642
16351643 /// TruncStoreActions - For each truncating store, keep a LegalizeAction that
16361644 /// indicates how instruction selection should deal with the store.
1637 uint64_t TruncStoreActions[EVT::LAST_VALUETYPE];
1645 uint64_t TruncStoreActions[MVT::LAST_VALUETYPE];
16381646
16391647 /// IndexedModeActions - For each indexed mode and each value type,
16401648 /// keep a pair of LegalizeAction that indicates how instruction
16421650 /// dimension is now the value_type for the reference. The second
16431651 /// dimension is the load [0] vs. store[1]. The third dimension
16441652 /// represents the various modes for load store.
1645 uint8_t IndexedModeActions[EVT::LAST_VALUETYPE][2][ISD::LAST_INDEXED_MODE];
1653 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][2][ISD::LAST_INDEXED_MODE];
16461654
16471655 /// ConvertActions - For each conversion from source type to destination type,
16481656 /// keep a LegalizeAction that indicates how instruction selection should
16491657 /// deal with the conversion.
16501658 /// Currently, this is used only for floating->floating conversions
16511659 /// (FP_EXTEND and FP_ROUND).
1652 uint64_t ConvertActions[EVT::LAST_VALUETYPE];
1660 uint64_t ConvertActions[MVT::LAST_VALUETYPE];
16531661
16541662 /// CondCodeActions - For each condition code (ISD::CondCode) keep a
16551663 /// LegalizeAction that indicates how instruction selection should
16741682 ///
16751683 /// Targets add entries to this map with AddPromotedToType(..), clients access
16761684 /// this with getTypeToPromoteTo(..).
1677 std::mapEVT::SimpleValueType>, EVT::SimpleValueType>
1685 std::mapMVT::SimpleValueType>, MVT::SimpleValueType>
16781686 PromoteToType;
16791687
16801688 /// LibcallRoutineNames - Stores the name each libcall.
117117 /// hasType - return true if this TargetRegisterClass has the ValueType vt.
118118 ///
119119 bool hasType(EVT vt) const {
120 for(int i = 0; VTs[i] != EVT::Other; ++i)
120 for(int i = 0; VTs[i].getSimpleVT().SimpleTy != MVT::Other; ++i)
121121 if (VTs[i] == vt)
122122 return true;
123123 return false;
131131
132132 vt_iterator vt_end() const {
133133 vt_iterator I = VTs;
134 while (*I != EVT::Other) ++I;
134 while (I->getSimpleVT().SimpleTy != MVT::Other) ++I;
135135 return I;
136136 }
137137
320320 /// register of the given type. If type is EVT::Other, then just return any
321321 /// register class the register belongs to.
322322 virtual const TargetRegisterClass *
323 getPhysicalRegisterRegClass(unsigned Reg, EVT VT = EVT::Other) const;
323 getPhysicalRegisterRegClass(unsigned Reg, EVT VT = MVT::Other) const;
324324
325325 /// getAllocatableSet - Returns a bitset indexed by register number
326326 /// indicating if a register is allocatable or not. If a register class is
511511 }]>;
512512
513513 def extloadi1 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
514 return cast(N)->getMemoryVT() == EVT::i1;
514 return cast(N)->getMemoryVT() == MVT::i1;
515515 }]>;
516516 def extloadi8 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
517 return cast(N)->getMemoryVT() == EVT::i8;
517 return cast(N)->getMemoryVT() == MVT::i8;
518518 }]>;
519519 def extloadi16 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
520 return cast(N)->getMemoryVT() == EVT::i16;
520 return cast(N)->getMemoryVT() == MVT::i16;
521521 }]>;
522522 def extloadi32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
523 return cast(N)->getMemoryVT() == EVT::i32;
523 return cast(N)->getMemoryVT() == MVT::i32;
524524 }]>;
525525 def extloadf32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
526 return cast(N)->getMemoryVT() == EVT::f32;
526 return cast(N)->getMemoryVT() == MVT::f32;
527527 }]>;
528528 def extloadf64 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
529 return cast(N)->getMemoryVT() == EVT::f64;
529 return cast(N)->getMemoryVT() == MVT::f64;
530530 }]>;
531531
532532 def sextloadi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
533 return cast(N)->getMemoryVT() == EVT::i1;
533 return cast(N)->getMemoryVT() == MVT::i1;
534534 }]>;
535535 def sextloadi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
536 return cast(N)->getMemoryVT() == EVT::i8;
536 return cast(N)->getMemoryVT() == MVT::i8;
537537 }]>;
538538 def sextloadi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
539 return cast(N)->getMemoryVT() == EVT::i16;
539 return cast(N)->getMemoryVT() == MVT::i16;
540540 }]>;
541541 def sextloadi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
542 return cast(N)->getMemoryVT() == EVT::i32;
542 return cast(N)->getMemoryVT() == MVT::i32;
543543 }]>;
544544
545545 def zextloadi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
546 return cast(N)->getMemoryVT() == EVT::i1;
546 return cast(N)->getMemoryVT() == MVT::i1;
547547 }]>;
548548 def zextloadi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
549 return cast(N)->getMemoryVT() == EVT::i8;
549 return cast(N)->getMemoryVT() == MVT::i8;
550550 }]>;
551551 def zextloadi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
552 return cast(N)->getMemoryVT() == EVT::i16;
552 return cast(N)->getMemoryVT() == MVT::i16;
553553 }]>;
554554 def zextloadi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
555 return cast(N)->getMemoryVT() == EVT::i32;
555 return cast(N)->getMemoryVT() == MVT::i32;
556556 }]>;
557557
558558 // store fragments.
572572 }]>;
573573 def truncstorei8 : PatFrag<(ops node:$val, node:$ptr),
574574 (truncstore node:$val, node:$ptr), [{
575 return cast(N)->getMemoryVT() == EVT::i8;
575 return cast(N)->getMemoryVT() == MVT::i8;
576576 }]>;
577577 def truncstorei16 : PatFrag<(ops node:$val, node:$ptr),
578578 (truncstore node:$val, node:$ptr), [{
579 return cast(N)->getMemoryVT() == EVT::i16;
579 return cast(N)->getMemoryVT() == MVT::i16;
580580 }]>;
581581 def truncstorei32 : PatFrag<(ops node:$val, node:$ptr),
582582 (truncstore node:$val, node:$ptr), [{
583 return cast(N)->getMemoryVT() == EVT::i32;
583 return cast(N)->getMemoryVT() == MVT::i32;
584584 }]>;
585585 def truncstoref32 : PatFrag<(ops node:$val, node:$ptr),
586586 (truncstore node:$val, node:$ptr), [{
587 return cast(N)->getMemoryVT() == EVT::f32;
587 return cast(N)->getMemoryVT() == MVT::f32;
588588 }]>;
589589 def truncstoref64 : PatFrag<(ops node:$val, node:$ptr),
590590 (truncstore node:$val, node:$ptr), [{
591 return cast(N)->getMemoryVT() == EVT::f64;
591 return cast(N)->getMemoryVT() == MVT::f64;
592592 }]>;
593593
594594 // indexed store fragments.
614614 }]>;
615615 def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
616616 (pre_truncst node:$val, node:$base, node:$offset), [{
617 return cast(N)->getMemoryVT() == EVT::i1;
617 return cast(N)->getMemoryVT() == MVT::i1;
618618 }]>;
619619 def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
620620 (pre_truncst node:$val, node:$base, node:$offset), [{
621 return cast(N)->getMemoryVT() == EVT::i8;
621 return cast(N)->getMemoryVT() == MVT::i8;
622622 }]>;
623623 def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
624624 (pre_truncst node:$val, node:$base, node:$offset), [{
625 return cast(N)->getMemoryVT() == EVT::i16;
625 return cast(N)->getMemoryVT() == MVT::i16;
626626 }]>;
627627 def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
628628 (pre_truncst node:$val, node:$base, node:$offset), [{
629 return cast(N)->getMemoryVT() == EVT::i32;
629 return cast(N)->getMemoryVT() == MVT::i32;
630630 }]>;
631631 def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
632632 (pre_truncst node:$val, node:$base, node:$offset), [{
633 return cast(N)->getMemoryVT() == EVT::f32;
633 return cast(N)->getMemoryVT() == MVT::f32;
634634 }]>;
635635
636636 def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
646646 }]>;
647647 def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
648648 (post_truncst node:$val, node:$base, node:$offset), [{
649 return cast(N)->getMemoryVT() == EVT::i1;
649 return cast(N)->getMemoryVT() == MVT::i1;
650650 }]>;
651651 def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
652652 (post_truncst node:$val, node:$base, node:$offset), [{
653 return cast(N)->getMemoryVT() == EVT::i8;
653 return cast(N)->getMemoryVT() == MVT::i8;
654654 }]>;
655655 def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
656656 (post_truncst node:$val, node:$base, node:$offset), [{
657 return cast(N)->getMemoryVT() == EVT::i16;
657 return cast(N)->getMemoryVT() == MVT::i16;
658658 }]>;
659659 def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
660660 (post_truncst node:$val, node:$base, node:$offset), [{
661 return cast(N)->getMemoryVT() == EVT::i32;
661 return cast(N)->getMemoryVT() == MVT::i32;
662662 }]>;
663663 def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
664664 (post_truncst node:$val, node:$base, node:$offset), [{
665 return cast(N)->getMemoryVT() == EVT::f32;
665 return cast(N)->getMemoryVT() == MVT::f32;
666666 }]>;
667667
668668 // setcc convenience fragments.
710710 def atomic_cmp_swap_8 :
711711 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
712712 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
713 return cast(N)->getMemoryVT() == EVT::i8;
713 return cast(N)->getMemoryVT() == MVT::i8;
714714 }]>;
715715 def atomic_cmp_swap_16 :
716716 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
717717 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
718 return cast(N)->getMemoryVT() == EVT::i16;
718 return cast(N)->getMemoryVT() == MVT::i16;
719719 }]>;
720720 def atomic_cmp_swap_32 :
721721 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
722722 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
723 return cast(N)->getMemoryVT() == EVT::i32;
723 return cast(N)->getMemoryVT() == MVT::i32;
724724 }]>;
725725 def atomic_cmp_swap_64 :
726726 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
727727 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
728 return cast(N)->getMemoryVT() == EVT::i64;
728 return cast(N)->getMemoryVT() == MVT::i64;
729729 }]>;
730730
731731 multiclass binary_atomic_op {
732732 def _8 : PatFrag<(ops node:$ptr, node:$val),
733733 (atomic_op node:$ptr, node:$val), [{
734 return cast(N)->getMemoryVT() == EVT::i8;
734 return cast(N)->getMemoryVT() == MVT::i8;
735735 }]>;
736736 def _16 : PatFrag<(ops node:$ptr, node:$val),
737737 (atomic_op node:$ptr, node:$val), [{
738 return cast(N)->getMemoryVT() == EVT::i16;
738 return cast(N)->getMemoryVT() == MVT::i16;
739739 }]>;
740740 def _32 : PatFrag<(ops node:$ptr, node:$val),
741741 (atomic_op node:$ptr, node:$val), [{
742 return cast(N)->getMemoryVT() == EVT::i32;
742 return cast(N)->getMemoryVT() == MVT::i32;
743743 }]>;
744744 def _64 : PatFrag<(ops node:$ptr, node:$val),
745745 (atomic_op node:$ptr, node:$val), [{
746 return cast(N)->getMemoryVT() == EVT::i64;
746 return cast(N)->getMemoryVT() == MVT::i64;
747747 }]>;
748748 }
749749
330330 static char isNegatibleForFree(SDValue Op, bool LegalOperations,
331331 unsigned Depth = 0) {
332332 // No compile time optimizations on this type.
333 if (Op.getValueType() == EVT::ppcf128)
333 if (Op.getValueType() == MVT::ppcf128)
334334 return 0;
335335
336336 // fneg is removable even if it has multiple uses.
832832 /// otherwise return a null sd operand.
833833 static SDValue getInputChainForNode(SDNode *N) {
834834 if (unsigned NumOps = N->getNumOperands()) {
835 if (N->getOperand(0).getValueType() == EVT::Other)
835 if (N->getOperand(0).getValueType() == MVT::Other)
836836 return N->getOperand(0);
837 else if (N->getOperand(NumOps-1).getValueType() == EVT::Other)
837 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
838838 return N->getOperand(NumOps-1);
839839 for (unsigned i = 1; i < NumOps-1; ++i)
840 if (N->getOperand(i).getValueType() == EVT::Other)
840 if (N->getOperand(i).getValueType() == MVT::Other)
841841 return N->getOperand(i);
842842 }
843843 return SDValue();
910910 } else {
911911 // New and improved token factor.
912912 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
913 EVT::Other, &Ops[0], Ops.size());
913 MVT::Other, &Ops[0], Ops.size());
914914 }
915915
916916 // Don't add users to work list.
10921092 if (N->hasNUsesOfValue(0, 1))
10931093 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0),
10941094 DAG.getNode(ISD::CARRY_FALSE,
1095 N->getDebugLoc(), EVT::Flag));
1095 N->getDebugLoc(), MVT::Flag));
10961096
10971097 // canonicalize constant to RHS.
10981098 if (N0C && !N1C)
11011101 // fold (addc x, 0) -> x + no carry out
11021102 if (N1C && N1C->isNullValue())
11031103 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
1104 N->getDebugLoc(), EVT::Flag));
1104 N->getDebugLoc(), MVT::Flag));
11051105
11061106 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
11071107 APInt LHSZero, LHSOne;
11181118 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
11191119 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1),
11201120 DAG.getNode(ISD::CARRY_FALSE,
1121 N->getDebugLoc(), EVT::Flag));
1121 N->getDebugLoc(), MVT::Flag));
11221122 }
11231123
11241124 return SDValue();
18771877 LN0->isUnindexed() && N0.hasOneUse() &&
18781878 // Do not change the width of a volatile load.
18791879 !LN0->isVolatile()) {
1880 EVT ExtVT = EVT::Other;
1880 EVT ExtVT = MVT::Other;
18811881 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits();
18821882 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue()))
18831883 ExtVT = EVT::getIntegerVT(ActiveBits);
18861886
18871887 // Do not generate loads of non-round integer types since these can
18881888 // be expensive (and would be wrong if the type is not byte sized).
1889 if (ExtVT != EVT::Other && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() &&
1889 if (ExtVT != MVT::Other && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() &&
18901890 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
18911891 EVT PtrType = N0.getOperand(1).getValueType();
18921892
22882288 }
22892289
22902290 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc
2291 if (N1C && N1C->getAPIntValue() == 1 && VT == EVT::i1 &&
2291 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 &&
22922292 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
22932293 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
22942294 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
27922792 if (N0C && N0C->isNullValue())
27932793 return N2;
27942794 // fold (select C, 1, X) -> (or C, X)
2795 if (VT == EVT::i1 && N1C && N1C->getAPIntValue() == 1)
2795 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1)
27962796 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
27972797 // fold (select C, 0, 1) -> (xor C, 1)
27982798 if (VT.isInteger() &&
2799 (VT0 == EVT::i1 ||
2799 (VT0 == MVT::i1 ||
28002800 (VT0.isInteger() &&
28012801 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) &&
28022802 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) {
28122812 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode);
28132813 }
28142814 // fold (select C, 0, X) -> (and (not C), X)
2815 if (VT == VT0 && VT == EVT::i1 && N1C && N1C->isNullValue()) {
2815 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
28162816 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
28172817 AddToWorkList(NOTNode.getNode());
28182818 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2);
28192819 }
28202820 // fold (select C, X, 1) -> (or (not C), X)
2821 if (VT == VT0 && VT == EVT::i1 && N2C && N2C->getAPIntValue() == 1) {
2821 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) {
28222822 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
28232823 AddToWorkList(NOTNode.getNode());
28242824 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1);
28252825 }
28262826 // fold (select C, X, 0) -> (and C, X)
2827 if (VT == EVT::i1 && N2C && N2C->isNullValue())
2827 if (VT == MVT::i1 && N2C && N2C->isNullValue())
28282828 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
28292829 // fold (select X, X, Y) -> (or X, Y)
28302830 // fold (select X, 1, Y) -> (or X, Y)
2831 if (VT == EVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1)))
2831 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1)))
28322832 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
28332833 // fold (select X, Y, X) -> (and X, Y)
28342834 // fold (select X, Y, 0) -> (and X, Y)
2835 if (VT == EVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0)))
2835 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0)))
28362836 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
28372837
28382838 // If we can fold this based on the true/false value, do so.
28422842 // fold selects based on a setcc into other things, such as min/max/abs
28432843 if (N0.getOpcode() == ISD::SETCC) {
28442844 // FIXME:
2845 // Check against EVT::Other for SELECT_CC, which is a workaround for targets
2845 // Check against MVT::Other for SELECT_CC, which is a workaround for targets
28462846 // having to say they don't support SELECT_CC on every type the DAG knows
28472847 // about, since there is no way to mark an opcode illegal at all value types
2848 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, EVT::Other) &&
2848 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) &&
28492849 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT))
28502850 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT,
28512851 N0.getOperand(0), N0.getOperand(1),
38863886 if (SrcEltVT.isFloatingPoint()) {
38873887 // Convert the input float vector to a int vector where the elements are the
38883888 // same sizes.
3889 assert((SrcEltVT == EVT::f32 || SrcEltVT == EVT::f64) && "Unknown FP VT!");
3889 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
38903890 EVT IntVT = EVT::getIntegerVT(SrcEltVT.getSizeInBits());
38913891 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode();
38923892 SrcEltVT = IntVT;
38953895 // Now we know the input is an integer vector. If the output is a FP type,
38963896 // convert to integer first, then to FP of the right size.
38973897 if (DstEltVT.isFloatingPoint()) {
3898 assert((DstEltVT == EVT::f32 || DstEltVT == EVT::f64) && "Unknown FP VT!");
3898 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
38993899 EVT TmpVT = EVT::getIntegerVT(DstEltVT.getSizeInBits());
39003900 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode();
39013901
39873987 }
39883988
39893989 // fold (fadd c1, c2) -> (fadd c1, c2)
3990 if (N0CFP && N1CFP && VT != EVT::ppcf128)
3990 if (N0CFP && N1CFP && VT != MVT::ppcf128)
39913991 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1);
39923992 // canonicalize constant to RHS
39933993 if (N0CFP && !N1CFP)
40284028 }
40294029
40304030 // fold (fsub c1, c2) -> c1-c2
4031 if (N0CFP && N1CFP && VT != EVT::ppcf128)
4031 if (N0CFP && N1CFP && VT != MVT::ppcf128)
40324032 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1);
40334033 // fold (fsub A, 0) -> A
40344034 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
40624062 }
40634063
40644064 // fold (fmul c1, c2) -> c1*c2
4065 if (N0CFP && N1CFP && VT != EVT::ppcf128)
4065 if (N0CFP && N1CFP && VT != MVT::ppcf128)
40664066 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1);
40674067 // canonicalize constant to RHS
40684068 if (N0CFP && !N1CFP)
41174117 }
41184118
41194119 // fold (fdiv c1, c2) -> c1/c2
4120 if (N0CFP && N1CFP && VT != EVT::ppcf128)
4120 if (N0CFP && N1CFP && VT != MVT::ppcf128)
41214121 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1);
41224122
41234123
41444144 EVT VT = N->getValueType(0);
41454145
41464146 // fold (frem c1, c2) -> fmod(c1,c2)
4147 if (N0CFP && N1CFP && VT != EVT::ppcf128)
4147 if (N0CFP && N1CFP && VT != MVT::ppcf128)
41484148 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1);
41494149
41504150 return SDValue();
41574157 ConstantFPSDNode *N1CFP = dyn_cast(N1);
41584158 EVT VT = N->getValueType(0);
41594159
4160 if (N0CFP && N1CFP && VT != EVT::ppcf128) // Constant fold
4160 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold
41614161 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1);
41624162
41634163 if (N1CFP) {
42074207 EVT OpVT = N0.getValueType();
42084208
42094209 // fold (sint_to_fp c1) -> c1fp
4210 if (N0C && OpVT != EVT::ppcf128)
4210 if (N0C && OpVT != MVT::ppcf128)
42114211 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
42124212
42134213 // If the input is a legal type, and SINT_TO_FP is not legal on this target,
42294229 EVT OpVT = N0.getValueType();
42304230
42314231 // fold (uint_to_fp c1) -> c1fp
4232 if (N0C && OpVT != EVT::ppcf128)
4232 if (N0C && OpVT != MVT::ppcf128)
42334233 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
42344234
42354235 // If the input is a legal type, and UINT_TO_FP is not legal on this target,
42624262 EVT VT = N->getValueType(0);
42634263
42644264 // fold (fp_to_uint c1fp) -> c1
4265 if (N0CFP && VT != EVT::ppcf128)
4265 if (N0CFP && VT != MVT::ppcf128)
42664266 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0);
42674267
42684268 return SDValue();
42754275 EVT VT = N->getValueType(0);
42764276
42774277 // fold (fp_round c1fp) -> c1fp
4278 if (N0CFP && N0.getValueType() != EVT::ppcf128)
4278 if (N0CFP && N0.getValueType() != MVT::ppcf128)
42794279 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1);
42804280
42814281 // fold (fp_round (fp_extend x)) -> x
43294329 return SDValue();
43304330
43314331 // fold (fp_extend c1fp) -> c1fp
4332 if (N0CFP && VT != EVT::ppcf128)
4332 if (N0CFP && VT != MVT::ppcf128)
43334333 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0);
43344334
43354335 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
43974397 EVT VT = N->getValueType(0);
43984398
43994399 // fold (fabs c1) -> fabs(c1)
4400 if (N0CFP && VT != EVT::ppcf128)
4400 if (N0CFP && VT != MVT::ppcf128)
44014401 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
44024402 // fold (fabs (fabs x)) -> (fabs x)
44034403 if (N0.getOpcode() == ISD::FABS)
44374437 return Chain;
44384438 // unconditional branch
44394439 if (N1C && N1C->getAPIntValue() == 1)
4440 return DAG.getNode(ISD::BR, N->getDebugLoc(), EVT::Other, Chain, N2);
4440 return DAG.getNode(ISD::BR, N->getDebugLoc(), MVT::Other, Chain, N2);
44414441 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
44424442 // on the target.
44434443 if (N1.getOpcode() == ISD::SETCC &&
4444 TLI.isOperationLegalOrCustom(ISD::BR_CC, EVT::Other)) {
4445 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), EVT::Other,
4444 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) {
4445 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
44464446 Chain, N1.getOperand(2),
44474447 N1.getOperand(0), N1.getOperand(1), N2);
44484448 }
44904490 removeFromWorkList(N1.getNode());
44914491 DAG.DeleteNode(N1.getNode());
44924492 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
4493 EVT::Other, Chain, SetCC, N2);
4493 MVT::Other, Chain, SetCC, N2);
44944494 }
44954495 }
44964496 }
45154515
45164516 // fold br_cc true, dest -> br dest (unconditional branch)
45174517 if (SCCC && !SCCC->isNullValue())
4518 return DAG.getNode(ISD::BR, N->getDebugLoc(), EVT::Other,
4518 return DAG.getNode(ISD::BR, N->getDebugLoc(), MVT::Other,
45194519 N->getOperand(0), N->getOperand(4));
45204520 // fold br_cc false, dest -> unconditional fall through
45214521 if (SCCC && SCCC->isNullValue())
45234523
45244524 // fold to a simpler setcc
45254525 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
4526 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), EVT::Other,
4526 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
45274527 N->getOperand(0), Simp.getOperand(2),
45284528 Simp.getOperand(0), Simp.getOperand(1),
45294529 N->getOperand(4));
48584858 // the updated indexed value in case of indexed loads), change uses of the
48594859 // chain value into uses of the chain input (i.e. delete the dead load).
48604860 if (!LD->isVolatile()) {
4861 if (N->getValueType(1) == EVT::Other) {
4861 if (N->getValueType(1) == MVT::Other) {
48624862 // Unindexed loads.
48634863 if (N->hasNUsesOfValue(0, 0)) {
48644864 // It's not safe to use the two value CombineTo variant here. e.g.
48824882 }
48834883 } else {
48844884 // Indexed loads.
4885 assert(N->getValueType(2) == EVT::Other && "Malformed indexed loads?");
4885 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
48864886 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) {
48874887 SDValue Undef = DAG.getUNDEF(N->getValueType(0));
48884888 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG));
49414941
49424942 // Create token factor to keep old chain connected.
49434943 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
4944 EVT::Other, Chain, ReplLoad.getValue(1));
4944 MVT::Other, Chain, ReplLoad.getValue(1));
49454945
49464946 // Replace uses with load result and token factor. Don't add users
49474947 // to work list.
50955095 // transform should not be done in this case.
50965096 if (Value.getOpcode() != ISD::TargetConstantFP) {
50975097 SDValue Tmp;
5098 switch (CFP->getValueType(0).getSimpleVT()) {
5098 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) {
50995099 default: llvm_unreachable("Unknown FP type");
5100 case EVT::f80: // We don't do this for these yet.
5101 case EVT::f128:
5102 case EVT::ppcf128:
5100 case MVT::f80: // We don't do this for these yet.
5101 case MVT::f128:
5102 case MVT::ppcf128:
51035103 break;
5104 case EVT::f32:
5105 if (((TLI.isTypeLegal(EVT::i32) || !LegalTypes) && !LegalOperations &&
5104 case MVT::f32:
5105 if (((TLI.isTypeLegal(MVT::i32) || !LegalTypes) && !LegalOperations &&
51065106 !ST->isVolatile()) ||
5107 TLI.isOperationLegalOrCustom(ISD::STORE, EVT::i32)) {
5107 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
51085108 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
5109 bitcastToAPInt().getZExtValue(), EVT::i32);
5109 bitcastToAPInt().getZExtValue(), MVT::i32);
51105110 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
51115111 Ptr, ST->getSrcValue(),
51125112 ST->getSrcValueOffset(), ST->isVolatile(),
51135113 ST->getAlignment());
51145114 }
51155115 break;
5116 case EVT::f64:
5117 if (((TLI.isTypeLegal(EVT::i64) || !LegalTypes) && !LegalOperations &&
5116 case MVT::f64:
5117 if (((TLI.isTypeLegal(MVT::i64) || !LegalTypes) && !LegalOperations &&
51185118 !ST->isVolatile()) ||
5119 TLI.isOperationLegalOrCustom(ISD::STORE, EVT::i64)) {
5119 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) {
51205120 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
5121 getZExtValue(), EVT::i64);
5121 getZExtValue(), MVT::i64);
51225122 return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
51235123 Ptr, ST->getSrcValue(),
51245124 ST->getSrcValueOffset(), ST->isVolatile(),
51255125 ST->getAlignment());
51265126 } else if (!ST->isVolatile() &&
5127 TLI.isOperationLegalOrCustom(ISD::STORE, EVT::i32)) {
5127 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
51285128 // Many FP stores are not made apparent until after legalize, e.g. for
51295129 // argument passing. Since this is so common, custom legalize the
51305130 // 64-bit integer store into two 32-bit stores.
51315131 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
5132 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, EVT::i32);
5133 SDValue Hi = DAG.getConstant(Val >> 32, EVT::i32);
5132 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
5133 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32);
51345134 if (TLI.isBigEndian()) std::swap(Lo, Hi);
51355135
51365136 int SVOffset = ST->getSrcValueOffset();
51485148 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi,
51495149 Ptr, ST->getSrcValue(),
51505150 SVOffset, isVolatile, Alignment);
5151 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), EVT::Other,
5151 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
51525152 St0, St1);
51535153 }
51545154
51785178
51795179 // Create token to keep both nodes around.
51805180 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
5181 EVT::Other, Chain, ReplStore);
5181 MVT::Other, Chain, ReplStore);
51825182
51835183 // Don't add users to work list.
51845184 return CombineTo(N, Token, false);
59315931 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
59325932 N2.getValueType(), SCC);
59335933 } else {
5934 SCC = DAG.getSetCC(N0.getDebugLoc(), EVT::i1, N0, N1, CC);
5934 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC);
59355935 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
59365936 N2.getValueType(), SCC);
59375937 }
62386238 }
62396239
62406240 // Construct a custom tailored token factor.
6241 SDValue NewChain = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), EVT::Other,
6241 SDValue NewChain = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
62426242 &Aliases[0], Aliases.size());
62436243
62446244 // Make sure the old chain gets cleaned up.
6464 // Ignore illegal types. We must do this before looking up the value
6565 // in ValueMap because Arguments are given virtual registers regardless
6666 // of whether FastISel can handle them.
67 EVT::SimpleValueType VT = RealVT.getSimpleVT();
67 MVT VT = RealVT.getSimpleVT();
6868 if (!TLI.isTypeLegal(VT)) {
69 // Promote EVT::i1 to a legal type though, because it's common and easy.
70 if (VT == EVT::i1)
69 // Promote MVT::i1 to a legal type though, because it's common and easy.
70 if (VT == MVT::i1)
7171 VT = TLI.getTypeToTransformTo(VT).getSimpleVT();
7272 else
7373 return 0;
189189 ///
190190 bool FastISel::SelectBinaryOp(User *I, ISD::NodeType ISDOpcode) {
191191 EVT VT = EVT::getEVT(I->getType(), /*HandleUnknown=*/true);
192 if (VT == EVT::Other || !VT.isSimple())
192 if (VT == MVT::Other || !VT.isSimple())
193193 // Unhandled type. Halt "fast" selection and bail.
194194 return false;
195195
198198 // under the assumption that i64 won't be used if the target doesn't
199199 // support it.
200200 if (!TLI.isTypeLegal(VT)) {
201 // EVT::i1 is special. Allow AND, OR, or XOR because they
201 // MVT::i1 is special. Allow AND, OR, or XOR because they
202202 // don't require additional zeroing, which makes them easy.
203 if (VT == EVT::i1 &&
203 if (VT == MVT::i1 &&
204204 (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
205205 ISDOpcode == ISD::XOR))
206206 VT = TLI.getTypeToTransformTo(VT);
260260 return false;
261261
262262 const Type *Ty = I->getOperand(0)->getType();
263 EVT::SimpleValueType VT = TLI.getPointerTy();
263 MVT VT = TLI.getPointerTy();
264264 for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end();
265265 OI != E; ++OI) {
266266 Value *Idx = *OI;
456456 default: break;
457457 case TargetLowering::Expand: {
458458 EVT VT = (IID == Intrinsic::eh_selector_i32 ?
459 EVT::i32 : EVT::i64);
459 MVT::i32 : MVT::i64);
460460
461461 if (MMI) {
462462 if (MBB->isLandingPad())
496496 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
497497 EVT DstVT = TLI.getValueType(I->getType());
498498
499 if (SrcVT == EVT::Other || !SrcVT.isSimple() ||
500 DstVT == EVT::Other || !DstVT.isSimple())
499 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
500 DstVT == MVT::Other || !DstVT.isSimple())
501501 // Unhandled type. Halt "fast" selection and bail.
502502 return false;
503503
505505 // it may be i1 if we're doing a truncate because that's
506506 // easy and somewhat common.
507507 if (!TLI.isTypeLegal(DstVT))
508 if (DstVT != EVT::i1 || Opcode != ISD::TRUNCATE)
508 if (DstVT != MVT::i1 || Opcode != ISD::TRUNCATE)
509509 // Unhandled type. Halt "fast" selection and bail.
510510 return false;
511511
513513 // it may be i1 if we're doing zero-extension because that's
514514 // easy and somewhat common.
515515 if (!TLI.isTypeLegal(SrcVT))
516 if (SrcVT != EVT::i1 || Opcode != ISD::ZERO_EXTEND)
516 if (SrcVT != MVT::i1 || Opcode != ISD::ZERO_EXTEND)
517517 // Unhandled type. Halt "fast" selection and bail.
518518 return false;
519519
523523 return false;
524524
525525 // If the operand is i1, arrange for the high bits in the register to be zero.
526 if (SrcVT == EVT::i1) {
526 if (SrcVT == MVT::i1) {
527527 SrcVT = TLI.getTypeToTransformTo(SrcVT);
528528 InputReg = FastEmitZExtFromI1(SrcVT.getSimpleVT(), InputReg);
529529 if (!InputReg)
530530 return false;
531531 }
532532 // If the result is i1, truncate to the target's type for i1 first.
533 if (DstVT == EVT::i1)
533 if (DstVT == MVT::i1)
534534 DstVT = TLI.getTypeToTransformTo(DstVT);
535535
536536 unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
558558 EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
559559 EVT DstVT = TLI.getValueType(I->getType());
560560
561 if (SrcVT == EVT::Other || !SrcVT.isSimple() ||
562 DstVT == EVT::Other || !DstVT.isSimple() ||
561 if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
562 DstVT == MVT::Other || !DstVT.isSimple() ||
563563 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
564564 // Unhandled type. Halt "fast" selection and bail.
565565 return false;
758758
759759 FastISel::~FastISel() {}
760760
761 unsigned FastISel::FastEmit_(EVT::SimpleValueType, EVT::SimpleValueType,
761 unsigned FastISel::FastEmit_(MVT, MVT,
762762 ISD::NodeType) {
763763 return 0;
764764 }
765765
766 unsigned FastISel::FastEmit_r(EVT::SimpleValueType, EVT::SimpleValueType,
766 unsigned FastISel::FastEmit_r(MVT, MVT,
767767 ISD::NodeType, unsigned /*Op0*/) {
768768 return 0;
769769 }
770770
771 unsigned FastISel::FastEmit_rr(EVT::SimpleValueType, EVT::SimpleValueType,
771 unsigned FastISel::FastEmit_rr(MVT, MVT,
772772 ISD::NodeType, unsigned /*Op0*/,
773773 unsigned /*Op0*/) {
774774 return 0;
775775 }
776776
777 unsigned FastISel::FastEmit_i(EVT::SimpleValueType, EVT::SimpleValueType,
778 ISD::NodeType, uint64_t /*Imm*/) {
777 unsigned FastISel::FastEmit_i(MVT, MVT, ISD::NodeType, uint64_t /*Imm*/) {
779778 return 0;
780779 }
781780
782 unsigned FastISel::FastEmit_f(EVT::SimpleValueType, EVT::SimpleValueType,
781 unsigned FastISel::FastEmit_f(MVT, MVT,
783782 ISD::NodeType, ConstantFP * /*FPImm*/) {
784783 return 0;
785784 }
786785
787 unsigned FastISel::FastEmit_ri(EVT::SimpleValueType, EVT::SimpleValueType,
786 unsigned FastISel::FastEmit_ri(MVT, MVT,
788787 ISD::NodeType, unsigned /*Op0*/,
789788 uint64_t /*Imm*/) {
790789 return 0;
791790 }
792791
793 unsigned FastISel::FastEmit_rf(EVT::SimpleValueType, EVT::SimpleValueType,
792 unsigned FastISel::FastEmit_rf(MVT, MVT,
794793 ISD::NodeType, unsigned /*Op0*/,
795794 ConstantFP * /*FPImm*/) {
796795 return 0;
797796 }
798797
799 unsigned FastISel::FastEmit_rri(EVT::SimpleValueType, EVT::SimpleValueType,
798 unsigned FastISel::FastEmit_rri(MVT, MVT,
800799 ISD::NodeType,
801800 unsigned /*Op0*/, unsigned /*Op1*/,
802801 uint64_t /*Imm*/) {
807806 /// to emit an instruction with an immediate operand using FastEmit_ri.
808807 /// If that fails, it materializes the immediate into a register and try
809808 /// FastEmit_rr instead.
810 unsigned FastISel::FastEmit_ri_(EVT::SimpleValueType VT, ISD::NodeType Opcode,
809 unsigned FastISel::FastEmit_ri_(MVT VT, ISD::NodeType Opcode,
811810 unsigned Op0, uint64_t Imm,
812 EVT::SimpleValueType ImmType) {
811 MVT ImmType) {
813812 // First check if immediate type is legal. If not, we can't use the ri form.
814813 unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm);
815814 if (ResultReg != 0)
824823 /// to emit an instruction with a floating-point immediate operand using
825824 /// FastEmit_rf. If that fails, it materializes the immediate into a register
826825 /// and try FastEmit_rr instead.
827 unsigned FastISel::FastEmit_rf_(EVT::SimpleValueType VT, ISD::NodeType Opcode,
826 unsigned FastISel::FastEmit_rf_(MVT VT, ISD::NodeType Opcode,
828827 unsigned Op0, ConstantFP *FPImm,
829 EVT::SimpleValueType ImmType) {
828 MVT ImmType) {
830829 // First check if immediate type is legal. If not, we can't use the rf form.
831830 unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm);
832831 if (ResultReg != 0)
987986 return ResultReg;
988987 }
989988
990 unsigned FastISel::FastEmitInst_extractsubreg(EVT::SimpleValueType RetVT,
989 unsigned FastISel::FastEmitInst_extractsubreg(MVT RetVT,
991990 unsigned Op0, uint32_t Idx) {
992991 const TargetRegisterClass* RC = MRI.getRegClass(Op0);
993992
10081007
10091008 /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
10101009 /// with all but the least significant bit set to zero.
1011 unsigned FastISel::FastEmitZExtFromI1(EVT::SimpleValueType VT, unsigned Op) {
1010 unsigned FastISel::FastEmitZExtFromI1(MVT VT, unsigned Op) {
10121011 return FastEmit_ri(VT, VT, ISD::AND, Op, 1);
10131012 }
212212 CodeGenOpt::Level ol)
213213 : TLI(dag.getTargetLoweringInfo()), DAG(dag), OptLevel(ol),
214214 ValueTypeActions(TLI.getValueTypeActions()) {
215 assert(EVT::LAST_VALUETYPE <= EVT::MAX_ALLOWED_VALUETYPE &&
215 assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
216216 "Too many value types for ValueTypeActions to hold!");
217217 }
218218
253253
254254 // The chain is usually at the end.
255255 SDValue TheChain(Node, Node->getNumValues()-1);
256 if (TheChain.getValueType() != EVT::Other) {
256 if (TheChain.getValueType() != MVT::Other) {
257257 // Sometimes it's at the beginning.
258258 TheChain = SDValue(Node, 0);
259 if (TheChain.getValueType() != EVT::Other) {
259 if (TheChain.getValueType() != MVT::Other) {
260260 // Otherwise, hunt for it.
261261 for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
262 if (Node->getValueType(i) == EVT::Other) {
262 if (Node->getValueType(i) == MVT::Other) {
263263 TheChain = SDValue(Node, i);
264264 break;
265265 }
266266
267267 // Otherwise, we walked into a node without a chain.
268 if (TheChain.getValueType() != EVT::Other)
268 if (TheChain.getValueType() != MVT::Other)
269269 return 0;
270270 }
271271 }
289289 assert(Node && "Didn't find callseq_start for a call??");
290290 if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
291291
292 assert(Node->getOperand(0).getValueType() == EVT::Other &&
292 assert(Node->getOperand(0).getValueType() == MVT::Other &&
293293 "Node doesn't have a token chain argument!");
294294 return FindCallStartFromCallEnd(Node->getOperand(0).getNode());
295295 }
346346 EVT VT = CFP->getValueType(0);
347347 ConstantFP *LLVMC = const_cast(CFP->getConstantFPValue());
348348 if (!UseCP) {
349 assert((VT == EVT::f64 || VT == EVT::f32) && "Invalid type expansion");
349 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
350350 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
351 (VT == EVT::f64) ? EVT::i64 : EVT::i32);
351 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
352352 }
353353
354354 EVT OrigVT = VT;
355355 EVT SVT = VT;
356 while (SVT != EVT::f32) {
357 SVT = (EVT::SimpleValueType)(SVT.getSimpleVT() - 1);
356 while (SVT != MVT::f32) {
357 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1);
358358 if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) &&
359359 // Only do this if the target has a native EXTLOAD instruction from
360360 // smaller type.
449449 MemVT, ST->isVolatile(),
450450 MinAlign(ST->getAlignment(), Offset)));
451451 // The order of the stores doesn't matter - say it with a TokenFactor.
452 return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &Stores[0],
452 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
453453 Stores.size());
454454 }
455455 }
458458 "Unaligned store of unknown type.");
459459 // Get the half-size VT
460460 EVT NewStoredVT =
461 (EVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1);
461 (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT().SimpleTy - 1);
462462 int NumBits = NewStoredVT.getSizeInBits();
463463 int IncrementSize = NumBits / 8;
464464
479479 ST->getSrcValue(), SVOffset + IncrementSize,
480480 NewStoredVT, ST->isVolatile(), Alignment);
481481
482 return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Store1, Store2);
482 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
483483 }
484484
485485 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
551551 NULL, 0, MemVT));
552552
553553 // The order of the stores doesn't matter - say it with a TokenFactor.
554 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &Stores[0],
554 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
555555 Stores.size());
556556
557557 // Finally, perform the original load only redirected to the stack slot.
606606 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
607607 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
608608
609 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo.getValue(1),
609 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
610610 Hi.getValue(1));
611611
612612 SDValue Ops[] = { Result, TF };
701701 bool isVolatile = ST->isVolatile();
702702 DebugLoc dl = ST->getDebugLoc();
703703 if (ConstantFPSDNode *CFP = dyn_cast(ST->getValue())) {
704 if (CFP->getValueType(0) == EVT::f32 &&
705 getTypeAction(EVT::i32) == Legal) {
704 if (CFP->getValueType(0) == MVT::f32 &&
705 getTypeAction(MVT::i32) == Legal) {
706706 Tmp3 = DAG.getConstant(CFP->getValueAPF().
707707 bitcastToAPInt().zextOrTrunc(32),
708 EVT::i32);
708 MVT::i32);
709709 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
710710 SVOffset, isVolatile, Alignment);
711 } else if (CFP->getValueType(0) == EVT::f64) {
711 } else if (CFP->getValueType(0) == MVT::f64) {
712712 // If this target supports 64-bit registers, do a single 64-bit store.
713 if (getTypeAction(EVT::i64) == Legal) {
713 if (getTypeAction(MVT::i64) == Legal) {
714714 Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
715 zextOrTrunc(64), EVT::i64);
715 zextOrTrunc(64), MVT::i64);
716716 return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
717717 SVOffset, isVolatile, Alignment);
718 } else if (getTypeAction(EVT::i32) == Legal && !ST->isVolatile()) {
718 } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
719719 // Otherwise, if the target supports 32-bit registers, use 2 32-bit
720720 // stores. If the target supports neither 32- nor 64-bits, this
721721 // xform is certainly not worth it.
722722 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
723 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), EVT::i32);
724 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), EVT::i32);
723 SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32);
724 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
725725 if (TLI.isBigEndian()) std::swap(Lo, Hi);
726726
727727 Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(),
731731 Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
732732 isVolatile, MinAlign(Alignment, 4U));
733733
734 return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo, Hi);
734 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
735735 }
736736 }
737737 }
776776 case ISD::INTRINSIC_VOID:
777777 case ISD::VAARG:
778778 case ISD::STACKSAVE:
779 Action = TLI.getOperationAction(Node->getOpcode(), EVT::Other);
779 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
780780 break;
781781 case ISD::SINT_TO_FP:
782782 case ISD::UINT_TO_FP:
881881 case ISD::BR_CC:
882882 case ISD::BRCOND:
883883 // Branches tweak the chain to include LastCALLSEQ_END
884 Ops[0] = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Ops[0],
884 Ops[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ops[0],
885885 LastCALLSEQ_END);
886886 Ops[0] = LegalizeOp(Ops[0]);
887887 LastCALLSEQ_END = DAG.getEntryNode();
978978 // Merge in the last call, to ensure that this call start after the last
979979 // call ended.
980980 if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
981 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
981 Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
982982 Tmp1, LastCALLSEQ_END);
983983 Tmp1 = LegalizeOp(Tmp1);
984984 }
10251025 Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
10261026 // Do not try to legalize the target-specific arguments (#1+), except for
10271027 // an optional flag input.
1028 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != EVT::Flag){
1028 if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
10291029 if (Tmp1 != Node->getOperand(0)) {
10301030 SmallVector Ops(Node->op_begin(), Node->op_end());
10311031 Ops[0] = Tmp1;
11211121 // tells the optimizers that those bits are undefined. It would be
11221122 // nice to have an effective generic way of getting these benefits...
11231123 // Until such a way is found, don't insist on promoting i1 here.
1124 (SrcVT != EVT::i1 ||
1125 TLI.getLoadExtAction(ExtType, EVT::i1) == TargetLowering::Promote)) {
1124 (SrcVT != MVT::i1 ||
1125 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
11261126 // Promote to a byte-sized load if not loading an integral number of
11271127 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
11281128 unsigned NewWidth = SrcVT.getStoreSizeInBits();
11881188
11891189 // Build a factor node to remember that this load is independent of the
11901190 // other one.
1191 Ch = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo.getValue(1),
1191 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
11921192 Hi.getValue(1));
11931193
11941194 // Move the top bits to the right place.
12171217
12181218 // Build a factor node to remember that this load is independent of the
12191219 // other one.
1220 Ch = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo.getValue(1),
1220 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
12211221 Hi.getValue(1));
12221222
12231223 // Move the top bits to the right place.
12661266 break;
12671267 case TargetLowering::Expand:
12681268 // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
1269 if (SrcVT == EVT::f32 && Node->getValueType(0) == EVT::f64) {
1269 if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
12701270 SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2, LD->getSrcValue(),
12711271 LD->getSrcValueOffset(),
12721272 LD->isVolatile(), LD->getAlignment());
14151415 }
14161416
14171417 // The order of the stores doesn't matter.
1418 Result = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo, Hi);
1418 Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
14191419 } else {
14201420 if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
14211421 Tmp2 != ST->getBasePtr())
15231523
15241524 SDValue StoreChain;
15251525 if (!Stores.empty()) // Not all undef elements?
1526 StoreChain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
1526 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
15271527 &Stores[0], Stores.size());
15281528 else
15291529 StoreChain = DAG.getEntryNode();
15361536 DebugLoc dl = Node->getDebugLoc();
15371537 SDValue Tmp1 = Node->getOperand(0);
15381538 SDValue Tmp2 = Node->getOperand(1);
1539 assert((Tmp2.getValueType() == EVT::f32 ||
1540 Tmp2.getValueType() == EVT::f64) &&
1539 assert((Tmp2.getValueType() == MVT::f32 ||
1540 Tmp2.getValueType() == MVT::f64) &&
15411541 "Ugly special-cased code!");
15421542 // Get the sign bit of the RHS.
15431543 SDValue SignBit;
1544 EVT IVT = Tmp2.getValueType() == EVT::f64 ? EVT::i64 : EVT::i32;
1544 EVT IVT = Tmp2.getValueType() == MVT::f64 ? MVT::i64 : MVT::i32;
15451545 if (isTypeLegal(IVT)) {
15461546 SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, IVT, Tmp2);
15471547 } else {
15481548 assert(isTypeLegal(TLI.getPointerTy()) &&
1549 (TLI.getPointerTy() == EVT::i32 ||
1550 TLI.getPointerTy() == EVT::i64) &&
1549 (TLI.getPointerTy() == MVT::i32 ||
1550 TLI.getPointerTy() == MVT::i64) &&
15511551 "Legal type for load?!");
15521552 SDValue StackPtr = DAG.CreateStackTemporary(Tmp2.getValueType());
15531553 SDValue StorePtr = StackPtr, LoadPtr = StackPtr;
15541554 SDValue Ch =
15551555 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StorePtr, NULL, 0);
1556 if (Tmp2.getValueType() == EVT::f64 && TLI.isLittleEndian())
1556 if (Tmp2.getValueType() == MVT::f64 && TLI.isLittleEndian())
15571557 LoadPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(),
15581558 LoadPtr, DAG.getIntPtrConstant(4));
15591559 SignBit = DAG.getExtLoad(ISD::SEXTLOAD, dl, TLI.getPointerTy(),
1560 Ch, LoadPtr, NULL, 0, EVT::i32);
1560 Ch, LoadPtr, NULL, 0, MVT::i32);
15611561 }
15621562 SignBit =
15631563 DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()),
15761576 DebugLoc dl = Node->getDebugLoc();
15771577 DwarfWriter *DW = DAG.getDwarfWriter();
15781578 bool useDEBUG_LOC = TLI.isOperationLegalOrCustom(ISD::DEBUG_LOC,
1579 EVT::Other);
1580 bool useLABEL = TLI.isOperationLegalOrCustom(ISD::DBG_LABEL, EVT::Other);
1579 MVT::Other);
1580 bool useLABEL = TLI.isOperationLegalOrCustom(ISD::DBG_LABEL, MVT::Other);
15811581
15821582 const DbgStopPointSDNode *DSP = cast(Node);
15831583 GlobalVariable *CU_GV = cast(DSP->getCompileUnit());
15911591 // A bit self-referential to have DebugLoc on Debug_Loc nodes, but it
15921592 // won't hurt anything.
15931593 if (useDEBUG_LOC) {
1594 return DAG.getNode(ISD::DEBUG_LOC, dl, EVT::Other, Node->getOperand(0),
1595 DAG.getConstant(Line, EVT::i32),
1596 DAG.getConstant(Col, EVT::i32),
1594 return DAG.getNode(ISD::DEBUG_LOC, dl, MVT::Other, Node->getOperand(0),
1595 DAG.getConstant(Line, MVT::i32),
1596 DAG.getConstant(Col, MVT::i32),
15971597 DAG.getSrcValue(CU.getGV()));
15981598 } else {
15991599 unsigned ID = DW->RecordSourceLine(Line, Col, CU);
18851885 RTLIB::Libcall Call_F80,
18861886 RTLIB::Libcall Call_PPCF128) {
18871887 RTLIB::Libcall LC;
1888 switch (Node->getValueType(0).getSimpleVT()) {
1888 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
18891889 default: llvm_unreachable("Unexpected request for libcall!");
1890 case EVT::f32: LC = Call_F32; break;
1891 case EVT::f64: LC = Call_F64; break;
1892 case EVT::f80: LC = Call_F80; break;
1893 case EVT::ppcf128: LC = Call_PPCF128; break;
1890 case MVT::f32: LC = Call_F32; break;
1891 case MVT::f64: LC = Call_F64; break;
1892 case MVT::f80: LC = Call_F80; break;
1893 case MVT::ppcf128: LC = Call_PPCF128; break;
18941894 }
18951895 return ExpandLibCall(LC, Node, false);
18961896 }
19011901 RTLIB::Libcall Call_I64,
19021902 RTLIB::Libcall Call_I128) {
19031903 RTLIB::Libcall LC;
1904 switch (Node->getValueType(0).getSimpleVT()) {
1904 switch (Node->getValueType(0).getSimpleVT().SimpleTy) {
19051905 default: llvm_unreachable("Unexpected request for libcall!");
1906 case EVT::i16: LC = Call_I16; break;
1907 case EVT::i32: LC = Call_I32; break;
1908 case EVT::i64: LC = Call_I64; break;
1909 case EVT::i128: LC = Call_I128; break;
1906 case MVT::i16: LC = Call_I16; break;
1907 case MVT::i32: LC = Call_I32; break;
1908 case MVT::i64: LC = Call_I64; break;
1909 case MVT::i128: LC = Call_I128; break;
19101910 }
19111911 return ExpandLibCall(LC, Node, isSigned);
19121912 }
19191919 SDValue Op0,
19201920 EVT DestVT,
19211921 DebugLoc dl) {
1922 if (Op0.getValueType() == EVT::i32) {
1922 if (Op0.getValueType() == MVT::i32) {
19231923 // simple 32-bit [signed|unsigned] integer to float/double expansion
19241924
19251925 // Get the stack frame index of a 8 byte buffer.
1926 SDValue StackSlot = DAG.CreateStackTemporary(EVT::f64);
1926 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
19271927
19281928 // word offset constant for Hi/Lo address computation
19291929 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
19381938 SDValue Op0Mapped;
19391939 if (isSigned) {
19401940 // constant used to invert sign bit (signed to unsigned mapping)
1941 SDValue SignBit = DAG.getConstant(0x80000000u, EVT::i32);
1942 Op0Mapped = DAG.getNode(ISD::XOR, dl, EVT::i32, Op0, SignBit);
1941 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
1942 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
19431943 } else {
19441944 Op0Mapped = Op0;
19451945 }
19471947 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
19481948 Op0Mapped, Lo, NULL, 0);
19491949 // initial hi portion of constructed double
1950 SDValue InitialHi = DAG.getConstant(0x43300000u, EVT::i32);
1950 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
19511951 // store the hi of the constructed double - biased exponent
19521952 SDValue Store2=DAG.getStore(Store1, dl, InitialHi, Hi, NULL, 0);
19531953 // load the constructed double
1954 SDValue Load = DAG.getLoad(EVT::f64, dl, Store2, StackSlot, NULL, 0);
1954 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, NULL, 0);
19551955 // FP constant to bias correct the final result
19561956 SDValue Bias = DAG.getConstantFP(isSigned ?
19571957 BitsToDouble(0x4330000080000000ULL) :
19581958 BitsToDouble(0x4330000000000000ULL),
1959 EVT::f64);
1959 MVT::f64);
19601960 // subtract the bias
1961 SDValue Sub = DAG.getNode(ISD::FSUB, dl, EVT::f64, Load, Bias);
1961 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
19621962 // final result
19631963 SDValue Result;
19641964 // handle final rounding
1965 if (DestVT == EVT::f64) {
1965 if (DestVT == MVT::f64) {
19661966 // do nothing
19671967 Result = Sub;
1968 } else if (DestVT.bitsLT(EVT::f64)) {
1968 } else if (DestVT.bitsLT(MVT::f64)) {
19691969 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
19701970 DAG.getIntPtrConstant(0));
1971 } else if (DestVT.bitsGT(EVT::f64)) {
1971 } else if (DestVT.bitsGT(MVT::f64)) {
19721972 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
19731973 }
19741974 return Result;
19871987 // as a negative number. To counteract this, the dynamic code adds an
19881988 // offset depending on the data type.
19891989 uint64_t FF;
1990 switch (Op0.getValueType().getSimpleVT()) {
1990 switch (Op0.getValueType().getSimpleVT().SimpleTy) {
19911991 default: llvm_unreachable("Unsupported integer type!");
1992 case EVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
1993 case EVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
1994 case EVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
1995 case EVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
1992 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
1993 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
1994 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
1995 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
19961996 }
19971997 if (TLI.isLittleEndian()) FF <<= 32;
19981998 Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
20022002 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
20032003 Alignment = std::min(Alignment, 4u);
20042004 SDValue FudgeInReg;
2005 if (DestVT == EVT::f32)
2006 FudgeInReg = DAG.getLoad(EVT::f32, dl, DAG.getEntryNode(), CPIdx,
2005 if (DestVT == MVT::f32)
2006 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
20072007 PseudoSourceValue::getConstantPool(), 0,
20082008 false, Alignment);
20092009 else {
20112011 LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
20122012 DAG.getEntryNode(), CPIdx,
20132013 PseudoSourceValue::getConstantPool(), 0,
2014 EVT::f32, false, Alignment));
2014 MVT::f32, false, Alignment));
20152015 }
20162016
20172017 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
20332033
20342034 // Scan for the appropriate larger type to use.
20352035 while (1) {
2036 NewInTy = (EVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
2036 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1);
20372037 assert(NewInTy.isInteger() && "Ran out of possibilities!");
20382038
20392039 // If the target supports SINT_TO_FP of this type, use it.
20752075
20762076 // Scan for the appropriate larger type to use.
20772077 while (1) {
2078 NewOutTy = (EVT::SimpleValueType)(NewOutTy.getSimpleVT()+1);
2078 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1);
20792079 assert(NewOutTy.isInteger() && "Ran out of possibilities!");
20802080
20812081 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
21062106 EVT VT = Op.getValueType();
21072107 EVT SHVT = TLI.getShiftAmountTy();
21082108 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
2109 switch (VT.getSimpleVT()) {
2109 switch (VT.getSimpleVT().SimpleTy) {
21102110 default: llvm_unreachable("Unhandled Expand type in BSWAP!");
2111 case EVT::i16:
2111 case MVT::i16:
21122112 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
21132113 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
21142114 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2115 case EVT::i32:
2115 case MVT::i32:
21162116 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
21172117 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
21182118 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
21222122 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
21232123 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
21242124 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2125 case EVT::i64:
2125 case MVT::i64:
21262126 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
21272127 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
21282128 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
28332833 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
28342834 TLI.getPICJumpTableRelocBase(Table, DAG));
28352835 }
2836 Tmp1 = DAG.getNode(ISD::BRIND, dl, EVT::Other, LD.getValue(1), Addr);
2836 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
28372837 Results.push_back(Tmp1);
28382838 break;
28392839 }
28432843 Tmp1 = Node->getOperand(0);
28442844 Tmp2 = Node->getOperand(1);
28452845 if (Tmp2.getOpcode() == ISD::SETCC) {
2846 Tmp1 = DAG.getNode(ISD::BR_CC, dl, EVT::Other,
2846 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
28472847 Tmp1, Tmp2.getOperand(2),
28482848 Tmp2.getOperand(0), Tmp2.getOperand(1),
28492849 Node->getOperand(2));
28502850 } else {
2851 Tmp1 = DAG.getNode(ISD::BR_CC, dl, EVT::Other, Tmp1,
2851 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
28522852 DAG.getCondCode(ISD::SETNE), Tmp2,
28532853 DAG.getConstant(0, Tmp2.getValueType()),
28542854 Node->getOperand(2));
3030 RTLIB::Libcall Call_F80,
3131 RTLIB::Libcall Call_PPCF128) {
3232 return
33 VT == EVT::f32 ? Call_F32 :
34 VT == EVT::f64 ? Call_F64 :
35 VT == EVT::f80 ? Call_F80 :
36 VT == EVT::ppcf128 ? Call_PPCF128 :
33 VT == MVT::f32 ? Call_F32 :
34 VT == MVT::f64 ? Call_F64 :
35 VT == MVT::f80 ? Call_F80 :
36 VT == MVT::ppcf128 ? Call_PPCF128 :
3737 RTLIB::UNKNOWN_LIBCALL;
3838 }
3939
352352 }
353353
354354 SDValue DAGTypeLegalizer::SoftenFloatRes_FPOWI(SDNode *N) {
355 assert(N->getOperand(1).getValueType() == EVT::i32 &&
355 assert(N->getOperand(1).getValueType() == MVT::i32 &&
356356 "Unsupported power type!");
357357 EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
358358 SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)), N->getOperand(1) };
509509 // a larger type, eg: i8 -> fp. Even if it is legal, no libcall may exactly
510510 // match. Look for an appropriate libcall.
511511 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
512 for (unsigned t = EVT::FIRST_INTEGER_VALUETYPE;
513 t <= EVT::LAST_INTEGER_VALUETYPE && LC == RTLIB::UNKNOWN_LIBCALL; ++t) {
514 NVT = (EVT::SimpleValueType)t;
512 for (unsigned t = MVT::FIRST_INTEGER_VALUETYPE;
513 t <= MVT::LAST_INTEGER_VALUETYPE && LC == RTLIB::UNKNOWN_LIBCALL; ++t) {
514 NVT = (MVT::SimpleValueType)t;
515515 // The source needs to big enough to hold the operand.
516516 if (NVT.bitsGE(SVT))
517517 LC = Signed ? RTLIB::getSINTTOFP(NVT, RVT):RTLIB::getUINTTOFP (NVT, RVT);
575575 SDValue RHSInt = GetSoftenedFloat(NewRHS);
576576 EVT VT = NewLHS.getValueType();
577577
578 assert((VT == EVT::f32 || VT == EVT::f64) && "Unsupported setcc type!");
578 assert((VT == MVT::f32 || VT == MVT::f64) && "Unsupported setcc type!");
579579
580580 // Expand into one or more soft-fp libcall(s).
581581 RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
582582 switch (CCCode) {
583583 case ISD::SETEQ:
584584 case ISD::SETOEQ:
585 LC1 = (VT == EVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
585 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
586586 break;
587587 case ISD::SETNE:
588588 case ISD::SETUNE:
589 LC1 = (VT == EVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
589 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
590590 break;
591591 case ISD::SETGE:
592592 case ISD::SETOGE:
593 LC1 = (VT == EVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
593 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
594594 break;
595595 case ISD::SETLT:
596596 case ISD::SETOLT:
597 LC1 = (VT == EVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
597 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
598598 break;
599599 case ISD::SETLE:
600600 case ISD::SETOLE:
601 LC1 = (VT == EVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
601 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
602602 break;
603603 case ISD::SETGT:
604604 case ISD::SETOGT:
605 LC1 = (VT == EVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
605 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
606606 break;
607607 case ISD::SETUO:
608 LC1 = (VT == EVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
608 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
609609 break;
610610 case ISD::SETO:
611 LC1 = (VT == EVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
611 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
612612 break;
613613 default:
614 LC1 = (VT == EVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
614 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
615615 switch (CCCode) {
616616 case ISD::SETONE:
617617 // SETONE = SETOLT | SETOGT
618 LC1 = (VT == EVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
618 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
619619 // Fallthrough
620620 case ISD::SETUGT:
621 LC2 = (VT == EVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
621 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
622622 break;
623623 case ISD::SETUGE:
624 LC2 = (VT == EVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
624 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
625625 break;
626626 case ISD::SETULT:
627 LC2 = (VT == EVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
627 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
628628 break;
629629 case ISD::SETULE:
630 LC2 = (VT == EVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
630 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
631631 break;
632632 case ISD::SETUEQ:
633 LC2 = (VT == EVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
633 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
634634 break;
635635 default: assert(false && "Do not know how to soften this setcc!");
636636 }
637637 }
638638
639 EVT RetVT = EVT::i32; // FIXME: is this the correct return type?
639 EVT RetVT = MVT::i32; // FIXME: is this the correct return type?
640640 SDValue Ops[2] = { LHSInt, RHSInt };
641641 NewLHS = MakeLibCall(LC1, RetVT, Ops, 2, false/*sign irrelevant*/, dl);
642642 NewRHS = DAG.getConstant(0, RetVT);
840840
841841 void DAGTypeLegalizer::ExpandFloatRes_FABS(SDNode *N, SDValue &Lo,
842842 SDValue &Hi) {
843 assert(N->getValueType(0) == EVT::ppcf128 &&
843 assert(N->getValueType(0) == MVT::ppcf128 &&
844844 "Logic only correct for ppcf128!");
845845 DebugLoc dl = N->getDebugLoc();
846846 SDValue Tmp;
10871087
10881088 void DAGTypeLegalizer::ExpandFloatRes_XINT_TO_FP(SDNode *N, SDValue &Lo,
10891089 SDValue &Hi) {
1090 assert(N->getValueType(0) == EVT::ppcf128 && "Unsupported XINT_TO_FP!");
1090 assert(N->getValueType(0) == MVT::ppcf128 && "Unsupported XINT_TO_FP!");
10911091 EVT VT = N->getValueType(0);
10921092 EVT NVT = TLI.getTypeToTransformTo(VT);
10931093 SDValue Src = N->getOperand(0);
10981098 // First do an SINT_TO_FP, whether the original was signed or unsigned.
10991099 // When promoting partial word types to i32 we must honor the signedness,
11001100 // though.
1101 if (SrcVT.bitsLE(EVT::i32)) {
1101 if (SrcVT.bitsLE(MVT::i32)) {
11021102 // The integer can be represented exactly in an f64.
11031103 Src = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl,
1104 EVT::i32, Src);
1104 MVT::i32, Src);
11051105 Lo = DAG.getConstantFP(APFloat(APInt(NVT.getSizeInBits(), 0)), NVT);
11061106 Hi = DAG.getNode(ISD::SINT_TO_FP, dl, NVT, Src);
11071107 } else {
11081108 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1109 if (SrcVT.bitsLE(EVT::i64)) {
1109 if (SrcVT.bitsLE(MVT::i64)) {
11101110 Src = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl,
1111 EVT::i64, Src);
1111 MVT::i64, Src);
11121112 LC = RTLIB::SINTTOFP_I64_PPCF128;
1113 } else if (SrcVT.bitsLE(EVT::i128)) {
1114 Src = DAG.getNode(ISD::SIGN_EXTEND, dl, EVT::i128, Src);
1113 } else if (SrcVT.bitsLE(MVT::i128)) {
1114 Src = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i128, Src);
11151115 LC = RTLIB::SINTTOFP_I128_PPCF128;
11161116 }
11171117 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XINT_TO_FP!");
11331133 static const uint64_t TwoE128[] = { 0x47f0000000000000LL, 0 };
11341134 const uint64_t *Parts = 0;
11351135
1136 switch (SrcVT.getSimpleVT()) {
1136 switch (SrcVT.getSimpleVT().SimpleTy) {
11371137 default:
11381138 assert(false && "Unsupported UINT_TO_FP!");
1139 case EVT::i32:
1139 case MVT::i32:
11401140 Parts = TwoE32;
11411141 break;
1142 case EVT::i64:
1142 case MVT::i64:
11431143 Parts = TwoE64;
11441144 break;
1145 case EVT::i128:
1145 case MVT::i128:
11461146 Parts = TwoE128;
11471147 break;
11481148 }
11491149
11501150 Lo = DAG.getNode(ISD::FADD, dl, VT, Hi,
11511151 DAG.getConstantFP(APFloat(APInt(128, 2, Parts)),
1152 EVT::ppcf128));
1152 MVT::ppcf128));
11531153 Lo = DAG.getNode(ISD::SELECT_CC, dl, VT, Src, DAG.getConstant(0, SrcVT),
11541154 Lo, Hi, DAG.getCondCode(ISD::SETLT));
11551155 GetPairElements(Lo, Lo, Hi);
12221222 GetExpandedFloat(NewRHS, RHSLo, RHSHi);
12231223
12241224 EVT VT = NewLHS.getValueType();
1225 assert(VT == EVT::ppcf128 && "Unsupported setcc type!");
1225 assert(VT == MVT::ppcf128 && "Unsupported setcc type!");
12261226
12271227 // FIXME: This generated code sucks. We want to generate
12281228 // FCMPU crN, hi1, hi2
12631263 }
12641264
12651265 SDValue DAGTypeLegalizer::ExpandFloatOp_FP_ROUND(SDNode *N) {
1266 assert(N->getOperand(0).getValueType() == EVT::ppcf128 &&
1266 assert(N->getOperand(0).getValueType() == MVT::ppcf128 &&
12671267 "Logic only correct for ppcf128!");
12681268 SDValue Lo, Hi;
12691269 GetExpandedFloat(N->getOperand(0), Lo, Hi);
12781278
12791279 // Expand ppcf128 to i32 by hand for the benefit of llvm-gcc bootstrap on
12801280 // PPC (the libcall is not available). FIXME: Do this in a less hacky way.
1281 if (RVT == EVT::i32) {
1282 assert(N->getOperand(0).getValueType() == EVT::ppcf128 &&
1281 if (RVT == MVT::i32) {
1282 assert(N->getOperand(0).getValueType() == MVT::ppcf128 &&
12831283 "Logic only correct for ppcf128!");
1284 SDValue Res = DAG.getNode(ISD::FP_ROUND_INREG, dl, EVT::ppcf128,
1285 N->getOperand(0), DAG.getValueType(EVT::f64));
1286 Res = DAG.getNode(ISD::FP_ROUND, dl, EVT::f64, Res,
1284 SDValue Res = DAG.getNode(ISD::FP_ROUND_INREG, dl, MVT::ppcf128,
1285 N->getOperand(0), DAG.getValueType(MVT::f64));
1286 Res = DAG.getNode(ISD::FP_ROUND, dl, MVT::f64, Res,
12871287 DAG.getIntPtrConstant(1));
1288 return DAG.getNode(ISD::FP_TO_SINT, dl, EVT::i32, Res);
1288 return DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Res);
12891289 }
12901290
12911291 RTLIB::Libcall LC = RTLIB::getFPTOSINT(N->getOperand(0).getValueType(), RVT);
12991299
13001300 // Expand ppcf128 to i32 by hand for the benefit of llvm-gcc bootstrap on
13011301 // PPC (the libcall is not available). FIXME: Do this in a less hacky way.
1302 if (RVT == EVT::i32) {
1303 assert(N->getOperand(0).getValueType() == EVT::ppcf128 &&
1302 if (RVT == MVT::i32) {
1303 assert(N->getOperand(0).getValueType() == MVT::ppcf128 &&
13041304 "Logic only correct for ppcf128!");
13051305 const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
13061306 APFloat APF = APFloat(APInt(128, 2, TwoE31));
1307 SDValue Tmp = DAG.getConstantFP(APF, EVT::ppcf128);
1307 SDValue Tmp = DAG.getConstantFP(APF, MVT::ppcf128);
13081308 // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
13091309 // FIXME: generated code sucks.
1310 return DAG.getNode(ISD::SELECT_CC, dl, EVT::i32, N->getOperand(0), Tmp,
1311 DAG.getNode(ISD::ADD, dl, EVT::i32,
1312 DAG.getNode(ISD::FP_TO_SINT, dl, EVT::i32,
1310 return DAG.getNode(ISD::SELECT_CC, dl, MVT::i32, N->getOperand(0), Tmp,
1311 DAG.getNode(ISD::ADD, dl, MVT::i32,
1312 DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32,
13131313 DAG.getNode(ISD::FSUB, dl,
1314 EVT::ppcf128,
1314 MVT::ppcf128,
13151315 N->getOperand(0),
13161316 Tmp)),
1317 DAG.getConstant(0x80000000, EVT::i32)),
1317 DAG.getConstant(0x80000000, MVT::i32)),
13181318 DAG.getNode(ISD::FP_TO_SINT, dl,
1319 EVT::i32, N->getOperand(0)),
1319 MVT::i32, N->getOperand(0)),
13201320 DAG.getCondCode(ISD::SETGE));
13211321 }
13221322
717717 assert(OpNo == 1 && "only know how to promote condition");
718718
719719 // Promote all the way up to the canonical SetCC type.
720 EVT SVT = TLI.getSetCCResultType(EVT::Other);
720 EVT SVT = TLI.getSetCCResultType(MVT::Other);
721721 SDValue Cond = PromoteTargetBoolean(N->getOperand(1), SVT);
722722
723723 // The chain (Op#0) and basic block destination (Op#2) are always legal types.
801801 NewOps[0] = N->getOperand(0);
802802 for (unsigned i = 1; i < array_lengthof(NewOps); ++i) {
803803 SDValue Flag = GetPromotedInteger(N->getOperand(i));
804 NewOps[i] = DAG.getZeroExtendInReg(Flag, dl, EVT::i1);
804 NewOps[i] = DAG.getZeroExtendInReg(Flag, dl, MVT::i1);
805805 }
806806 return DAG.UpdateNodeOperands(SDValue (N, 0), NewOps,
807807 array_lengthof(NewOps));
10081008 TLI.isOperationLegalOrCustom(ISD::ADDC,
10091009 TLI.getTypeToExpandTo(NVT))) {
10101010 // Emit this X << 1 as X+X.
1011 SDVTList VTList = DAG.getVTList(NVT, EVT::Flag);
1011 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
10121012 SDValue LoOps[2] = { InL, InL };
10131013 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
10141014 SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
12361236 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
12371237 // them. TODO: Teach operation legalization how to expand unsupported
12381238 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1239 // a carry of type EVT::Flag, but there doesn't seem to be any way to
1239 // a carry of type MVT::Flag, but there doesn't seem to be any way to
12401240 // generate a value of this type in the expanded code sequence.
12411241 bool hasCarry =
12421242 TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
12441244 TLI.getTypeToExpandTo(NVT));
12451245
12461246 if (hasCarry) {
1247 SDVTList VTList = DAG.getVTList(NVT, EVT::Flag);
1247 SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
12481248 if (N->getOpcode() == ISD::ADD) {
12491249 Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
12501250 HiOps[2] = Lo.getValue(1);
12891289 DebugLoc dl = N->getDebugLoc();
12901290 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
12911291 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1292 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), EVT::Flag);
1292 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
12931293 SDValue LoOps[2] = { LHSL, RHSL };
12941294 SDValue HiOps[3] = { LHSH, RHSH };
12951295
13151315 DebugLoc dl = N->getDebugLoc();
13161316 GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
13171317 GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
1318 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), EVT::Flag);
1318 SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
13191319 SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
13201320 SDValue HiOps[3] = { LHSH, RHSH };
13211321
15381538
15391539 // Build a factor node to remember that this load is independent of the
15401540 // other one.
1541 Ch = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo.getValue(1),
1541 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
15421542 Hi.getValue(1));
15431543 } else {
15441544 // Big-endian - high bits are at low addresses. Favor aligned loads at
15641564
15651565 // Build a factor node to remember that this load is independent of the
15661566 // other one.
1567 Ch = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo.getValue(1),
1567 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
15681568 Hi.getValue(1));
15691569
15701570 if (ExcessBits < NVT.getSizeInBits()) {
16721672
16731673 // If nothing else, we can make a libcall.
16741674 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1675 if (VT == EVT::i16)
1675 if (VT == MVT::i16)
16761676 LC = RTLIB::MUL_I16;
1677 else if (VT == EVT::i32)
1677 else if (VT == MVT::i32)
16781678 LC = RTLIB::MUL_I32;
1679 else if (VT == EVT::i64)
1679 else if (VT == MVT::i64)
16801680 LC = RTLIB::MUL_I64;
1681 else if (VT == EVT::i128)
1681 else if (VT == MVT::i128)
16821682 LC = RTLIB::MUL_I128;
16831683 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
16841684
16921692 DebugLoc dl = N->getDebugLoc();
16931693
16941694 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1695 if (VT == EVT::i16)
1695 if (VT == MVT::i16)
16961696 LC = RTLIB::SDIV_I16;
1697 else if (VT == EVT::i32)
1697 else if (VT == MVT::i32)
16981698 LC = RTLIB::SDIV_I32;
1699 else if (VT == EVT::i64)
1699 else if (VT == MVT::i64)
17001700 LC = RTLIB::SDIV_I64;
1701 else if (VT == EVT::i128)
1701 else if (VT == MVT::i128)
17021702 LC = RTLIB::SDIV_I128;