llvm.org GIT mirror llvm / 824dfb1
[AArch64] This is a work in progress to provide a machine description for the Cortex-A53 subtarget in the AArch64 backend. This patch lays the ground work to annotate each AArch64 instruction (no NEON yet) with a list of SchedReadWrite types. The patch also provides the Cortex-A53 processor resources, maps those the the default SchedReadWrites, and provides basic latency. NEON support will be added in a subsequent patch with proper forwarding logic. Verification was done by setting the pre-RA scheduler to linearize to better gauge the effect of the MIScheduler. Even without modeling the forward logic, the results show a modest improvement for Cortex-A53. Reviewers: apazos, mcrosier, atrick Patch by Dave Estes <cestes@codeaurora.org>! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202767 91177308-0d34-0410-b5e6-96231b3b80d8 Chad Rosier 6 years ago
6 changed file(s) with 631 addition(s) and 187 deletion(s). Raw diff Collapse all Expand all
4040
4141 def : Processor<"generic", GenericItineraries, [FeatureFPARMv8, FeatureNEON]>;
4242
43 def : ProcNoItin<"cortex-a53", [FeatureFPARMv8,
44 FeatureNEON,
45 FeatureCrypto]>;
43 def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
44 "Cortex-A53 ARM processors",
45 [FeatureFPARMv8,
46 FeatureNEON,
47 FeatureCrypto]>;
4648
47 def : ProcNoItin<"cortex-a57", [FeatureFPARMv8,
48 FeatureNEON,
49 FeatureCrypto]>;
49 def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
50 "Cortex-A57 ARM processors",
51 [FeatureFPARMv8,
52 FeatureNEON,
53 FeatureCrypto]>;
54
55 def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
56 def : Processor<"cortex-a57", NoItineraries, [ProcA57]>;
5057
5158 //===----------------------------------------------------------------------===//
5259 // Register File Description
349349 outs, (ins exts.GPR:$Rn, GPR32:$Rm, UXTB_operand:$Imm3),
350350 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
351351 [(opfrag exts.ty:$Rn, (shl exts.uxtb, UXTB_operand:$Imm3))],
352 NoItinerary>;
352 NoItinerary>,
353 Sched<[WriteALU, ReadALU, ReadALU]>;
353354 def w_uxth : A64I_addsubext
354355 outs, (ins exts.GPR:$Rn, GPR32:$Rm, UXTH_operand:$Imm3),
355356 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
356357 [(opfrag exts.ty:$Rn, (shl exts.uxth, UXTH_operand:$Imm3))],
357 NoItinerary>;
358 NoItinerary>,
359 Sched<[WriteALU, ReadALU, ReadALU]>;
358360 def w_uxtw : A64I_addsubext
359361 outs, (ins exts.GPR:$Rn, GPR32:$Rm, UXTW_operand:$Imm3),
360362 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
361363 [(opfrag exts.ty:$Rn, (shl exts.uxtw, UXTW_operand:$Imm3))],
362 NoItinerary>;
364 NoItinerary>,
365 Sched<[WriteALU, ReadALU, ReadALU]>;
363366
364367 def w_sxtb : A64I_addsubext
365368 outs, (ins exts.GPR:$Rn, GPR32:$Rm, SXTB_operand:$Imm3),
366369 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
367370 [(opfrag exts.ty:$Rn, (shl exts.sxtb, SXTB_operand:$Imm3))],
368 NoItinerary>;
371 NoItinerary>,
372 Sched<[WriteALU, ReadALU, ReadALU]>;
369373 def w_sxth : A64I_addsubext
370374 outs, (ins exts.GPR:$Rn, GPR32:$Rm, SXTH_operand:$Imm3),
371375 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
372376 [(opfrag exts.ty:$Rn, (shl exts.sxth, SXTH_operand:$Imm3))],
373 NoItinerary>;
377 NoItinerary>,
378 Sched<[WriteALU, ReadALU, ReadALU]>;
374379 def w_sxtw : A64I_addsubext
375380 outs, (ins exts.GPR:$Rn, GPR32:$Rm, SXTW_operand:$Imm3),
376381 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
377382 [(opfrag exts.ty:$Rn, (shl exts.sxtw, SXTW_operand:$Imm3))],
378 NoItinerary>;
383 NoItinerary>,
384 Sched<[WriteALU, ReadALU, ReadALU]>;
379385 }
380386
381387 // These two could be merge in with the above, but their patterns aren't really
387393 (ins GPR64xsp:$Rn, GPR64:$Rm, UXTX_operand:$Imm3),
388394 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
389395 [(opfrag i64:$Rn, (shl i64:$Rm, UXTX_operand:$Imm3))],
390 NoItinerary>;
396 NoItinerary>,
397 Sched<[WriteALU, ReadALU, ReadALU]>;
391398
392399 def x_sxtx : A64I_addsubext<0b1, op, S, 0b00, 0b111,
393400 outs,
394401 (ins GPR64xsp:$Rn, GPR64:$Rm, SXTX_operand:$Imm3),
395402 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
396403 [/* No Pattern: same as uxtx */],
397 NoItinerary>;
404 NoItinerary>,
405 Sched<[WriteALU, ReadALU, ReadALU]>;
398406 }
399407
400408 multiclass addsub_wxtx {
401409 def w_uxtx : A64I_addsubext<0b0, op, S, 0b00, 0b011,
402 outs,
403 (ins GPR32wsp:$Rn, GPR32:$Rm, UXTX_operand:$Imm3),
404 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
405 [/* No pattern: probably same as uxtw */],
406 NoItinerary>;
410 outs, (ins GPR32wsp:$Rn, GPR32:$Rm, UXTX_operand:$Imm3),
411 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
412 [/* No pattern: probably same as uxtw */],
413 NoItinerary>,
414 Sched<[WriteALU, ReadALU, ReadALU]>;
407415
408416 def w_sxtx : A64I_addsubext<0b0, op, S, 0b00, 0b111,
409 outs,
410 (ins GPR32wsp:$Rn, GPR32:$Rm, SXTX_operand:$Imm3),
411 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
412 [/* No Pattern: probably same as uxtw */],
413 NoItinerary>;
417 outs, (ins GPR32wsp:$Rn, GPR32:$Rm, SXTX_operand:$Imm3),
418 !strconcat(asmop, "$Rn, $Rm, $Imm3"),
419 [/* No Pattern: probably same as uxtw */],
420 NoItinerary>,
421 Sched<[WriteALU, ReadALU, ReadALU]>;
414422 }
415423
416424 class SetRD
656664 (ins GPRsp:$Rn, imm_operand:$Imm12),
657665 !strconcat(asmop, "\t$Rd, $Rn, $Imm12"),
658666 [(set Ty:$Rd, (add Ty:$Rn, imm_operand:$Imm12))],
659 NoItinerary>;
667 NoItinerary>,
668 Sched<[WriteALU, ReadALU]>;
660669
661670
662671 // S variants can read SP but would write to ZR
665674 (ins GPRsp:$Rn, imm_operand:$Imm12),
666675 !strconcat(asmop, "s\t$Rd, $Rn, $Imm12"),
667676 [(set Ty:$Rd, (addc Ty:$Rn, imm_operand:$Imm12))],
668 NoItinerary> {
677 NoItinerary>,
678 Sched<[WriteALU, ReadALU]> {
669679 let Defs = [NZCV];
670680 }
671681
677687 !strconcat(cmpasmop, " $Rn, $Imm12"),
678688 [(set NZCV,
679689 (A64cmp Ty:$Rn, cmp_imm_operand:$Imm12))],
680 NoItinerary> {
690 NoItinerary>,
691 Sched<[WriteALU, ReadALU]> {
681692 let Rd = 0b11111;
682693 let Defs = [NZCV];
683694 let isCompare = 1;
739750 // Contains: ADD, ADDS, SUB, SUBS + aliases CMN, CMP, NEG, NEGS
740751
741752 //===-------------------------------
742 // 1. The "shifed register" operands. Shared with logical insts.
753 // 1. The "shifted register" operands. Shared with logical insts.
743754 //===-------------------------------
744755
745756 multiclass shift_operands {
799810 [(set GPR:$Rd, (opfrag ty:$Rn, (shl ty:$Rm,
800811 !cast("lsl_operand_" # ty):$Imm6))
801812 )],
802 NoItinerary>;
813 NoItinerary>,
814 Sched<[WriteALU, ReadALU]>;
803815
804816 def _lsr : A64I_addsubshift
805817 (outs GPR:$Rd),
809821 [(set ty:$Rd, (opfrag ty:$Rn, (srl ty:$Rm,
810822 !cast("lsr_operand_" # ty):$Imm6))
811823 )],
812 NoItinerary>;
824 NoItinerary>,
825 Sched<[WriteALU, ReadALU]>;
813826
814827 def _asr : A64I_addsubshift
815828 (outs GPR:$Rd),
819832 [(set ty:$Rd, (opfrag ty:$Rn, (sra ty:$Rm,
820833 !cast("asr_operand_" # ty):$Imm6))
821834 )],
822 NoItinerary>;
835 NoItinerary>,
836 Sched<[WriteALU, ReadALU]>;
823837 }
824838
825839 def _noshift
905919 [(set NZCV, (opfrag ty:$Rn, (shl ty:$Rm,
906920 !cast("lsl_operand_" # ty):$Imm6))
907921 )],
908 NoItinerary>;
922 NoItinerary>,
923 Sched<[WriteCMP, ReadCMP, ReadCMP]>;
909924
910925 def _lsr : A64I_addsubshift
911926 (outs),
915930 [(set NZCV, (opfrag ty:$Rn, (srl ty:$Rm,
916931 !cast("lsr_operand_" # ty):$Imm6))
917932 )],
918 NoItinerary>;
933 NoItinerary>,
934 Sched<[WriteCMP, ReadCMP, ReadCMP]>;
919935
920936 def _asr : A64I_addsubshift
921937 (outs),
925941 [(set NZCV, (opfrag ty:$Rn, (sra ty:$Rm,
926942 !cast("asr_operand_" # ty):$Imm6))
927943 )],
928 NoItinerary>;
944 NoItinerary>,
945 Sched<[WriteCMP, ReadCMP, ReadCMP]>;
929946 }
930947
931948 def _noshift
952969 def www : A64I_addsubcarry<0b0, op, s, 0b000000,
953970 (outs GPR32:$Rd), (ins GPR32:$Rn, GPR32:$Rm),
954971 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
955 [], NoItinerary>;
972 [], NoItinerary>,
973 Sched<[WriteALU, ReadALU, ReadALU]>;
956974
957975 def xxx : A64I_addsubcarry<0b1, op, s, 0b000000,
958976 (outs GPR64:$Rd), (ins GPR64:$Rn, GPR64:$Rm),
959977 !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
960 [], NoItinerary>;
978 [], NoItinerary>,
979 Sched<[WriteALU, ReadALU, ReadALU]>;
961980 }
962981 }
963982
10431062 def wwii : A64I_bitfield<0b0, opc, 0b0, (outs GPR32:$Rd),
10441063 (ins GPR32:$Rn, bitfield32_imm:$ImmR, bitfield32_imm:$ImmS),
10451064 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1046 [], NoItinerary> {
1065 [], NoItinerary>,
1066 Sched<[WriteALU, ReadALU]> {
10471067 let DecoderMethod = "DecodeBitfieldInstruction";
10481068 }
10491069
10501070 def xxii : A64I_bitfield<0b1, opc, 0b1, (outs GPR64:$Rd),
10511071 (ins GPR64:$Rn, bitfield64_imm:$ImmR, bitfield64_imm:$ImmS),
10521072 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1053 [], NoItinerary> {
1073 [], NoItinerary>,
1074 Sched<[WriteALU, ReadALU]> {
10541075 let DecoderMethod = "DecodeBitfieldInstruction";
10551076 }
10561077 }
10631084 def BFMwwii :
10641085 A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd),
10651086 (ins GPR32:$src, GPR32:$Rn, bitfield32_imm:$ImmR, bitfield32_imm:$ImmS),
1066 "bfm\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
1087 "bfm\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>,
1088 Sched<[WriteALU, ReadALU]> {
10671089 let DecoderMethod = "DecodeBitfieldInstruction";
10681090 let Constraints = "$src = $Rd";
10691091 }
10711093 def BFMxxii :
10721094 A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd),
10731095 (ins GPR64:$src, GPR64:$Rn, bitfield64_imm:$ImmR, bitfield64_imm:$ImmS),
1074 "bfm\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
1096 "bfm\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>,
1097 Sched<[WriteALU, ReadALU]> {
10751098 let DecoderMethod = "DecodeBitfieldInstruction";
10761099 let Constraints = "$src = $Rd";
10771100 }
10931116 : A64I_bitfield
10941117 (outs GPRDest:$Rd), (ins GPR32:$Rn),
10951118 !strconcat(asmop, "\t$Rd, $Rn"),
1096 [(set dty:$Rd, pattern)], NoItinerary> {
1119 [(set dty:$Rd, pattern)], NoItinerary>,
1120 Sched<[WriteALU, ReadALU]> {
10971121 let ImmR = 0b000000;
10981122 let ImmS = imms;
10991123 }
11471171 (outs GPR32:$Rd), (ins GPR32:$Rn, bitfield32_imm:$ImmR),
11481172 !strconcat(asmop, "\t$Rd, $Rn, $ImmR"),
11491173 [(set i32:$Rd, (opnode i32:$Rn, bitfield32_imm:$ImmR))],
1150 NoItinerary> {
1174 NoItinerary>,
1175 Sched<[WriteALU, ReadALU]> {
11511176 let ImmS = 31;
11521177 }
11531178
11551180 (outs GPR64:$Rd), (ins GPR64:$Rn, bitfield64_imm:$ImmR),
11561181 !strconcat(asmop, "\t$Rd, $Rn, $ImmR"),
11571182 [(set i64:$Rd, (opnode i64:$Rn, bitfield64_imm:$ImmR))],
1158 NoItinerary> {
1183 NoItinerary>,
1184 Sched<[WriteALU, ReadALU]> {
11591185 let ImmS = 63;
11601186 }
11611187
11961222 : A64I_bitfield
11971223 "lsl\t$Rd, $Rn, $FullImm",
11981224 [(set ty:$Rd, (shl ty:$Rn, operand:$FullImm))],
1199 NoItinerary> {
1225 NoItinerary>,
1226 Sched<[WriteALU, ReadALU]> {
12001227 bits<12> FullImm;
12011228 let ImmR = FullImm{5-0};
12021229 let ImmS = FullImm{11-6};
12431270 (ins GPR32:$Rn, bitfield32_imm:$ImmR, bfx32_width:$ImmS),
12441271 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
12451272 [(set i32:$Rd, (op i32:$Rn, imm:$ImmR, imm:$ImmS))],
1246 NoItinerary> {
1273 NoItinerary>,
1274 Sched<[WriteALU, ReadALU]> {
12471275 // As above, no disassembler allowed.
12481276 let isAsmParserOnly = 1;
12491277 }
12521280 (ins GPR64:$Rn, bitfield64_imm:$ImmR, bfx64_width:$ImmS),
12531281 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
12541282 [(set i64:$Rd, (op i64:$Rn, imm:$ImmR, imm:$ImmS))],
1255 NoItinerary> {
1283 NoItinerary>,
1284 Sched<[WriteALU, ReadALU]> {
12561285 // As above, no disassembler allowed.
12571286 let isAsmParserOnly = 1;
12581287 }
12631292
12641293 // Again, variants based on BFM modify Rd so need it as an input too.
12651294 def BFXILwwii : A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd),
1266 (ins GPR32:$src, GPR32:$Rn, bitfield32_imm:$ImmR, bfx32_width:$ImmS),
1267 "bfxil\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
1295 (ins GPR32:$src, GPR32:$Rn, bitfield32_imm:$ImmR, bfx32_width:$ImmS),
1296 "bfxil\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>,
1297 Sched<[WriteALU, ReadALU]> {
12681298 // As above, no disassembler allowed.
12691299 let isAsmParserOnly = 1;
12701300 let Constraints = "$src = $Rd";
12711301 }
12721302
12731303 def BFXILxxii : A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd),
1274 (ins GPR64:$src, GPR64:$Rn, bitfield64_imm:$ImmR, bfx64_width:$ImmS),
1275 "bfxil\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
1304 (ins GPR64:$src, GPR64:$Rn, bitfield64_imm:$ImmR, bfx64_width:$ImmS),
1305 "bfxil\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>,
1306 Sched<[WriteALU, ReadALU]> {
12761307 // As above, no disassembler allowed.
12771308 let isAsmParserOnly = 1;
12781309 let Constraints = "$src = $Rd";
13521383 def wwii : A64I_bitfield<0b0, opc, 0b0, (outs GPR32:$Rd),
13531384 (ins GPR32:$Rn, bfi32_lsb:$ImmR, bfi32_width:$ImmS),
13541385 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1355 [], NoItinerary> {
1386 [], NoItinerary>,
1387 Sched<[WriteALU, ReadALU]> {
13561388 // As above, no disassembler allowed.
13571389 let isAsmParserOnly = 1;
13581390 }
13601392 def xxii : A64I_bitfield<0b1, opc, 0b1, (outs GPR64:$Rd),
13611393 (ins GPR64:$Rn, bfi64_lsb:$ImmR, bfi64_width:$ImmS),
13621394 !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
1363 [], NoItinerary> {
1395 [], NoItinerary>,
1396 Sched<[WriteALU, ReadALU]> {
13641397 // As above, no disassembler allowed.
13651398 let isAsmParserOnly = 1;
13661399 }
13721405
13731406 def BFIwwii : A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd),
13741407 (ins GPR32:$src, GPR32:$Rn, bfi32_lsb:$ImmR, bfi32_width:$ImmS),
1375 "bfi\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
1408 "bfi\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>,
1409 Sched<[WriteALU, ReadALU]> {
13761410 // As above, no disassembler allowed.
13771411 let isAsmParserOnly = 1;
13781412 let Constraints = "$src = $Rd";
13801414
13811415 def BFIxxii : A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd),
13821416 (ins GPR64:$src, GPR64:$Rn, bfi64_lsb:$ImmR, bfi64_width:$ImmS),
1383 "bfi\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
1417 "bfi\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>,
1418 Sched<[WriteALU, ReadALU]> {
13841419 // As above, no disassembler allowed.
13851420 let isAsmParserOnly = 1;
13861421 let Constraints = "$src = $Rd";
14171452 (ins GPR64:$Rt, bcc_target:$Label),
14181453 !strconcat(asmop,"\t$Rt, $Label"),
14191454 [(A64br_cc (A64cmp i64:$Rt, 0), SETOP, bb:$Label)],
1420 NoItinerary>;
1455 NoItinerary>,
1456 Sched<[WriteBr, ReadBr]>;
14211457
14221458 def w : A64I_cmpbr<0b0, op,
14231459 (outs),
14241460 (ins GPR32:$Rt, bcc_target:$Label),
14251461 !strconcat(asmop,"\t$Rt, $Label"),
14261462 [(A64br_cc (A64cmp i32:$Rt, 0), SETOP, bb:$Label)],
1427 NoItinerary>;
1463 NoItinerary>,
1464 Sched<[WriteBr, ReadBr]>;
14281465 }
14291466 }
14301467
14551492 def Bcc : A64I_condbr<0b0, 0b0, (outs),
14561493 (ins cond_code:$Cond, bcc_target:$Label),
14571494 "b.$Cond $Label", [(A64br_cc NZCV, (i32 imm:$Cond), bb:$Label)],
1458 NoItinerary> {
1495 NoItinerary>,
1496 Sched<[WriteBr]> {
14591497 let Uses = [NZCV];
14601498 let isBranch = 1;
14611499 let isTerminator = 1;
15011539 : A64I_condcmpimm
15021540 (ins GPR:$Rn, uimm5:$UImm5, uimm4:$NZCVImm, cond_code_op:$Cond),
15031541 !strconcat(asmop, "\t$Rn, $UImm5, $NZCVImm, $Cond"),
1504 [], NoItinerary> {
1542 [], NoItinerary>,
1543 Sched<[WriteCMP, ReadCMP]> {
15051544 let Defs = [NZCV];
15061545 }
15071546
15671606 (ins GPR32:$Rn, GPR32:$Rm, cond_code_op:$Cond),
15681607 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Cond"),
15691608 [(set i32:$Rd, (select i32:$Rn, i32:$Rm))],
1570 NoItinerary>;
1609 NoItinerary>,
1610 Sched<[WriteCMP, ReadCMP]>;
15711611
15721612
15731613 def xxxc : A64I_condsel<0b1, op, 0b0, op2,
15751615 (ins GPR64:$Rn, GPR64:$Rm, cond_code_op:$Cond),
15761616 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Cond"),
15771617 [(set i64:$Rd, (select i64:$Rn, i64:$Rm))],
1578 NoItinerary>;
1618 NoItinerary>,
1619 Sched<[WriteCMP, ReadCMP]>;
15791620 }
15801621 }
15811622
16851726 (outs GPRrc:$Rd),
16861727 (ins GPRrc:$Rn),
16871728 patterns,
1688 itin>;
1729 itin>,
1730 Sched<[WriteALU, ReadALU]>;
16891731
16901732 multiclass A64I_dp_1src opcode, string asmop> {
16911733 let hasSideEffects = 0 in {
17411783 (outs GPRsp:$Rd),
17421784 (ins GPRsp:$Rn, GPRsp:$Rm),
17431785 patterns,
1744 itin>;
1786 itin>,
1787 Sched<[WriteALU, ReadALU, ReadALU]>;
17451788
17461789 multiclass dp_2src_crc {
17471790 def B_www : dp_2src_impl<0b0, {0, 1, 0, c, 0, 0},
17921835 defm CRC32 : dp_2src_crc<0b0, "crc32">;
17931836 defm CRC32C : dp_2src_crc<0b1, "crc32c">;
17941837
1795 defm UDIV : dp_2src<0b000010, "udiv", udiv>;
1796 defm SDIV : dp_2src<0b000011, "sdiv", sdiv>;
1797
1798 defm LSLV : dp_2src_zext<0b001000, "lsl", shl>;
1799 defm LSRV : dp_2src_zext<0b001001, "lsr", srl>;
1800 defm ASRV : dp_2src_zext<0b001010, "asr", sra>;
1801 defm RORV : dp_2src_zext<0b001011, "ror", rotr>;
1838 let SchedRW = [WriteDiv, ReadDiv, ReadDiv] in {
1839 defm UDIV : dp_2src<0b000010, "udiv", udiv>;
1840 defm SDIV : dp_2src<0b000011, "sdiv", sdiv>;
1841 }
1842
1843 let SchedRW = [WriteALUs, ReadALU, ReadALU] in {
1844 defm LSLV : dp_2src_zext<0b001000, "lsl", shl>;
1845 defm LSRV : dp_2src_zext<0b001001, "lsr", srl>;
1846 defm ASRV : dp_2src_zext<0b001010, "asr", sra>;
1847 defm RORV : dp_2src_zext<0b001011, "ror", rotr>;
1848 }
18021849
18031850 // Extra patterns for an incoming 64-bit value for a 32-bit
18041851 // operation. Since the LLVM operations are undefined (as in C) if the
18311878 : A64I_dp3
18321879 (outs AccReg:$Rd), (ins SrcReg:$Rn, SrcReg:$Rm, AccReg:$Ra),
18331880 !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Ra"),
1834 [(set AccTy:$Rd, pattern)], NoItinerary> {
1881 [(set AccTy:$Rd, pattern)], NoItinerary>,
1882 Sched<[WriteMAC, ReadMAC, ReadMAC, ReadMAC]> {
18351883 RegisterClass AccGPR = AccReg;
18361884 RegisterClass SrcGPR = SrcReg;
18371885 }
18611909 (ins GPR64:$Rn, GPR64:$Rm),
18621910 "umulh\t$Rd, $Rn, $Rm",
18631911 [(set i64:$Rd, (mulhu i64:$Rn, i64:$Rm))],
1864 NoItinerary>;
1912 NoItinerary>,
1913 Sched<[WriteMAC, ReadMAC, ReadMAC]>;
18651914
18661915 def SMULHxxx : A64I_dp3<0b1, 0b000100, (outs GPR64:$Rd),
18671916 (ins GPR64:$Rn, GPR64:$Rm),
18681917 "smulh\t$Rd, $Rn, $Rm",
18691918 [(set i64:$Rd, (mulhs i64:$Rn, i64:$Rm))],
1870 NoItinerary>;
1919 NoItinerary>,
1920 Sched<[WriteMAC, ReadMAC, ReadMAC]>;
18711921 }
18721922
18731923 multiclass A64I_dp3_3operand
19151965
19161966 class A64I_exceptImpl opc, bits<2> ll, string asmop>
19171967 : A64I_exception
1918 !strconcat(asmop, "\t$UImm16"), [], NoItinerary> {
1968 !strconcat(asmop, "\t$UImm16"), [], NoItinerary>,
1969 Sched<[WriteBr]> {
19191970 let isBranch = 1;
19201971 let isTerminator = 1;
19211972 }
19461997 "extr\t$Rd, $Rn, $Rm, $LSB",
19471998 [(set i32:$Rd,
19481999 (A64Extr i32:$Rn, i32:$Rm, imm:$LSB))],
1949 NoItinerary>;
2000 NoItinerary>,
2001 Sched<[WriteALU, ReadALU, ReadALU]>;
19502002 def EXTRxxxi : A64I_extract<0b1, 0b000, 0b1,
19512003 (outs GPR64:$Rd),
19522004 (ins GPR64:$Rn, GPR64:$Rm, bitfield64_imm:$LSB),
19532005 "extr\t$Rd, $Rn, $Rm, $LSB",
19542006 [(set i64:$Rd,
19552007 (A64Extr i64:$Rn, i64:$Rm, imm:$LSB))],
1956 NoItinerary>;
2008 NoItinerary>,
2009 Sched<[WriteALU, ReadALU, ReadALU]>;
19572010
19582011 def : InstAlias<"ror $Rd, $Rs, $LSB",
19592012 (EXTRwwwi GPR32:$Rd, GPR32:$Rs, GPR32:$Rs, bitfield32_imm:$LSB)>;
20002053 multiclass A64I_fpcmpSignal type, bit imm, dag ins, dag pattern> {
20012054 def _quiet : A64I_fpcmp<0b0, 0b0, type, 0b00, {0b0, imm, 0b0, 0b0, 0b0},
20022055 (outs), ins, "fcmp\t$Rn, $Rm", [pattern],
2003 NoItinerary> {
2056 NoItinerary>,
2057 Sched<[WriteFPALU, ReadFPALU, ReadFPALU]> {
20042058 let Defs = [NZCV];
20052059 }
20062060
20072061 def _sig : A64I_fpcmp<0b0, 0b0, type, 0b00, {0b1, imm, 0b0, 0b0, 0b0},
2008 (outs), ins, "fcmpe\t$Rn, $Rm", [], NoItinerary> {
2062 (outs), ins, "fcmpe\t$Rn, $Rm", [], NoItinerary>,
2063 Sched<[WriteFPALU, ReadFPALU, ReadFPALU]> {
20092064 let Defs = [NZCV];
20102065 }
20112066 }
20342089 (outs),
20352090 (ins FPR:$Rn, FPR:$Rm, uimm4:$NZCVImm, cond_code_op:$Cond),
20362091 !strconcat(asmop, "\t$Rn, $Rm, $NZCVImm, $Cond"),
2037 [], NoItinerary> {
2092 [], NoItinerary>,
2093 Sched<[WriteFPALU, ReadFPALU, ReadFPALU]> {
20382094 let Defs = [NZCV];
20392095 }
20402096
20522108 def FCSELsssc : A64I_fpcondsel<0b0, 0b0, 0b00, (outs FPR32:$Rd),
20532109 (ins FPR32:$Rn, FPR32:$Rm, cond_code_op:$Cond),
20542110 "fcsel\t$Rd, $Rn, $Rm, $Cond",
2055 [(set f32:$Rd,
2111 [(set f32:$Rd,
20562112 (simple_select f32:$Rn, f32:$Rm))],
2057 NoItinerary>;
2113 NoItinerary>,
2114 Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
20582115
20592116
20602117 def FCSELdddc : A64I_fpcondsel<0b0, 0b0, 0b01, (outs FPR64:$Rd),
20622119 "fcsel\t$Rd, $Rn, $Rm, $Cond",
20632120 [(set f64:$Rd,
20642121 (simple_select f64:$Rn, f64:$Rm))],
2065 NoItinerary>;
2122 NoItinerary>,
2123 Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
20662124 }
20672125
20682126 //===----------------------------------------------------------------------===//
20802138 def ss : A64I_fpdp1<0b0, 0b0, 0b00, opcode, (outs FPR32:$Rd), (ins FPR32:$Rn),
20812139 !strconcat(asmstr, "\t$Rd, $Rn"),
20822140 [(set f32:$Rd, (opnode f32:$Rn))],
2083 NoItinerary>;
2141 NoItinerary>,
2142 Sched<[WriteFPALU, ReadFPALU]>;
20842143
20852144 def dd : A64I_fpdp1<0b0, 0b0, 0b01, opcode, (outs FPR64:$Rd), (ins FPR64:$Rn),
20862145 !strconcat(asmstr, "\t$Rd, $Rn"),
20872146 [(set f64:$Rd, (opnode f64:$Rn))],
2088 NoItinerary>;
2147 NoItinerary>,
2148 Sched<[WriteFPALU, ReadFPALU]>;
20892149 }
20902150
20912151 defm FMOV : A64I_fpdp1sizes<0b000000, "fmov">;
20922152 defm FABS : A64I_fpdp1sizes<0b000001, "fabs", fabs>;
20932153 defm FNEG : A64I_fpdp1sizes<0b000010, "fneg", fneg>;
2094 defm FSQRT : A64I_fpdp1sizes<0b000011, "fsqrt", fsqrt>;
2154 let SchedRW = [WriteFPSqrt, ReadFPSqrt] in {
2155 defm FSQRT : A64I_fpdp1sizes<0b000011, "fsqrt", fsqrt>;
2156 }
20952157
20962158 defm FRINTN : A64I_fpdp1sizes<0b001000, "frintn">;
20972159 defm FRINTP : A64I_fpdp1sizes<0b001001, "frintp", fceil>;
21202182 {0,0,0,1, DestReg.t1, DestReg.t0},
21212183 (outs DestReg.Class:$Rd), (ins SrcReg.Class:$Rn),
21222184 "fcvt\t$Rd, $Rn",
2123 [(set DestReg.VT:$Rd, (opnode SrcReg.VT:$Rn))], NoItinerary>;
2185 [(set DestReg.VT:$Rd, (opnode SrcReg.VT:$Rn))], NoItinerary>,
2186 Sched<[WriteFPALU, ReadFPALU]>;
21242187
21252188 def FCVTds : A64I_fpdp1_fcvt;
21262189 def FCVThs : A64I_fpdp1_fcvt;
21452208 (ins FPR32:$Rn, FPR32:$Rm),
21462209 !strconcat(asmstr, "\t$Rd, $Rn, $Rm"),
21472210 [(set f32:$Rd, (opnode f32:$Rn, f32:$Rm))],
2148 NoItinerary>;
2211 NoItinerary>,
2212 Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
21492213
21502214 def ddd : A64I_fpdp2<0b0, 0b0, 0b01, opcode,
21512215 (outs FPR64:$Rd),
21522216 (ins FPR64:$Rn, FPR64:$Rm),
21532217 !strconcat(asmstr, "\t$Rd, $Rn, $Rm"),
21542218 [(set f64:$Rd, (opnode f64:$Rn, f64:$Rm))],
2155 NoItinerary>;
2219 NoItinerary>,
2220 Sched<[WriteFPALU, ReadFPALU, ReadFPALU]>;
21562221 }
21572222
21582223 let isCommutable = 1 in {
2159 defm FMUL : A64I_fpdp2sizes<0b0000, "fmul", fmul>;
2224 let SchedRW = [WriteFPMul, ReadFPMul, ReadFPMul] in {
2225 defm FMUL : A64I_fpdp2sizes<0b0000, "fmul", fmul>;
2226 }
21602227 defm FADD : A64I_fpdp2sizes<0b0010, "fadd", fadd>;
21612228
21622229 // No patterns for these.
21652232 defm FMAXNM : A64I_fpdp2sizes<0b0110, "fmaxnm", FPNoBinop>;
21662233 defm FMINNM : A64I_fpdp2sizes<0b0111, "fminnm", FPNoBinop>;
21672234
2168 defm FNMUL : A64I_fpdp2sizes<0b1000, "fnmul",
2169 PatFrag<(ops node:$lhs, node:$rhs),
2170 (fneg (fmul node:$lhs, node:$rhs))> >;
2171 }
2172
2173 defm FDIV : A64I_fpdp2sizes<0b0001, "fdiv", fdiv>;
2235 let SchedRW = [WriteFPMul, ReadFPMul, ReadFPMul] in {
2236 defm FNMUL : A64I_fpdp2sizes<0b1000, "fnmul",
2237 PatFrag<(ops node:$lhs, node:$rhs),
2238 (fneg (fmul node:$lhs, node:$rhs))> >;
2239 }
2240 }
2241
2242 let SchedRW = [WriteFPDiv, ReadFPDiv, ReadFPDiv] in {
2243 defm FDIV : A64I_fpdp2sizes<0b0001, "fdiv", fdiv>;
2244 }
21742245 defm FSUB : A64I_fpdp2sizes<0b0011, "fsub", fsub>;
21752246
21762247 //===----------------------------------------------------------------------===//
21912262 (ins FPR:$Rn, FPR:$Rm, FPR:$Ra),
21922263 !strconcat(asmop,"\t$Rd, $Rn, $Rm, $Ra"),
21932264 [(set VT:$Rd, (fmakind VT:$Rn, VT:$Rm, VT:$Ra))],
2194 NoItinerary>;
2265 NoItinerary>,
2266 Sched<[WriteFPMAC, ReadFPMAC, ReadFPMAC, ReadFPMAC]>;
21952267
21962268 def FMADDssss : A64I_fpdp3Impl<"fmadd", FPR32, f32, 0b00, 0b0, 0b0, fma>;
21972269 def FMSUBssss : A64I_fpdp3Impl<"fmsub", FPR32, f32, 0b00, 0b0, 0b1, fmsub>;
22702342 // worth going for a multiclass here. Oh well.
22712343
22722344 class A64I_fptofix type, bits<3> opcode,
2273 RegisterClass GPR, RegisterClass FPR,
2274 ValueType DstTy, ValueType SrcTy,
2345 RegisterClass GPR, RegisterClass FPR,
2346 ValueType DstTy, ValueType SrcTy,
22752347 Operand scale_op, string asmop, SDNode cvtop>
22762348 : A64I_fpfixed
22772349 (outs GPR:$Rd), (ins FPR:$Rn, scale_op:$Scale),
22782350 !strconcat(asmop, "\t$Rd, $Rn, $Scale"),
22792351 [(set DstTy:$Rd, (cvtop (fmul SrcTy:$Rn, scale_op:$Scale)))],
2280 NoItinerary>;
2352 NoItinerary>,
2353 Sched<[WriteFPALU, ReadFPALU]>;
22812354
22822355 def FCVTZSwsi : A64I_fptofix<0b0, 0b00, 0b000, GPR32, FPR32, i32, f32,
22832356 cvtfix_i32_op, "fcvtzs", fp_to_sint>;
23062379 (outs FPR:$Rd), (ins GPR:$Rn, scale_op:$Scale),
23072380 !strconcat(asmop, "\t$Rd, $Rn, $Scale"),
23082381 [(set DstTy:$Rd, (fdiv (cvtop SrcTy:$Rn), scale_op:$Scale))],
2309 NoItinerary>;
2382 NoItinerary>,
2383 Sched<[WriteFPALU, ReadFPALU]>;
23102384
23112385 def SCVTFswi : A64I_fixtofp<0b0, 0b00, 0b010, FPR32, GPR32, f32, i32,
23122386 cvtfix_i32_op, "scvtf", sint_to_fp>;
23332407 class A64I_fpintI type, bits<2> rmode, bits<3> opcode,
23342408 RegisterClass DestPR, RegisterClass SrcPR, string asmop>
23352409 : A64I_fpint
2336 !strconcat(asmop, "\t$Rd, $Rn"), [], NoItinerary>;
2410 !strconcat(asmop, "\t$Rd, $Rn"), [], NoItinerary>,
2411 Sched<[WriteFPALU, ReadFPALU]>;
23372412
23382413 multiclass A64I_fptointRM rmode, bit o2, string asmop> {
23392414 def Sws : A64I_fpintI<0b0, 0b00, rmode, {o2, 0, 0},
24192494 let DecoderMethod = "DecodeFMOVLaneInstruction" in {
24202495 def FMOVxv : A64I_fpint<0b1, 0b0, 0b10, 0b01, 0b110,
24212496 (outs GPR64:$Rd), (ins VPR128:$Rn, lane1:$Lane),
2422 "fmov\t$Rd, $Rn.d[$Lane]", [], NoItinerary>;
2497 "fmov\t$Rd, $Rn.d[$Lane]", [], NoItinerary>,
2498 Sched<[WriteFPALU, ReadFPALU]>;
24232499
24242500 def FMOVvx : A64I_fpint<0b1, 0b0, 0b10, 0b01, 0b111,
24252501 (outs VPR128:$Rd), (ins GPR64:$Rn, lane1:$Lane),
2426 "fmov\t$Rd.d[$Lane], $Rn", [], NoItinerary>;
2502 "fmov\t$Rd.d[$Lane], $Rn", [], NoItinerary>,
2503 Sched<[WriteFPALU, ReadFPALU]>;
24272504 }
24282505
24292506 let Predicates = [HasFPARMv8] in {
24702547 (ins fmov_operand:$Imm8),
24712548 "fmov\t$Rd, $Imm8",
24722549 [(set VT:$Rd, fmov_operand:$Imm8)],
2473 NoItinerary>;
2550 NoItinerary>,
2551 Sched<[WriteFPALU]>;
24742552
24752553 def FMOVsi : A64I_fpimm_impl<0b00, FPR32, f32, fmov32_operand>;
24762554 def FMOVdi : A64I_fpimm_impl<0b01, FPR64, f64, fmov64_operand>;
25192597 class A64I_LDRlitSimple opc, bit v, RegisterClass OutReg,
25202598 list patterns = []>
25212599 : A64I_LDRlit
2522 "ldr\t$Rt, $Imm19", patterns, NoItinerary>;
2600 "ldr\t$Rt, $Imm19", patterns, NoItinerary>,
2601 Sched<[WriteLd]>;
25232602
25242603 let mayLoad = 1 in {
25252604 def LDRw_lit : A64I_LDRlitSimple<0b00, 0b0, GPR32>;
25402619 (outs GPR64:$Rt),
25412620 (ins ldrlit_label:$Imm19),
25422621 "ldrsw\t$Rt, $Imm19",
2543 [], NoItinerary>;
2622 [], NoItinerary>,
2623 Sched<[WriteLd]>;
25442624
25452625 def PRFM_lit : A64I_LDRlit<0b11, 0b0,
25462626 (outs), (ins prefetch_op:$Rt, ldrlit_label:$Imm19),
25472627 "prfm\t$Rt, $Imm19",
2548 [], NoItinerary>;
2628 [], NoItinerary>,
2629 Sched<[WriteLd]>;
25492630 }
25502631
25512632 //===----------------------------------------------------------------------===//
26372718 multiclass A64I_LRex opcode> {
26382719 def _byte: A64I_LRexs_impl<0b00, opcode, !strconcat(asmstr, "b"),
26392720 (outs GPR32:$Rt), (ins GPR64xsp0:$Rn),
2640 [], NoItinerary>;
2721 [], NoItinerary>,
2722 Sched<[WriteLd]>;
26412723
26422724 def _hword: A64I_LRexs_impl<0b01, opcode, !strconcat(asmstr, "h"),
26432725 (outs GPR32:$Rt), (ins GPR64xsp0:$Rn),
2644 [], NoItinerary>;
2726 [], NoItinerary>,
2727 Sched<[WriteLd]>;
26452728
26462729 def _word: A64I_LRexs_impl<0b10, opcode, asmstr,
26472730 (outs GPR32:$Rt), (ins GPR64xsp0:$Rn),
2648 [], NoItinerary>;
2731 [], NoItinerary>,
2732 Sched<[WriteLd]>;
26492733
26502734 def _dword: A64I_LRexs_impl<0b11, opcode, asmstr,
26512735 (outs GPR64:$Rt), (ins GPR64xsp0:$Rn),
2652 [], NoItinerary>;
2736 [], NoItinerary>,
2737 Sched<[WriteLd]>;
26532738 }
26542739
26552740 defm LDXR : A64I_LRex<"ldxr", 0b000>;
27752860 def _word: A64I_LPexs_impl<0b10, opcode, asmstr,
27762861 (outs GPR32:$Rt, GPR32:$Rt2),
27772862 (ins GPR64xsp0:$Rn),
2778 [], NoItinerary>;
2863 [], NoItinerary>,
2864 Sched<[WriteLd]>;
27792865
27802866 def _dword: A64I_LPexs_impl<0b11, opcode, asmstr,
27812867 (outs GPR64:$Rt, GPR64:$Rt2),
27822868 (ins GPR64xsp0:$Rn),
2783 [], NoItinerary>;
2869 [], NoItinerary>,
2870 Sched<[WriteLd]>;
27842871 }
27852872
27862873 defm LDXP : A64I_LPex<"ldxp", 0b010>;
30033090 def _LDR : A64I_LSunsigimm
30043091 (outs GPR:$Rt), (ins GPR64xsp:$Rn, params.uimm12:$UImm12),
30053092 "ldr" # asmsuffix # "\t$Rt, [$Rn, $UImm12]",
3006 [], NoItinerary> {
3093 [], NoItinerary>,
3094 Sched<[WriteLd, ReadLd]> {
30073095 let mayLoad = 1;
30083096 }
30093097 def : InstAlias<"ldr" # asmsuffix # " $Rt, [$Rn]",
30153103 (outs GPR:$Rt),
30163104 (ins GPR64xsp:$Rn, GPR32:$Rm, params.regextWm:$Ext),
30173105 "ldr" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]",
3018 [], NoItinerary>;
3106 [], NoItinerary>,
3107 Sched<[WriteLd, ReadLd, ReadLd]>;
30193108
30203109 def _Xm_RegOffset_LDR : A64I_LSregoff
30213110 (outs GPR:$Rt),
30223111 (ins GPR64xsp:$Rn, GPR64:$Rm, params.regextXm:$Ext),
30233112 "ldr" # asmsuffix # "\t$Rt, [$Rn, $Rm, $Ext]",
3024 [], NoItinerary>;
3113 [], NoItinerary>,
3114 Sched<[WriteLd, ReadLd, ReadLd]>;
30253115 }
30263116 def : InstAlias<"ldr" # asmsuffix # " $Rt, [$Rn, $Rm]",
30273117 (!cast(prefix # "_Xm_RegOffset_LDR") GPR:$Rt, GPR64xsp:$Rn,
30573147 def _LDUR : A64I_LSunalimm
30583148 (outs GPR:$Rt), (ins GPR64xsp:$Rn, simm9:$SImm9),
30593149 "ldur" # asmsuffix # "\t$Rt, [$Rn, $SImm9]",
3060 [], NoItinerary> {
3150 [], NoItinerary>,
3151 Sched<[WriteLd, ReadLd]> {
30613152 let mayLoad = 1;
30623153 }
30633154 def : InstAlias<"ldur" # asmsuffix # " $Rt, [$Rn]",
30803171 (outs GPR:$Rt, GPR64xsp:$Rn_wb),
30813172 (ins GPR64xsp:$Rn, simm9:$SImm9),
30823173 "ldr" # asmsuffix # "\t$Rt, [$Rn], $SImm9",
3083 [], NoItinerary> {
3174 [], NoItinerary>,
3175 Sched<[WriteLd, ReadLd]> {
30843176 let mayLoad = 1;
30853177 let Constraints = "$Rn = $Rn_wb";
30863178 let DecoderMethod = "DecodeSingleIndexedInstruction";
31033195 (outs GPR:$Rt, GPR64xsp:$Rn_wb),
31043196 (ins GPR64xsp:$Rn, simm9:$SImm9),
31053197 "ldr" # asmsuffix # "\t$Rt, [$Rn, $SImm9]!",
3106 [], NoItinerary> {
3198 [], NoItinerary>,
3199 Sched<[WriteLd, ReadLd]> {
31073200 let mayLoad = 1;
31083201 let Constraints = "$Rn = $Rn_wb";
31093202 let DecoderMethod = "DecodeSingleIndexedInstruction";
31633256 (outs GPR32:$Rt),
31643257 (ins GPR64xsp:$Rn, params.uimm12:$UImm12),
31653258 "ldrs" # asmopcode # "\t$Rt, [$Rn, $UImm12]",
3166 [], NoItinerary> {
3259 [], NoItinerary>,
3260 Sched<[WriteLd, ReadLd]> {
31673261 let mayLoad = 1;
31683262 }
31693263 def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn]",
31733267 (outs GPR64:$Rt),
31743268 (ins GPR64xsp:$Rn, params.uimm12:$UImm12),
31753269 "ldrs" # asmopcode # "\t$Rt, [$Rn, $UImm12]",
3176 [], NoItinerary> {
3270 [], NoItinerary>,
3271 Sched<[WriteLd, ReadLd]> {
31773272 let mayLoad = 1;
31783273 }
31793274 def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn]",
31853280 (outs GPR32:$Rt),
31863281 (ins GPR64xsp:$Rn, GPR32:$Rm, params.regextWm:$Ext),
31873282 "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]",
3188 [], NoItinerary>;
3283 [], NoItinerary>,
3284 Sched<[WriteLd, ReadLd, ReadLd]>;
31893285
31903286 def w_Xm_RegOffset : A64I_LSregoff
31913287 (outs GPR32:$Rt),
31923288 (ins GPR64xsp:$Rn, GPR64:$Rm, params.regextXm:$Ext),
31933289 "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]",
3194 [], NoItinerary>;
3290 [], NoItinerary>,
3291 Sched<[WriteLd, ReadLd, ReadLd]>;
31953292
31963293 def x_Wm_RegOffset : A64I_LSregoff
31973294 (outs GPR64:$Rt),
31983295 (ins GPR64xsp:$Rn, GPR32:$Rm, params.regextWm:$Ext),
31993296 "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]",
3200 [], NoItinerary>;
3297 [], NoItinerary>,
3298 Sched<[WriteLd, ReadLd, ReadLd]>;
32013299
32023300 def x_Xm_RegOffset : A64I_LSregoff
32033301 (outs GPR64:$Rt),
32043302 (ins GPR64xsp:$Rn, GPR64:$Rm, params.regextXm:$Ext),
32053303 "ldrs" # asmopcode # "\t$Rt, [$Rn, $Rm, $Ext]",
3206 [], NoItinerary>;
3304 [], NoItinerary>,
3305 Sched<[WriteLd, ReadLd, ReadLd]>;
32073306 }
32083307 def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn, $Rm]",
32093308 (!cast(prefix # "w_Xm_RegOffset") GPR32:$Rt, GPR64xsp:$Rn,
32203319 (outs GPR32:$Rt),
32213320 (ins GPR64xsp:$Rn, simm9:$SImm9),
32223321 "ldurs" # asmopcode # "\t$Rt, [$Rn, $SImm9]",
3223 [], NoItinerary>;
3322 [], NoItinerary>,
3323 Sched<[WriteLd, ReadLd]>;
32243324
32253325 def x_U : A64I_LSunalimm
32263326 (outs GPR64:$Rt),
32273327 (ins GPR64xsp:$Rn, simm9:$SImm9),
32283328 "ldurs" # asmopcode # "\t$Rt, [$Rn, $SImm9]",
3229 [], NoItinerary>;
3329 [], NoItinerary>,
3330 Sched<[WriteLd, ReadLd]>;
32303331
32313332
32323333 // Post-indexed
32343335 (outs GPR32:$Rt, GPR64xsp:$Rn_wb),
32353336 (ins GPR64xsp:$Rn, simm9:$SImm9),
32363337 "ldrs" # asmopcode # "\t$Rt, [$Rn], $SImm9",
3237 [], NoItinerary> {
3338 [], NoItinerary>,
3339 Sched<[WriteLd, ReadLd]> {
32383340 let Constraints = "$Rn = $Rn_wb";
32393341 let DecoderMethod = "DecodeSingleIndexedInstruction";
32403342 }
32433345 (outs GPR64:$Rt, GPR64xsp:$Rn_wb),
32443346 (ins GPR64xsp:$Rn, simm9:$SImm9),
32453347 "ldrs" # asmopcode # "\t$Rt, [$Rn], $SImm9",
3246 [], NoItinerary> {
3348 [], NoItinerary>,
3349 Sched<[WriteLd, ReadLd]> {
32473350 let Constraints = "$Rn = $Rn_wb";
32483351 let DecoderMethod = "DecodeSingleIndexedInstruction";
32493352 }
32533356 (outs GPR32:$Rt, GPR64xsp:$Rn_wb),
32543357 (ins GPR64xsp:$Rn, simm9:$SImm9),
32553358 "ldrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]!",
3256 [], NoItinerary> {
3359 [], NoItinerary>,
3360 Sched<[WriteLd, ReadLd]> {
32573361 let Constraints = "$Rn = $Rn_wb";
32583362 let DecoderMethod = "DecodeSingleIndexedInstruction";
32593363 }
32623366 (outs GPR64:$Rt, GPR64xsp:$Rn_wb),
32633367 (ins GPR64xsp:$Rn, simm9:$SImm9),
32643368 "ldrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]!",
3265 [], NoItinerary> {
3369 [], NoItinerary>,
3370 Sched<[WriteLd, ReadLd]> {
32663371 let Constraints = "$Rn = $Rn_wb";
32673372 let DecoderMethod = "DecodeSingleIndexedInstruction";
32683373 }
32803385 (outs GPR64:$Rt),
32813386 (ins GPR64xsp:$Rn, word_uimm12:$UImm12),
32823387 "ldrsw\t$Rt, [$Rn, $UImm12]",
3283 [], NoItinerary> {
3388 [], NoItinerary>,
3389 Sched<[WriteLd, ReadLd]> {
32843390 let mayLoad = 1;
32853391 }
32863392 def : InstAlias<"ldrsw $Rt, [$Rn]", (LDRSWx GPR64:$Rt, GPR64xsp:$Rn, 0)>;
32903396 (outs GPR64:$Rt),
32913397 (ins GPR64xsp:$Rn, GPR32:$Rm, word_Wm_regext:$Ext),
32923398 "ldrsw\t$Rt, [$Rn, $Rm, $Ext]",
3293 [], NoItinerary>;
3399 [], NoItinerary>,
3400 Sched<[WriteLd, ReadLd, ReadLd]>;
32943401
32953402 def LDRSWx_Xm_RegOffset : A64I_LSregoff<0b10, 0b0, 0b10, 0b1,
32963403 (outs GPR64:$Rt),
32973404 (ins GPR64xsp:$Rn, GPR64:$Rm, word_Xm_regext:$Ext),
32983405 "ldrsw\t$Rt, [$Rn, $Rm, $Ext]",
3299 [], NoItinerary>;
3406 [], NoItinerary>,
3407 Sched<[WriteLd, ReadLd, ReadLd]>;
33003408 }
33013409 def : InstAlias<"ldrsw $Rt, [$Rn, $Rm]",
33023410 (LDRSWx_Xm_RegOffset GPR64:$Rt, GPR64xsp:$Rn, GPR64:$Rm, 2)>;
33073415 (outs GPR64:$Rt),
33083416 (ins GPR64xsp:$Rn, simm9:$SImm9),
33093417 "ldursw\t$Rt, [$Rn, $SImm9]",
3310 [], NoItinerary> {
3418 [], NoItinerary>,
3419 Sched<[WriteLd, ReadLd]> {
33113420 let mayLoad = 1;
33123421 }
33133422 def : InstAlias<"ldursw $Rt, [$Rn]", (LDURSWx GPR64:$Rt, GPR64xsp:$Rn, 0)>;
33173426 (outs GPR64:$Rt, GPR64xsp:$Rn_wb),
33183427 (ins GPR64xsp:$Rn, simm9:$SImm9),
33193428 "ldrsw\t$Rt, [$Rn], $SImm9",
3320 [], NoItinerary> {
3429 [], NoItinerary>,
3430 Sched<[WriteLd, ReadLd]> {
33213431 let mayLoad = 1;
33223432 let Constraints = "$Rn = $Rn_wb";
33233433 let DecoderMethod = "DecodeSingleIndexedInstruction";
33273437 (outs GPR64:$Rt, GPR64xsp:$Rn_wb),
33283438 (ins GPR64xsp:$Rn, simm9:$SImm9),
33293439 "ldrsw\t$Rt, [$Rn, $SImm9]!",
3330 [], NoItinerary> {
3440 [], NoItinerary>,
3441 Sched<[WriteLd, ReadLd]> {
33313442 let mayLoad = 1;
33323443 let Constraints = "$Rn = $Rn_wb";
33333444 let DecoderMethod = "DecodeSingleIndexedInstruction";
33403451 def PRFM : A64I_LSunsigimm<0b11, 0b0, 0b10, (outs),
33413452 (ins prefetch_op:$Rt, GPR64xsp:$Rn, dword_uimm12:$UImm12),
33423453 "prfm\t$Rt, [$Rn, $UImm12]",
3343 [], NoItinerary> {
3454 [], NoItinerary>,
3455 Sched<[WritePreLd, ReadPreLd]> {
33443456 let mayLoad = 1;
33453457 }
33463458 def : InstAlias<"prfm $Rt, [$Rn]",
33513463 (ins prefetch_op:$Rt, GPR64xsp:$Rn,
33523464 GPR32:$Rm, dword_Wm_regext:$Ext),
33533465 "prfm\t$Rt, [$Rn, $Rm, $Ext]",
3354 [], NoItinerary>;
3466 [], NoItinerary>,
3467 Sched<[WritePreLd, ReadPreLd]>;
33553468 def PRFM_Xm_RegOffset : A64I_LSregoff<0b11, 0b0, 0b10, 0b1, (outs),
33563469 (ins prefetch_op:$Rt, GPR64xsp:$Rn,
33573470 GPR64:$Rm, dword_Xm_regext:$Ext),
33583471 "prfm\t$Rt, [$Rn, $Rm, $Ext]",
3359 [], NoItinerary>;
3472 [], NoItinerary>,
3473 Sched<[WritePreLd, ReadPreLd]>;
33603474 }
33613475
33623476 def : InstAlias<"prfm $Rt, [$Rn, $Rm]",
33673481 def PRFUM : A64I_LSunalimm<0b11, 0b0, 0b10, (outs),
33683482 (ins prefetch_op:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
33693483 "prfum\t$Rt, [$Rn, $SImm9]",
3370 [], NoItinerary> {
3484 [], NoItinerary>,
3485 Sched<[WritePreLd, ReadPreLd]> {
33713486 let mayLoad = 1;
33723487 }
33733488 def : InstAlias<"prfum $Rt, [$Rn]",
33873502 def _UnPriv_STR : A64I_LSunpriv
33883503 (outs), (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
33893504 "sttr" # asmsuffix # "\t$Rt, [$Rn, $SImm9]",
3390 [], NoItinerary> {
3505 [], NoItinerary>,
3506 Sched<[WriteLd, ReadLd]> {
33913507 let mayStore = 1;
33923508 }
33933509
33973513 def _UnPriv_LDR : A64I_LSunpriv
33983514 (outs GPR:$Rt), (ins GPR64xsp:$Rn, simm9:$SImm9),
33993515 "ldtr" # asmsuffix # "\t$Rt, [$Rn, $SImm9]",
3400 [], NoItinerary> {
3516 [], NoItinerary>,
3517 Sched<[WriteLd, ReadLd]> {
34013518 let mayLoad = 1;
34023519 }
34033520
34263543 (outs GPR32:$Rt),
34273544 (ins GPR64xsp:$Rn, simm9:$SImm9),
34283545 "ldtrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]",
3429 [], NoItinerary>;
3546 [], NoItinerary>,
3547 Sched<[WriteLd, ReadLd]>;
34303548
34313549 def x : A64I_LSunpriv
34323550 (outs GPR64:$Rt),
34333551 (ins GPR64xsp:$Rn, simm9:$SImm9),
34343552 "ldtrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]",
3435 [], NoItinerary>;
3553 [], NoItinerary>,
3554 Sched<[WriteLd, ReadLd]>;
34363555 }
34373556
34383557 def : InstAlias<"ldtrs" # asmopcode # " $Rt, [$Rn]",
34533572 (outs GPR64:$Rt),
34543573 (ins GPR64xsp:$Rn, simm9:$SImm9),
34553574 "ldtrsw\t$Rt, [$Rn, $SImm9]",
3456 [], NoItinerary> {
3575 [], NoItinerary>,
3576 Sched<[WriteLd, ReadLd]> {
34573577 let mayLoad = 1;
34583578 }
34593579 def : InstAlias<"ldtrsw $Rt, [$Rn]", (LDTRSWx GPR64:$Rt, GPR64xsp:$Rn, 0)>;
35153635 Operand simm7, string prefix> {
35163636 def _STR : A64I_LSPoffset
35173637 (ins SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn, simm7:$SImm7),
3518 "stp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {
3638 "stp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary>,
3639 Sched<[WriteLd, ReadLd]> {
35193640 let mayStore = 1;
35203641 let DecoderMethod = "DecodeLDSTPairInstruction";
35213642 }
35263647 def _LDR : A64I_LSPoffset
35273648 (outs SomeReg:$Rt, SomeReg:$Rt2),
35283649 (ins GPR64xsp:$Rn, simm7:$SImm7),
3529 "ldp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {
3650 "ldp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary>,
3651 Sched<[WriteLd, ReadLd]> {
35303652 let mayLoad = 1;
35313653 let DecoderMethod = "DecodeLDSTPairInstruction";
35323654 }
35523674 (outs SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn_wb),
35533675 (ins GPR64xsp:$Rn, simm7:$SImm7),
35543676 "ldp\t$Rt, $Rt2, [$Rn], $SImm7",
3555 [], NoItinerary> {
3677 [], NoItinerary>,
3678 Sched<[WriteLd, ReadLd]> {
35563679 let mayLoad = 1;
35573680 let Constraints = "$Rn = $Rn_wb";
35583681 let DecoderMethod = "DecodeLDSTPairInstruction";
35713694 (outs SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn_wb),
35723695 (ins GPR64xsp:$Rn, simm7:$SImm7),
35733696 "ldp\t$Rt, $Rt2, [$Rn, $SImm7]!",
3574 [], NoItinerary> {
3697 [], NoItinerary>,
3698 Sched<[WriteLd, ReadLd]> {
35753699 let mayLoad = 1;
35763700 let Constraints = "$Rn = $Rn_wb";
35773701 let DecoderMethod = "DecodeLDSTPairInstruction";
35903714 def _NonTemp_LDR : A64I_LSPnontemp
35913715 (outs SomeReg:$Rt, SomeReg:$Rt2),
35923716 (ins GPR64xsp:$Rn, simm7:$SImm7),
3593 "ldnp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {
3717 "ldnp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary>,
3718 Sched<[WriteLd, ReadLd]> {
35943719 let mayLoad = 1;
35953720 let DecoderMethod = "DecodeLDSTPairInstruction";
35963721 }
36153740 def LDPSWx : A64I_LSPoffset<0b01, 0b0, 0b1,
36163741 (outs GPR64:$Rt, GPR64:$Rt2),
36173742 (ins GPR64xsp:$Rn, word_simm7:$SImm7),
3618 "ldpsw\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {
3743 "ldpsw\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary>,
3744 Sched<[WriteLd, ReadLd]> {
36193745 let mayLoad = 1;
36203746 let DecoderMethod = "DecodeLDSTPairInstruction";
36213747 }
36363762 (outs GPR64:$Rt, GPR64:$Rt2, GPR64:$Rn_wb),
36373763 (ins GPR64xsp:$Rn, word_simm7:$SImm7),
36383764 "ldpsw\t$Rt, $Rt2, [$Rn, $SImm7]!",
3639 [], NoItinerary> {
3765 [], NoItinerary>,
3766 Sched<[WriteLd, ReadLd]> {
36403767 let mayLoad = 1;
36413768 let Constraints = "$Rn = $Rn_wb";
36423769 let DecoderMethod = "DecodeLDSTPairInstruction";
36813808 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
36823809 [(set i32:$Rd,
36833810 (opnode i32:$Rn, logical_imm32_operand:$Imm))],
3684 NoItinerary>;
3811 NoItinerary>,
3812 Sched<[WriteALU, ReadALU]>;
36853813
36863814 def xxi : A64I_logicalimm<0b1, opc, (outs GPR64xsp:$Rd),
36873815 (ins GPR64:$Rn, logical_imm64_operand:$Imm),
36883816 !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
36893817 [(set i64:$Rd,
36903818 (opnode i64:$Rn, logical_imm64_operand:$Imm))],
3691 NoItinerary>;
3819 NoItinerary>,
3820 Sched<[WriteALU, ReadALU]>;
36923821 }
36933822
36943823 defm AND : A64I_logimmSizes<0b00, "and", and>;
36993828 def ANDSwwi : A64I_logicalimm<0b0, 0b11, (outs GPR32:$Rd),
37003829 (ins GPR32:$Rn, logical_imm32_operand:$Imm),
37013830 "ands\t$Rd, $Rn, $Imm",
3702 [], NoItinerary>;
3831 [], NoItinerary>,
3832 Sched<[WriteALU, ReadALU]>;
37033833
37043834 def ANDSxxi : A64I_logicalimm<0b1, 0b11, (outs GPR64:$Rd),
37053835 (ins GPR64:$Rn, logical_imm64_operand:$Imm),
37063836 "ands\t$Rd, $Rn, $Imm",
3707 [], NoItinerary>;
3837 [], NoItinerary>,
3838 Sched<[WriteALU, ReadALU]>;
37083839 }
37093840
37103841
37493880 [(set ty:$Rd, (opfrag ty:$Rn, (shl ty:$Rm,
37503881 !cast("lsl_operand_" # ty):$Imm6))
37513882 )],
3752 NoItinerary>;
3883 NoItinerary>,
3884 Sched<[WriteALU, ReadALU, ReadALU]>;
37533885
37543886 def _lsr : A64I_logicalshift
37553887 (outs GPR:$Rd),
37593891 [(set ty:$Rd, (opfrag ty:$Rn, (srl ty:$Rm,
37603892 !cast("lsr_operand_" # ty):$Imm6))
37613893 )],
3762 NoItinerary>;
3894 NoItinerary>,
3895 Sched<[WriteALU, ReadALU, ReadALU]>;
37633896
37643897 def _asr : A64I_logicalshift
37653898 (outs GPR:$Rd),
37693902 [(set ty:$Rd, (opfrag ty:$Rn, (sra ty:$Rm,
37703903 !cast("asr_operand_" # ty):$Imm6))
37713904 )],
3772 NoItinerary>;
3905 NoItinerary>,
3906 Sched<[WriteALU, ReadALU, ReadALU]>;
37733907
37743908 def _ror : A64I_logicalshift
37753909 (outs GPR:$Rd),
37793913 [(set ty:$Rd, (opfrag ty:$Rn, (rotr ty:$Rm,
37803914 !cast("ror_operand_" # ty):$Imm6))
37813915 )],
3782 NoItinerary>;
3916 NoItinerary>,
3917 Sched<[WriteALU, ReadALU, ReadALU]>;
37833918 }
37843919
37853920 def _noshift
38343969 [(set NZCV, (A64setcc (and ty:$Rn, (shl ty:$Rm,
38353970 !cast("lsl_operand_" # ty):$Imm6)),
38363971 0, signed_cond))],
3837 NoItinerary>;
3972 NoItinerary>,
3973 Sched<[WriteALU, ReadALU, ReadALU]>;
38383974
38393975
38403976 def _lsr : A64I_logicalshift
38453981 [(set NZCV, (A64setcc (and ty:$Rn, (srl ty:$Rm,
38463982 !cast("lsr_operand_" # ty):$Imm6)),
38473983 0, signed_cond))],
3848 NoItinerary>;
3984 NoItinerary>,
3985 Sched<[WriteALU, ReadALU, ReadALU]>;
38493986
38503987 def _asr : A64I_logicalshift
38513988 (outs),
38553992 [(set NZCV, (A64setcc (and ty:$Rn, (sra ty:$Rm,
38563993 !cast("asr_operand_" # ty):$Imm6)),
38573994 0, signed_cond))],
3858 NoItinerary>;
3995 NoItinerary>,
3996 Sched<[WriteALU, ReadALU, ReadALU]>;
38593997
38603998 def _ror : A64I_logicalshift
38613999 (outs),
38654003 [(set NZCV, (A64setcc (and ty:$Rn, (rotr ty:$Rm,
38664004 !cast("ror_operand_" # ty):$Imm6)),
38674005 0, signed_cond))],
3868 NoItinerary>;
4006 NoItinerary>,
4007 Sched<[WriteALU, ReadALU, ReadALU]>;
38694008 }
38704009
38714010 def _noshift : InstAlias<"tst $Rn, $Rm",
38884027 "mvn\t$Rd, $Rm, $Imm6",
38894028 [(set ty:$Rd, (not (shl ty:$Rm,
38904029 !cast("lsl_operand_" # ty):$Imm6)))],
3891 NoItinerary>;
4030 NoItinerary>,
4031 Sched<[WriteALU, ReadALU, ReadALU]>;
38924032
38934033
38944034 def _lsr : A64I_logicalshift
38984038 "mvn\t$Rd, $Rm, $Imm6",
38994039 [(set ty:$Rd, (not (srl ty:$Rm,
39004040 !cast("lsr_operand_" # ty):$Imm6)))],
3901 NoItinerary>;
4041 NoItinerary>,
4042 Sched<[WriteALU, ReadALU, ReadALU]>;
39024043
39034044 def _asr : A64I_logicalshift
39044045 (outs GPR:$Rd),
39074048 "mvn\t$Rd, $Rm, $Imm6",
39084049 [(set ty:$Rd, (not (sra ty:$Rm,
39094050 !cast("asr_operand_" # ty):$Imm6)))],
3910 NoItinerary>;
4051 NoItinerary>,
4052 Sched<[WriteALU, ReadALU, ReadALU]>;
39114053
39124054 def _ror : A64I_logicalshift
39134055 (outs GPR:$Rd),
39164058 "mvn\t$Rd, $Rm, $Imm6",
39174059 [(set ty:$Rd, (not (rotr ty:$Rm,
39184060 !cast("lsl_operand_" # ty):$Imm6)))],
3919 NoItinerary>;
4061 NoItinerary>,
4062 Sched<[WriteALU, ReadALU, ReadALU]>;
39204063 }
39214064
39224065 def _noshift : InstAlias<"mvn $Rn, $Rm",
39714114
39724115 def wii : A64I_movw<0b0, opc, (outs GPR32:$Rd), ins32bit,
39734116 !strconcat(asmop, "\t$Rd, $FullImm"),
3974 [], NoItinerary> {
4117 [], NoItinerary>,
4118 Sched<[WriteALU]> {
39754119 bits<18> FullImm;
39764120 let UImm16 = FullImm{15-0};
39774121 let Shift = FullImm{17-16};
39794123
39804124 def xii : A64I_movw<0b1, opc, (outs GPR64:$Rd), ins64bit,
39814125 !strconcat(asmop, "\t$Rd, $FullImm"),
3982 [], NoItinerary> {
4126 [], NoItinerary>,
4127 Sched<[WriteALU]> {
39834128 bits<18> FullImm;
39844129 let UImm16 = FullImm{15-0};
39854130 let Shift = FullImm{17-16};
40874232
40884233 let hasSideEffects = 0 in {
40894234 def ADRxi : A64I_PCADR<0b0, (outs GPR64:$Rd), (ins adr_label:$Label),
4090 "adr\t$Rd, $Label", [], NoItinerary>;
4235 "adr\t$Rd, $Label", [], NoItinerary>,
4236 Sched<[WriteALUs]>;
40914237
40924238 def ADRPxi : A64I_PCADR<0b1, (outs GPR64:$Rd), (ins adrp_label:$Label),
4093 "adrp\t$Rd, $Label", [], NoItinerary>;
4239 "adrp\t$Rd, $Label", [], NoItinerary>,
4240 Sched<[WriteALUs]>;
40944241 }
40954242
40964243 //===----------------------------------------------------------------------===//
43764523 "tbz\t$Rt, $Imm, $Label",
43774524 [(A64br_cc (A64cmp (and i64:$Rt, tstb64_pat:$Imm), 0),
43784525 A64eq, bb:$Label)],
4379 NoItinerary>;
4526 NoItinerary>,
4527 Sched<[WriteBr]>;
43804528
43814529 def TBNZxii : A64I_TBimm<0b1, (outs),
43824530 (ins GPR64:$Rt, uimm6:$Imm, tbimm_target:$Label),
43834531 "tbnz\t$Rt, $Imm, $Label",
43844532 [(A64br_cc (A64cmp (and i64:$Rt, tstb64_pat:$Imm), 0),
43854533 A64ne, bb:$Label)],
4386 NoItinerary>;
4534 NoItinerary>,
4535 Sched<[WriteBr]>;
43874536
43884537
43894538 // Note, these instructions overlap with the above 64-bit patterns. This is
43954544 "tbz\t$Rt, $Imm, $Label",
43964545 [(A64br_cc (A64cmp (and i32:$Rt, tstb32_pat:$Imm), 0),
43974546 A64eq, bb:$Label)],
4398 NoItinerary> {
4547 NoItinerary>,
4548 Sched<[WriteBr]> {
43994549 let Imm{5} = 0b0;
44004550 }
44014551
44044554 "tbnz\t$Rt, $Imm, $Label",
44054555 [(A64br_cc (A64cmp (and i32:$Rt, tstb32_pat:$Imm), 0),
44064556 A64ne, bb:$Label)],
4407 NoItinerary> {
4557 NoItinerary>,
4558 Sched<[WriteBr]> {
44084559 let Imm{5} = 0b0;
44094560 }
44104561 }
44394590 class A64I_BimmImpl patterns, Operand lbl_type>
44404591 : A64I_Bimm
44414592 !strconcat(asmop, "\t$Label"), patterns,
4442 NoItinerary>;
4593 NoItinerary>,
4594 Sched<[WriteBr]>;
44434595
44444596 let isBranch = 1 in {
44454597 def Bimm : A64I_BimmImpl<0b0, "b", [(br bb:$Label)], bimm_target> {
44474599 let isBarrier = 1;
44484600 }
44494601
4450 def BLimm : A64I_BimmImpl<0b1, "bl",
4451 [(AArch64Call tglobaladdr:$Label)], blimm_target> {
4452 let isCall = 1;
4453 let Defs = [X30];
4602 let SchedRW = [WriteBrL] in {
4603 def BLimm : A64I_BimmImpl<0b1, "bl",
4604 [(AArch64Call tglobaladdr:$Label)], blimm_target> {
4605 let isCall = 1;
4606 let Defs = [X30];
4607 }
44544608 }
44554609 }
44564610
44674621 dag outs, dag ins, string asmstr, list patterns,
44684622 InstrItinClass itin = NoItinerary>
44694623 : A64I_Breg
4470 outs, ins, asmstr, patterns, itin> {
4624 outs, ins, asmstr, patterns, itin>,
4625 Sched<[WriteBr]> {
44714626 let isBranch = 1;
44724627 let isIndirectBranch = 1;
44734628 }
44834638 let isTerminator = 1;
44844639 }
44854640
4486 def BLRx : A64I_BregImpl<0b0001, (outs), (ins GPR64:$Rn),
4487 "blr\t$Rn", [(AArch64Call i64:$Rn)]> {
4488 let isBarrier = 0;
4489 let isCall = 1;
4490 let Defs = [X30];
4641 let SchedRW = [WriteBrL] in {
4642 def BLRx : A64I_BregImpl<0b0001, (outs), (ins GPR64:$Rn),
4643 "blr\t$Rn", [(AArch64Call i64:$Rn)]> {
4644 let isBarrier = 0;
4645 let isCall = 1;
4646 let Defs = [X30];
4647 }
44914648 }
44924649
44934650 def RETx : A64I_BregImpl<0b0010, (outs), (ins GPR64:$Rn),
66 //
77 //===----------------------------------------------------------------------===//
88
9 //===----------------------------------------------------------------------===//
10 // Generic processor itineraries for legacy compatibility.
11
912 def GenericItineraries : ProcessorItineraries<[], [], []>;
13
14
15 //===----------------------------------------------------------------------===//
16 // Base SchedReadWrite types
17
18 // Basic ALU
19 def WriteALU : SchedWrite; // Generic: may contain shift and/or ALU operation
20 def WriteALUs : SchedWrite; // Shift only with no ALU operation
21 def ReadALU : SchedRead; // Operand not needed for shifting
22 def ReadALUs : SchedRead; // Operand needed for shifting
23
24 // Multiply with optional accumulate
25 def WriteMAC : SchedWrite;
26 def ReadMAC : SchedRead;
27
28 // Compares
29 def WriteCMP : SchedWrite;
30 def ReadCMP : SchedRead;
31
32 // Division
33 def WriteDiv : SchedWrite;
34 def ReadDiv : SchedRead;
35
36 // Loads
37 def WriteLd : SchedWrite;
38 def WritePreLd : SchedWrite;
39 def ReadLd : SchedRead;
40 def ReadPreLd : SchedRead;
41
42 // Branches
43 def WriteBr : SchedWrite;
44 def WriteBrL : SchedWrite;
45 def ReadBr : SchedRead;
46
47 // Floating Point ALU
48 def WriteFPALU : SchedWrite;
49 def ReadFPALU : SchedRead;
50
51 // Floating Point MAC, Mul, Div, Sqrt
52 // Most processors will simply send all of these down a dedicated pipe, but
53 // they're explicitly seperated here for flexibility of modeling later. May
54 // consider consolidating them into a single WriteFPXXXX type in the future.
55 def WriteFPMAC : SchedWrite;
56 def WriteFPMul : SchedWrite;
57 def WriteFPDiv : SchedWrite;
58 def WriteFPSqrt : SchedWrite;
59 def ReadFPMAC : SchedRead;
60 def ReadFPMul : SchedRead;
61 def ReadFPDiv : SchedRead;
62 def ReadFPSqrt : SchedRead;
63
64 // Noop
65 def WriteNoop : SchedWrite;
66
67
68 //===----------------------------------------------------------------------===//
69 // Subtarget specific Machine Models.
70
71 include "AArch64ScheduleA53.td"
0 //=- AArch64ScheduleA53.td - ARM Cortex-A53 Scheduling Definitions -*- tablegen -*-=//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the itinerary class data for the ARM Cortex A53 processors.
10 //
11 //===----------------------------------------------------------------------===//
12
13 // ===---------------------------------------------------------------------===//
14 // The following definitions describe the simpler per-operand machine model.
15 // This works with MachineScheduler. See MCSchedModel.h for details.
16
17 // Cortex-A53 machine model for scheduling and other instruction cost heuristics.
18 def CortexA53Model : SchedMachineModel {
19 let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.
20 let MinLatency = 1 ; // OperandCycles are interpreted as MinLatency.
21 let LoadLatency = 2; // Optimistic load latency assuming bypass.
22 // This is overriden by OperandCycles if the
23 // Itineraries are queried instead.
24 let MispredictPenalty = 9; // Based on "Cortex-A53 Software Optimisation
25 // Specification - Instruction Timings"
26 // v 1.0 Spreadsheet
27 }
28
29
30 //===----------------------------------------------------------------------===//
31 // Define each kind of processor resource and number available.
32
33 // Modeling each pipeline as a ProcResource using the default BufferSize = -1.
34 // Cortex-A53 is in-order and therefore should be using BufferSize = 0. The
35 // current configuration performs better with the basic latencies provided so
36 // far. Will revisit BufferSize once the latency information is more accurate.
37
38 let SchedModel = CortexA53Model in {
39
40 def A53UnitALU : ProcResource<2>; // Int ALU
41 def A53UnitMAC : ProcResource<1>; // Int MAC
42 def A53UnitDiv : ProcResource<1>; // Int Division
43 def A53UnitLdSt : ProcResource<1>; // Load/Store
44 def A53UnitB : ProcResource<1>; // Branch
45 def A53UnitFPALU : ProcResource<1>; // FP ALU
46 def A53UnitFPMDS : ProcResource<1>; // FP Mult/Div/Sqrt
47
48
49 //===----------------------------------------------------------------------===//
50 // Subtarget-specific SchedWrite types which both map the ProcResources and
51 // set the latency.
52
53 // Issue - Every instruction must consume an A53WriteIssue. Optionally,
54 // instructions that cannot be dual-issued will also include the
55 // A53WriteIssue2nd in their SchedRW list. That second WriteRes will
56 // ensure that a second issue slot is consumed.
57 def A53WriteIssue : SchedWriteRes<[]>;
58 def A53WriteIssue2nd : SchedWriteRes<[]> { let Latency = 0; }
59
60 // ALU - These are reduced to 1 despite a true latency of 4 in order to easily
61 // model forwarding logic. Once forwarding is properly modelled, then
62 // they'll be corrected.
63 def : WriteRes { let Latency = 1; }
64 def : WriteRes { let Latency = 1; }
65 def : WriteRes { let Latency = 1; }
66
67 // MAC
68 def : WriteRes { let Latency = 4; }
69
70 // Div
71 def : WriteRes { let Latency = 4; }
72
73 // Load
74 def : WriteRes { let Latency = 4; }
75 def : WriteRes { let Latency = 4; }
76
77 // Branch
78 def : WriteRes;
79 def : WriteRes;
80
81 // FP ALU
82 def : WriteRes {let Latency = 6; }
83
84 // FP MAC, Mul, Div, Sqrt
85 // Using Double Precision numbers for now as a worst case. Additionally, not
86 // modeling the exact hazard but instead treating the whole pipe as a hazard.
87 // As an example VMUL, VMLA, and others are actually pipelined. VDIV and VSQRT
88 // have a total latency of 33 and 32 respectively but only a hazard of 29 and
89 // 28 (double-prescion example).
90 def : WriteRes { let Latency = 10; }
91 def : WriteRes { let Latency = 6; }
92 def : WriteRes { let Latency = 33;
93 let ResourceCycles = [29]; }
94 def : WriteRes { let Latency = 32;
95 let ResourceCycles = [28]; }
96
97
98 //===----------------------------------------------------------------------===//
99 // Subtarget-specific SchedRead types.
100
101 // No forwarding defined for ReadALU yet.
102 def : ReadAdvance;
103
104 // No forwarding defined for ReadCMP yet.
105 def : ReadAdvance;
106
107 // No forwarding defined for ReadBr yet.
108 def : ReadAdvance;
109
110 // No forwarding defined for ReadMAC yet.
111 def : ReadAdvance;
112
113 // No forwarding defined for ReadDiv yet.
114 def : ReadAdvance;
115
116 // No forwarding defined for ReadLd, ReadPreLd yet.
117 def : ReadAdvance;
118 def : ReadAdvance;
119
120 // No forwarding defined for ReadFPALU yet.
121 def : ReadAdvance;
122
123 // No forwarding defined for ReadFPMAC/Mul/Div/Sqrt yet.
124 def : ReadAdvance;
125 def : ReadAdvance;
126 def : ReadAdvance;
127 def : ReadAdvance;
128
129 }
2828 class AArch64Subtarget : public AArch64GenSubtargetInfo {
2929 virtual void anchor();
3030 protected:
31 enum ARMProcFamilyEnum {Others, CortexA53, CortexA57};
32
33 /// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
34 ARMProcFamilyEnum ARMProcFamily;
35
3136 bool HasFPARMv8;
3237 bool HasNEON;
3338 bool HasCrypto;
0 ; REQUIRES: asserts
1 ; RUN: llc < %s -march=aarch64 -mcpu=cortex-a53 -pre-RA-sched=source -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s
2 ;
3 ; The Cortex-A53 machine model will cause the MADD instruction to be scheduled
4 ; much higher than the ADD instructions in order to hide latency. When not
5 ; specifying a subtarget, the MADD will remain near the end of the block.
6 ; CHECK: main
7 ; CHECK: *** Final schedule for BB#2 ***
8 ; CHECK: SU(13)
9 ; CHECK: MADDwwww
10 ; CHECK: SU(4)
11 ; CHECK: ADDwwi_lsl0_s
12 ; CHECK: ********** MI Scheduling **********
13 @main.x = private unnamed_addr constant [8 x i32] [i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1], align 4
14 @main.y = private unnamed_addr constant [8 x i32] [i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2], align 4
15
16 ; Function Attrs: nounwind
17 define i32 @main() #0 {
18 entry:
19 %retval = alloca i32, align 4
20 %x = alloca [8 x i32], align 4
21 %y = alloca [8 x i32], align 4
22 %i = alloca i32, align 4
23 %xx = alloca i32, align 4
24 %yy = alloca i32, align 4
25 store i32 0, i32* %retval
26 %0 = bitcast [8 x i32]* %x to i8*
27 call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* bitcast ([8 x i32]* @main.x to i8*), i64 32, i32 4, i1 false)
28 %1 = bitcast [8 x i32]* %y to i8*
29 call void @llvm.memcpy.p0i8.p0i8.i64(i8* %1, i8* bitcast ([8 x i32]* @main.y to i8*), i64 32, i32 4, i1 false)
30 store i32 0, i32* %xx, align 4
31 store i32 0, i32* %yy, align 4
32 store i32 0, i32* %i, align 4
33 br label %for.cond
34
35 for.cond: ; preds = %for.inc, %entry
36 %2 = load i32* %i, align 4
37 %cmp = icmp slt i32 %2, 8
38 br i1 %cmp, label %for.body, label %for.end
39
40 for.body: ; preds = %for.cond
41 %3 = load i32* %i, align 4
42 %idxprom = sext i32 %3 to i64
43 %arrayidx = getelementptr inbounds [8 x i32]* %x, i32 0, i64 %idxprom
44 %4 = load i32* %arrayidx, align 4
45 %add = add nsw i32 %4, 1
46 store i32 %add, i32* %xx, align 4
47 %5 = load i32* %xx, align 4
48 %add1 = add nsw i32 %5, 12
49 store i32 %add1, i32* %xx, align 4
50 %6 = load i32* %xx, align 4
51 %add2 = add nsw i32 %6, 23
52 store i32 %add2, i32* %xx, align 4
53 %7 = load i32* %xx, align 4
54 %add3 = add nsw i32 %7, 34
55 store i32 %add3, i32* %xx, align 4
56 %8 = load i32* %i, align 4
57 %idxprom4 = sext i32 %8 to i64
58 %arrayidx5 = getelementptr inbounds [8 x i32]* %y, i32 0, i64 %idxprom4
59 %9 = load i32* %arrayidx5, align 4
60 %10 = load i32* %yy, align 4
61 %mul = mul nsw i32 %10, %9
62 store i32 %mul, i32* %yy, align 4
63 br label %for.inc
64
65 for.inc: ; preds = %for.body
66 %11 = load i32* %i, align 4
67 %inc = add nsw i32 %11, 1
68 store i32 %inc, i32* %i, align 4
69 br label %for.cond
70
71 for.end: ; preds = %for.cond
72 %12 = load i32* %xx, align 4
73 %13 = load i32* %yy, align 4
74 %add6 = add nsw i32 %12, %13
75 ret i32 %add6
76 }
77
78 ; Function Attrs: nounwind
79 declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture readonly, i64, i32, i1) #1
80
81 attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
82 attributes #1 = { nounwind }