llvm.org GIT mirror llvm / 819f312
[globalisel] Move as much RegisterBank initialization to the constructor as possible Summary: The register bank is now entirely initialized in the constructor. However, we still have the hardcoded number of register classes which will be dealt with in the TableGen patch (D27338) since we do not have access to this information to resolve this at this stage. The number of register classes is known to the TRI and to TableGen but the RegisterBank constructor is too early for the former and too late for the latter. This will be fixed when the data is tablegen-erated. Reviewers: t.p.northover, ab, rovka, qcolombet Subscribers: aditya_nandakumar, kristof.beyls, vkalintiris, llvm-commits, dberris Differential Revision: https://reviews.llvm.org/D27809 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291770 91177308-0d34-0410-b5e6-96231b3b80d8 Daniel Sanders 3 years ago
7 changed file(s) with 32 addition(s) and 43 deletion(s). Raw diff Collapse all Expand all
4040 friend RegisterBankInfo;
4141
4242 public:
43 /// The default constructor will leave the object in
44 /// an invalid state. I.e. isValid() == false.
45 /// The fields must be updated to fix that and only
46 /// RegisterBankInfo instances are allowed to do that
47 RegisterBank();
43 RegisterBank(unsigned ID, const char *Name, unsigned Size,
44 const uint32_t *ContainedRegClasses);
4845
4946 /// Get the identifier of this register bank.
5047 unsigned getID() const { return ID; }
395395 llvm_unreachable("This constructor should not be executed");
396396 }
397397
398 void setRegBankData(unsigned ID, const char *Name, unsigned Size,
399 const uint32_t *CoveredClasses);
400
401398 /// Get the register bank identified by \p ID.
402399 RegisterBank &getRegBank(unsigned ID) {
403400 assert(ID < getNumRegBanks() && "Accessing an unknown register bank");
1818
1919 const unsigned RegisterBank::InvalidID = UINT_MAX;
2020
21 RegisterBank::RegisterBank() : ID(InvalidID), Name(nullptr), Size(0) {}
21 RegisterBank::RegisterBank(unsigned ID, const char *Name, unsigned Size,
22 const uint32_t *CoveredClasses)
23 : ID(ID), Name(Name), Size(Size) {
24 ContainedRegClasses.resize(200);
25 ContainedRegClasses.setBitsInMask(CoveredClasses);
26 }
2227
2328 bool RegisterBank::verify(const TargetRegisterInfo &TRI) const {
2429 assert(isValid() && "Invalid register bank");
5555 unsigned NumRegBanks)
5656 : RegBanks(RegBanks), NumRegBanks(NumRegBanks) {
5757 #ifndef NDEBUG
58 for (unsigned Idx = 0, End = getNumRegBanks(); Idx != End; ++Idx)
58 for (unsigned Idx = 0, End = getNumRegBanks(); Idx != End; ++Idx) {
5959 assert(RegBanks[Idx] != nullptr && "Invalid RegisterBank");
60 assert(RegBanks[Idx]->isValid() && "RegisterBank should be valid");
61 }
6062 #endif // NDEBUG
6163 }
6264
7880 }
7981 #endif // NDEBUG
8082 return true;
81 }
82
83 void RegisterBankInfo::setRegBankData(unsigned ID, const char *Name,
84 unsigned Size,
85 const uint32_t *CoveredClasses) {
86 RegisterBank &RB = getRegBank(ID);
87 RB.ID = ID;
88 RB.Name = Name;
89 RB.Size = Size;
90 RB.ContainedRegClasses.resize(200);
91 RB.ContainedRegClasses.setBitsInMask(CoveredClasses);
9283 }
9384
9485 const RegisterBank *
140140 0,
141141 };
142142
143 RegisterBank GPRRegBank;
144 RegisterBank FPRRegBank;
145 RegisterBank CCRRegBank;
143 RegisterBank GPRRegBank(AArch64::GPRRegBankID, "GPR", 64, GPRCoverageData);
144 RegisterBank FPRRegBank(AArch64::FPRRegBankID, "FPR", 512, FPRCoverageData);
145 RegisterBank CCRRegBank(AArch64::CCRRegBankID, "CCR", 32, CCRCoverageData);
146146
147147 RegisterBank *RegBanks[] = {&GPRRegBank, &FPRRegBank, &CCRRegBank};
148148
4040 if (AlreadyInit)
4141 return;
4242 AlreadyInit = true;
43 // The GPR register bank is fully defined by all the registers in
44 // GR64all + its subclasses.
45 setRegBankData(AArch64::GPRRegBankID, "GPR", 64, AArch64::GPRCoverageData);
43
4644 const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID);
4745 (void)RBGPR;
4846 assert(&AArch64::GPRRegBank == &RBGPR &&
4947 "The order in RegBanks is messed up");
50 assert(RBGPR.covers(*TRI.getRegClass(AArch64::GPR32RegClassID)) &&
51 "Subclass not added?");
52 assert(RBGPR.getSize() == 64 && "GPRs should hold up to 64-bit");
53
54 // The FPR register bank is fully defined by all the registers in
55 // GR64all + its subclasses.
56 setRegBankData(AArch64::FPRRegBankID, "FPR", 512, AArch64::FPRCoverageData);
5748
5849 const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID);
5950 (void)RBFPR;
6051 assert(&AArch64::FPRRegBank == &RBFPR &&
6152 "The order in RegBanks is messed up");
53
54 const RegisterBank &RBCCR = getRegBank(AArch64::CCRRegBankID);
55 (void)RBCCR;
56 assert(&AArch64::CCRRegBank == &RBCCR &&
57 "The order in RegBanks is messed up");
58
59 // The GPR register bank is fully defined by all the registers in
60 // GR64all + its subclasses.
61 assert(RBGPR.covers(*TRI.getRegClass(AArch64::GPR32RegClassID)) &&
62 "Subclass not added?");
63 assert(RBGPR.getSize() == 64 && "GPRs should hold up to 64-bit");
64
65 // The FPR register bank is fully defined by all the registers in
66 // GR64all + its subclasses.
6267 assert(RBFPR.covers(*TRI.getRegClass(AArch64::QQRegClassID)) &&
6368 "Subclass not added?");
6469 assert(RBFPR.covers(*TRI.getRegClass(AArch64::FPR64RegClassID)) &&
6671 assert(RBFPR.getSize() == 512 &&
6772 "FPRs should hold up to 512-bit via QQQQ sequence");
6873
69 // Initialize the CCR bank.
70 setRegBankData(AArch64::CCRRegBankID, "CCR", 32, AArch64::CCRCoverageData);
71 const RegisterBank &RBCCR = getRegBank(AArch64::CCRRegBankID);
72 (void)RBCCR;
73 assert(&AArch64::CCRRegBank == &RBCCR &&
74 "The order in RegBanks is messed up");
7574 assert(RBCCR.covers(*TRI.getRegClass(AArch64::CCRRegClassID)) &&
7675 "Class not added?");
7776 assert(RBCCR.getSize() == 32 && "CCR should hold up to 32-bit");
5454 0,
5555 };
5656
57 RegisterBank GPRRegBank;
57 RegisterBank GPRRegBank(ARM::GPRRegBankID, "GPRB", 32, ARM::GPRCoverageData);
5858 RegisterBank *RegBanks[] = {&GPRRegBank};
5959
6060 RegisterBankInfo::PartialMapping GPRPartialMapping{0, 32, GPRRegBank};
7676 return;
7777 AlreadyInit = true;
7878
79 // Initialize the GPR bank.
80 setRegBankData(ARM::GPRRegBankID, "GPRB", 32, ARM::GPRCoverageData);
8179 const RegisterBank &RBGPR = getRegBank(ARM::GPRRegBankID);
8280 (void)RBGPR;
8381 assert(&ARM::GPRRegBank == &RBGPR && "The order in RegBanks is messed up");
82
83 // Initialize the GPR bank.
8484 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRRegClassID)) &&
8585 "Subclass not added?");
8686 assert(RBGPR.covers(*TRI.getRegClass(ARM::GPRwithAPSRRegClassID)) &&