llvm.org GIT mirror llvm / 81092dc
Remove (hopefully) all trailing whitespaces from the mips backend. Patch by Hatanaka, Akira git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127003 91177308-0d34-0410-b5e6-96231b3b80d8 Bruno Cardoso Lopes 9 years ago
20 changed file(s) with 267 addition(s) and 267 deletion(s). Raw diff Collapse all Expand all
66 //
77 //===----------------------------------------------------------------------===//
88 //
9 // This file contains the entry points for global functions defined in
9 // This file contains the entry points for global functions defined in
1010 // the LLVM Mips back-end.
1111 //
1212 //===----------------------------------------------------------------------===//
5858 def FeatureMips2 : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",
5959 "Mips2 ISA Support">;
6060 def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32",
61 "Mips32 ISA Support",
61 "Mips32 ISA Support",
6262 [FeatureCondMov, FeatureBitCount]>;
6363 def FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion",
6464 "Mips32r2", "Mips32r2 ISA Support",
2929 #include "llvm/MC/MCSymbol.h"
3030 #include "llvm/Target/Mangler.h"
3131 #include "llvm/Target/TargetData.h"
32 #include "llvm/Target/TargetLoweringObjectFile.h"
32 #include "llvm/Target/TargetLoweringObjectFile.h"
3333 #include "llvm/Target/TargetMachine.h"
3434 #include "llvm/Target/TargetOptions.h"
3535 #include "llvm/Target/TargetRegistry.h"
5252 return "Mips Assembly Printer";
5353 }
5454
55 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
55 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
5656 unsigned AsmVariant, const char *ExtraCode,
5757 raw_ostream &O);
5858 void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O);
5959 void printUnsignedImm(const MachineInstr *MI, int opNum, raw_ostream &O);
60 void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
60 void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
6161 const char *Modifier = 0);
62 void printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
62 void printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
6363 const char *Modifier = 0);
6464 void printSavedRegsBitmask(raw_ostream &O);
6565 void printHex32(unsigned int Value, raw_ostream &O);
9393 // -- Frame directive "frame Stackpointer, Stacksize, RARegister"
9494 // Describe the stack frame.
9595 //
96 // -- Mask directives "(f)mask bitmask, offset"
96 // -- Mask directives "(f)mask bitmask, offset"
9797 // Tells the assembler which registers are saved and where.
98 // bitmask - contain a little endian bitset indicating which registers are
99 // saved on function prologue (e.g. with a 0x80000000 mask, the
98 // bitmask - contain a little endian bitset indicating which registers are
99 // saved on function prologue (e.g. with a 0x80000000 mask, the
100100 // assembler knows the register 31 (RA) is saved at prologue.
101 // offset - the position before stack pointer subtraction indicating where
101 // offset - the position before stack pointer subtraction indicating where
102102 // the first saved register on prologue is located. (e.g. with a
103103 //
104104 // Consider the following function prologue:
109109 // sw $ra, 40($sp)
110110 // sw $fp, 36($sp)
111111 //
112 // With a 0xc0000000 mask, the assembler knows the register 31 (RA) and
113 // 30 (FP) are saved at prologue. As the save order on prologue is from
114 // left to right, RA is saved first. A -8 offset means that after the
112 // With a 0xc0000000 mask, the assembler knows the register 31 (RA) and
113 // 30 (FP) are saved at prologue. As the save order on prologue is from
114 // left to right, RA is saved first. A -8 offset means that after the
115115 // stack pointer subtration, the first register in the mask (RA) will be
116116 // saved at address 48-8=40.
117117 //
121121 // Mask directives
122122 //===----------------------------------------------------------------------===//
123123
124 // Create a bitmask with all callee saved registers for CPU or Floating Point
124 // Create a bitmask with all callee saved registers for CPU or Floating Point
125125 // registers. For CPU registers consider RA, GP and FP for saving if necessary.
126126 void MipsAsmPrinter::printSavedRegsBitmask(raw_ostream &O) {
127127 const TargetFrameLowering *TFI = TM.getFrameLowering();
167167 // Print a 32 bit hex number with all numbers.
168168 void MipsAsmPrinter::printHex32(unsigned Value, raw_ostream &O) {
169169 O << "0x";
170 for (int i = 7; i >= 0; i--)
170 for (int i = 7; i >= 0; i--)
171171 O << utohexstr((Value & (0xF << (i*4))) >> (i*4));
172172 }
173173
190190 }
191191
192192 /// Emit Set directives.
193 const char *MipsAsmPrinter::getCurrentABIString() const {
193 const char *MipsAsmPrinter::getCurrentABIString() const {
194194 switch (Subtarget->getTargetABI()) {
195 case MipsSubtarget::O32: return "abi32";
195 case MipsSubtarget::O32: return "abi32";
196196 case MipsSubtarget::O64: return "abiO64";
197197 case MipsSubtarget::N32: return "abiN32";
198198 case MipsSubtarget::N64: return "abi64";
202202
203203 llvm_unreachable("Unknown Mips ABI");
204204 return NULL;
205 }
205 }
206206
207207 void MipsAsmPrinter::EmitFunctionEntryLabel() {
208208 OutStreamer.EmitRawText("\t.ent\t" + Twine(CurrentFnSym->getName()));
213213 /// the first basic block in the function.
214214 void MipsAsmPrinter::EmitFunctionBodyStart() {
215215 emitFrameDirective();
216
216
217217 SmallString<128> Str;
218218 raw_svector_ostream OS(Str);
219219 printSavedRegsBitmask(OS);
225225 void MipsAsmPrinter::EmitFunctionBodyEnd() {
226226 // There are instruction for this macros, but they must
227227 // always be at the function end, and we can't emit and
228 // break with BB logic.
228 // break with BB logic.
229229 OutStreamer.EmitRawText(StringRef("\t.set\tmacro"));
230230 OutStreamer.EmitRawText(StringRef("\t.set\treorder"));
231231 OutStreamer.EmitRawText("\t.end\t" + Twine(CurrentFnSym->getName()));
235235 /// isBlockOnlyReachableByFallthough - Return true if the basic block has
236236 /// exactly one predecessor and the control transfer mechanism between
237237 /// the predecessor and this block is a fall-through.
238 bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB)
238 bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB)
239239 const {
240240 // The predecessor has to be immediately before this block.
241241 const MachineBasicBlock *Pred = *MBB->pred_begin();
245245 if (const BasicBlock *bb = Pred->getBasicBlock())
246246 if (isa(bb->getTerminator()))
247247 return false;
248
248
249249 return AsmPrinter::isBlockOnlyReachableByFallthrough(MBB);
250250 }
251251
252252 // Print out an operand for an inline asm expression.
253 bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
253 bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
254254 unsigned AsmVariant,const char *ExtraCode,
255255 raw_ostream &O) {
256256 // Does this asm operand have a single letter operand modifier?
257 if (ExtraCode && ExtraCode[0])
257 if (ExtraCode && ExtraCode[0])
258258 return true; // Unknown modifier.
259259
260260 printOperand(MI, OpNo, O);
286286 if (MI->getOpcode() == Mips::LUi)
287287 O << "%hi(";
288288 else
289 O << "%lo(";
289 O << "%lo(";
290290 break;
291291 }
292292
322322 if (MO.getOffset())
323323 O << "+" << MO.getOffset();
324324 break;
325
325
326326 default:
327327 llvm_unreachable("");
328328 }
335335 const MachineOperand &MO = MI->getOperand(opNum);
336336 if (MO.isImm())
337337 O << (unsigned short int)MO.getImm();
338 else
338 else
339339 printOperand(MI, opNum, O);
340340 }
341341
351351 return;
352352 }
353353
354 // Load/Store memory operands -- imm($reg)
355 // If PIC target the target is loaded as the
354 // Load/Store memory operands -- imm($reg)
355 // If PIC target the target is loaded as the
356356 // pattern lw $25,%call16($28)
357357 printOperand(MI, opNum, O);
358358 O << "(";
364364 printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
365365 const char *Modifier) {
366366 const MachineOperand& MO = MI->getOperand(opNum);
367 O << Mips::MipsFCCToString((Mips::CondCode)MO.getImm());
367 O << Mips::MipsFCCToString((Mips::CondCode)MO.getImm());
368368 }
369369
370370 void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) {
371371 // FIXME: Use SwitchSection.
372
372
373373 // Tell the assembler which ABI we are using
374374 OutStreamer.EmitRawText("\t.section .mdebug." + Twine(getCurrentABIString()));
375375
382382 }
383383
384384 // return to previous section
385 OutStreamer.EmitRawText(StringRef("\t.previous"));
385 OutStreamer.EmitRawText(StringRef("\t.previous"));
386386 }
387387
388388 // Force static initialization.
389 extern "C" void LLVMInitializeMipsAsmPrinter() {
389 extern "C" void LLVMInitializeMipsAsmPrinter() {
390390 RegisterAsmPrinter X(TheMipsTarget);
391391 RegisterAsmPrinter Y(TheMipselTarget);
392392 }
0 //===- MipsCallingConv.td - Calling Conventions for Mips ---*- tablegen -*-===//
1 //
1 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
6 //
6 //
77 //===----------------------------------------------------------------------===//
88 // This describes the calling conventions for Mips architecture.
99 //===----------------------------------------------------------------------===//
1010
1111 /// CCIfSubtarget - Match if the current subtarget has a feature F.
12 class CCIfSubtarget:
12 class CCIfSubtarget:
1313 CCIf().", F), A>;
1414
1515 //===----------------------------------------------------------------------===//
1616 // Mips O32 Calling Convention
1717 //===----------------------------------------------------------------------===//
1818
19 // Only the return rules are defined here for O32. The rules for argument
19 // Only the return rules are defined here for O32. The rules for argument
2020 // passing are defined in MipsISelLowering.cpp.
2121 def RetCC_MipsO32 : CallingConv<[
2222 // i32 are returned in registers V0, V1
4040 // Integer arguments are passed in integer registers.
4141 CCIfType<[i32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3]>>,
4242
43 // Single fp arguments are passed in pairs within 32-bit mode
44 CCIfType<[f32], CCIfSubtarget<"isSingleFloat()",
43 // Single fp arguments are passed in pairs within 32-bit mode
44 CCIfType<[f32], CCIfSubtarget<"isSingleFloat()",
4545 CCAssignToReg<[F12, F13, F14, F15, F16, F17, F18, F19]>>>,
4646
47 CCIfType<[f32], CCIfSubtarget<"isNotSingleFloat()",
47 CCIfType<[f32], CCIfSubtarget<"isNotSingleFloat()",
4848 CCAssignToReg<[F12, F14, F16, F18]>>>,
4949
5050 // The first 4 doubl fp arguments are passed in single fp registers.
51 CCIfType<[f64], CCIfSubtarget<"isNotSingleFloat()",
51 CCIfType<[f64], CCIfSubtarget<"isNotSingleFloat()",
5252 CCAssignToReg<[D6, D7, D8, D9]>>>,
5353
5454 // Integer values get stored in stack slots that are 4 bytes in
5151 /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
5252 /// make the right decision when generating code for different targets.
5353 const MipsSubtarget &Subtarget;
54
54
5555 public:
5656 explicit MipsDAGToDAGISel(MipsTargetMachine &tm) :
5757 SelectionDAGISel(tm),
5858 TM(tm), Subtarget(tm.getSubtarget()) {}
59
59
6060 // Pass Name
6161 virtual const char *getPassName() const {
6262 return "MIPS DAG->DAG Pattern Instruction Selection";
63 }
64
65
66 private:
63 }
64
65
66 private:
6767 // Include the pieces autogenerated from the target description.
6868 #include "MipsGenDAGISel.inc"
6969
115115 Offset = CurDAG->getTargetConstant(0, MVT::i32);
116116 return true;
117117 }
118
118
119119 // on PIC code Load GA
120120 if (TM.getRelocationModel() == Reloc::PIC_) {
121 if ((Addr.getOpcode() == ISD::TargetGlobalAddress) ||
122 (Addr.getOpcode() == ISD::TargetConstantPool) ||
121 if ((Addr.getOpcode() == ISD::TargetGlobalAddress) ||
122 (Addr.getOpcode() == ISD::TargetConstantPool) ||
123123 (Addr.getOpcode() == ISD::TargetJumpTable)){
124124 Base = CurDAG->getRegister(Mips::GP, MVT::i32);
125125 Offset = Addr;
129129 if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
130130 Addr.getOpcode() == ISD::TargetGlobalAddress))
131131 return false;
132 }
133
132 }
133
134134 // Operand is a result from an ADD.
135135 if (Addr.getOpcode() == ISD::ADD) {
136136 if (ConstantSDNode *CN = dyn_cast(Addr.getOperand(1))) {
157157 // Generate:
158158 // lui $2, %hi($CPI1_0)
159159 // lwc1 $f0, %lo($CPI1_0)($2)
160 if ((Addr.getOperand(0).getOpcode() == MipsISD::Hi ||
160 if ((Addr.getOperand(0).getOpcode() == MipsISD::Hi ||
161161 Addr.getOperand(0).getOpcode() == ISD::LOAD) &&
162162 Addr.getOperand(1).getOpcode() == MipsISD::Lo) {
163 SDValue LoVal = Addr.getOperand(1);
163 SDValue LoVal = Addr.getOperand(1);
164164 if (dyn_cast(LoVal.getOperand(0))) {
165165 Base = Addr.getOperand(0);
166166 Offset = LoVal.getOperand(0);
175175 }
176176
177177 SDNode *MipsDAGToDAGISel::SelectLoadFp64(SDNode *N) {
178 MVT::SimpleValueType NVT =
178 MVT::SimpleValueType NVT =
179179 N->getValueType(0).getSimpleVT().SimpleTy;
180180
181181 if (!Subtarget.isMips1() || NVT != MVT::f64)
198198 MemRefs0[0] = cast(N)->getMemOperand();
199199 DebugLoc dl = N->getDebugLoc();
200200
201 // The second load should start after for 4 bytes.
201 // The second load should start after for 4 bytes.
202202 if (ConstantSDNode *C = dyn_cast(Offset0))
203203 Offset1 = CurDAG->getTargetConstant(C->getSExtValue()+4, MVT::i32);
204204 else if (ConstantPoolSDNode *CP = dyn_cast(Offset0))
205 Offset1 = CurDAG->getTargetConstantPool(CP->getConstVal(),
206 MVT::i32,
207 CP->getAlignment(),
208 CP->getOffset()+4,
205 Offset1 = CurDAG->getTargetConstantPool(CP->getConstVal(),
206 MVT::i32,
207 CP->getAlignment(),
208 CP->getOffset()+4,
209209 CP->getTargetFlags());
210210 else
211211 return NULL;
219219 // Generate:
220220 // lwc $f0, X($3)
221221 // lwc $f1, X+4($3)
222 SDNode *LD0 = CurDAG->getMachineNode(Mips::LWC1, dl, MVT::f32,
222 SDNode *LD0 = CurDAG->getMachineNode(Mips::LWC1, dl, MVT::f32,
223223 MVT::Other, Offset0, Base, Chain);
224224 SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
225225 dl, NVT), 0);
226 SDValue I0 = CurDAG->getTargetInsertSubreg(Mips::sub_fpeven, dl,
226 SDValue I0 = CurDAG->getTargetInsertSubreg(Mips::sub_fpeven, dl,
227227 MVT::f64, Undef, SDValue(LD0, 0));
228228
229229 SDNode *LD1 = CurDAG->getMachineNode(Mips::LWC1, dl, MVT::f32,
230230 MVT::Other, Offset1, Base, SDValue(LD0, 1));
231 SDValue I1 = CurDAG->getTargetInsertSubreg(Mips::sub_fpodd, dl,
231 SDValue I1 = CurDAG->getTargetInsertSubreg(Mips::sub_fpodd, dl,
232232 MVT::f64, I0, SDValue(LD1, 0));
233233
234234 ReplaceUses(SDValue(N, 0), I1);
240240
241241 SDNode *MipsDAGToDAGISel::SelectStoreFp64(SDNode *N) {
242242
243 if (!Subtarget.isMips1() ||
243 if (!Subtarget.isMips1() ||
244244 N->getOperand(1).getValueType() != MVT::f64)
245245 return NULL;
246246
264264 DebugLoc dl = N->getDebugLoc();
265265
266266 // Get the even and odd part from the f64 register
267 SDValue FPOdd = CurDAG->getTargetExtractSubreg(Mips::sub_fpodd,
267 SDValue FPOdd = CurDAG->getTargetExtractSubreg(Mips::sub_fpodd,
268268 dl, MVT::f32, N1);
269269 SDValue FPEven = CurDAG->getTargetExtractSubreg(Mips::sub_fpeven,
270270 dl, MVT::f32, N1);
271271
272 // The second store should start after for 4 bytes.
272 // The second store should start after for 4 bytes.
273273 if (ConstantSDNode *C = dyn_cast(Offset0))
274274 Offset1 = CurDAG->getTargetConstant(C->getSExtValue()+4, MVT::i32);
275275 else
314314 }
315315
316316 ///
317 // Instruction Selection not handled by the auto-generated
317 // Instruction Selection not handled by the auto-generated
318318 // tablegen selection should be handled here.
319 ///
319 ///
320320 switch(Opcode) {
321321
322322 default: break;
323323
324 case ISD::SUBE:
324 case ISD::SUBE:
325325 case ISD::ADDE: {
326326 SDValue InFlag = Node->getOperand(2), CmpLHS;
327327 unsigned Opc = InFlag.getOpcode(); (void)Opc;
328 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
329 (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
328 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
329 (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
330330 "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
331331
332332 unsigned MOp;
333333 if (Opcode == ISD::ADDE) {
334334 CmpLHS = InFlag.getValue(0);
335335 MOp = Mips::ADDu;
336 } else {
336 } else {
337337 CmpLHS = InFlag.getOperand(0);
338338 MOp = Mips::SUBu;
339339 }
345345
346346 EVT VT = LHS.getValueType();
347347 SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, dl, VT, Ops, 2);
348 SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, dl, VT,
348 SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, dl, VT,
349349 SDValue(Carry,0), RHS);
350350
351351 return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue,
369369 SDNode *MulDiv = CurDAG->getMachineNode(Op, dl, MVT::Glue, Op1, Op2);
370370
371371 SDValue InFlag = SDValue(MulDiv, 0);
372 SDNode *Lo = CurDAG->getMachineNode(Mips::MFLO, dl, MVT::i32,
372 SDNode *Lo = CurDAG->getMachineNode(Mips::MFLO, dl, MVT::i32,
373373 MVT::Glue, InFlag);
374374 InFlag = SDValue(Lo,1);
375375 SDNode *Hi = CurDAG->getMachineNode(Mips::MFHI, dl, MVT::i32, InFlag);
376376
377 if (!SDValue(Node, 0).use_empty())
377 if (!SDValue(Node, 0).use_empty())
378378 ReplaceUses(SDValue(Node, 0), SDValue(Lo,0));
379379
380 if (!SDValue(Node, 1).use_empty())
380 if (!SDValue(Node, 1).use_empty())
381381 ReplaceUses(SDValue(Node, 1), SDValue(Hi,0));
382382
383383 return NULL;
384384 }
385385
386386 /// Special Muls
387 case ISD::MUL:
387 case ISD::MUL:
388388 if (Subtarget.isMips32())
389389 break;
390390 case ISD::MULHS:
393393 SDValue MulOp2 = Node->getOperand(1);
394394
395395 unsigned MulOp = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT);
396 SDNode *MulNode = CurDAG->getMachineNode(MulOp, dl,
396 SDNode *MulNode = CurDAG->getMachineNode(MulOp, dl,
397397 MVT::Glue, MulOp1, MulOp2);
398398
399399 SDValue InFlag = SDValue(MulNode, 0);
407407 /// Div/Rem operations
408408 case ISD::SREM:
409409 case ISD::UREM:
410 case ISD::SDIV:
410 case ISD::SDIV:
411411 case ISD::UDIV: {
412412 SDValue Op1 = Node->getOperand(0);
413413 SDValue Op2 = Node->getOperand(1);
432432
433433 case ISD::ConstantFP: {
434434 ConstantFPSDNode *CN = dyn_cast(Node);
435 if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
436 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
435 if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
436 SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
437437 Mips::ZERO, MVT::i32);
438438 SDValue Undef = SDValue(
439439 CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, MVT::f64), 0);
440440 SDNode *MTC = CurDAG->getMachineNode(Mips::MTC1, dl, MVT::f32, Zero);
441 SDValue I0 = CurDAG->getTargetInsertSubreg(Mips::sub_fpeven, dl,
441 SDValue I0 = CurDAG->getTargetInsertSubreg(Mips::sub_fpeven, dl,
442442 MVT::f64, Undef, SDValue(MTC, 0));
443 SDValue I1 = CurDAG->getTargetInsertSubreg(Mips::sub_fpodd, dl,
443 SDValue I1 = CurDAG->getTargetInsertSubreg(Mips::sub_fpodd, dl,
444444 MVT::f64, I0, SDValue(MTC, 0));
445445 ReplaceUses(SDValue(Node, 0), I1);
446446 return I1.getNode();
460460 // Other cases are autogenerated.
461461 break;
462462
463 /// Handle direct and indirect calls when using PIC. On PIC, when
464 /// GOT is smaller than about 64k (small code) the GA target is
465 /// loaded with only one instruction. Otherwise GA's target must
466 /// be loaded with 3 instructions.
463 /// Handle direct and indirect calls when using PIC. On PIC, when
464 /// GOT is smaller than about 64k (small code) the GA target is
465 /// loaded with only one instruction. Otherwise GA's target must
466 /// be loaded with 3 instructions.
467467 case MipsISD::JmpLink: {
468468 if (TM.getRelocationModel() == Reloc::PIC_) {
469469 unsigned LastOpNum = Node->getNumOperands()-1;
484484
485485 // Use load to get GOT target
486486 SDValue Ops[] = { Callee, GPReg, Chain };
487 SDValue Load = SDValue(CurDAG->getMachineNode(Mips::LW, dl, MVT::i32,
487 SDValue Load = SDValue(CurDAG->getMachineNode(Mips::LW, dl, MVT::i32,
488488 MVT::Other, Ops, 3), 0);
489489 Chain = Load.getValue(1);
490490
491491 // Call target must be on T9
492492 Chain = CurDAG->getCopyToReg(Chain, dl, Mips::T9, Load, InFlag);
493 } else
493 } else
494494 /// Indirect call
495495 Chain = CurDAG->getCopyToReg(Chain, dl, Mips::T9, Callee, InFlag);
496496
505505 Ops.push_back(Chain.getValue(1));
506506
507507 // Emit Jump and Link Register
508 SDNode *ResNode = CurDAG->getMachineNode(Mips::JALR, dl, NodeTys,
508 SDNode *ResNode = CurDAG->getMachineNode(Mips::JALR, dl, NodeTys,
509509 &Ops[0], Ops.size());
510510
511511 // Replace Chain and InFlag
512512 ReplaceUses(SDValue(Node, 0), SDValue(ResNode, 0));
513513 ReplaceUses(SDValue(Node, 1), SDValue(ResNode, 1));
514514 return ResNode;
515 }
515 }
516516 }
517517 }
518518
528528 return ResNode;
529529 }
530530
531 /// createMipsISelDag - This pass converts a legalized DAG into a
531 /// createMipsISelDag - This pass converts a legalized DAG into a
532532 /// MIPS-specific DAG, ready for instruction scheduling.
533533 FunctionPass *llvm::createMipsISelDag(MipsTargetMachine &TM) {
534534 return new MipsDAGToDAGISel(TM);
3030
3131 // Get the Higher 16 bits from a 32-bit immediate
3232 // No relation with Mips Hi register
33 Hi,
33 Hi,
3434
3535 // Get the Lower 16 bits from a 32-bit immediate
3636 // No relation with Mips Lo register
37 Lo,
37 Lo,
3838
3939 // Handle gp_rel (small data/bss sections) relocation.
4040 GPRel,
5454 // Floating Point Rounding
5555 FPRound,
5656
57 // Return
57 // Return
5858 Ret,
5959
6060 // MAdd/Sub nodes
6868 //===--------------------------------------------------------------------===//
6969 // TargetLowering Implementation
7070 //===--------------------------------------------------------------------===//
71
71
7272 class MipsTargetLowering : public TargetLowering {
7373 public:
7474 explicit MipsTargetLowering(MipsTargetMachine &TM);
7676 /// LowerOperation - Provide custom lowering hooks for some operations.
7777 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
7878
79 /// getTargetNodeName - This method returns the name of a target specific
79 /// getTargetNodeName - This method returns the name of a target specific
8080 // DAG node.
8181 virtual const char *getTargetNodeName(unsigned Opcode) const;
8282
8686 /// getFunctionAlignment - Return the Log2 alignment of this function.
8787 virtual unsigned getFunctionAlignment(const Function *F) const;
8888
89 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
89 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
9090 private:
9191 // Subtarget Info
9292 const MipsSubtarget *Subtarget;
148148 ConstraintWeight getSingleConstraintMatchWeight(
149149 AsmOperandInfo &info, const char *constraint) const;
150150
151 std::pair
151 std::pair
152152 getRegForInlineAsmConstraint(const std::string &Constraint,
153153 EVT VT) const;
154154
2626 def SDT_MipsFPBrcond : SDTypeProfile<0, 3, [SDTCisSameAs<0, 2>, SDTCisInt<0>,
2727 SDTCisVT<1, OtherVT>]>;
2828 def SDT_MipsFPCmp : SDTypeProfile<1, 3, [SDTCisVT<0, i32>,
29 SDTCisSameAs<1, 2>, SDTCisFP<1>,
29 SDTCisSameAs<1, 2>, SDTCisFP<1>,
3030 SDTCisInt<3>]>;
3131 def SDT_MipsFPSelectCC : SDTypeProfile<1, 4, [SDTCisInt<1>, SDTCisInt<4>,
3232 SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>]>;
3333
3434 def MipsFPRound : SDNode<"MipsISD::FPRound", SDTFPRoundOp, [SDNPOptInGlue]>;
35 def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond,
36 [SDNPHasChain]>;
35 def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond,
36 [SDNPHasChain]>;
3737 def MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp>;
3838 def MipsFPSelectCC : SDNode<"MipsISD::FPSelectCC", SDT_MipsFPSelectCC>;
3939
5353 //===----------------------------------------------------------------------===//
5454 // Instruction Class Templates
5555 //
56 // A set of multiclasses is used to address the register usage.
56 // A set of multiclasses is used to address the register usage.
5757 //
5858 // S32 - single precision in 16 32bit even fp registers
5959 // single precision in 32 32bit fp registers in SingleOnly mode
6464 // Only S32 and D32 are supported right now.
6565 //===----------------------------------------------------------------------===//
6666
67 multiclass FFR1_1 funct, string asmstr>
67 multiclass FFR1_1 funct, string asmstr>
6868 {
6969 def _S32 : FFR<0x11, funct, 0x0, (outs FGR32:$fd), (ins FGR32:$fs),
7070 !strconcat(asmstr, ".s $fd, $fs"), []>;
7373 !strconcat(asmstr, ".d $fd, $fs"), []>, Requires<[In32BitMode]>;
7474 }
7575
76 multiclass FFR1_2 funct, string asmstr, SDNode FOp>
76 multiclass FFR1_2 funct, string asmstr, SDNode FOp>
7777 {
7878 def _S32 : FFR<0x11, funct, 0x0, (outs FGR32:$fd), (ins FGR32:$fs),
79 !strconcat(asmstr, ".s $fd, $fs"),
79 !strconcat(asmstr, ".s $fd, $fs"),
8080 [(set FGR32:$fd, (FOp FGR32:$fs))]>;
8181
8282 def _D32 : FFR<0x11, funct, 0x1, (outs AFGR64:$fd), (ins AFGR64:$fs),
83 !strconcat(asmstr, ".d $fd, $fs"),
83 !strconcat(asmstr, ".d $fd, $fs"),
8484 [(set AFGR64:$fd, (FOp AFGR64:$fs))]>, Requires<[In32BitMode]>;
8585 }
8686
87 class FFR1_3 funct, bits<5> fmt, RegisterClass RcSrc,
88 RegisterClass RcDst, string asmstr>:
89 FFR<0x11, funct, fmt, (outs RcSrc:$fd), (ins RcDst:$fs),
90 !strconcat(asmstr, " $fd, $fs"), []>;
87 class FFR1_3 funct, bits<5> fmt, RegisterClass RcSrc,
88 RegisterClass RcDst, string asmstr>:
89 FFR<0x11, funct, fmt, (outs RcSrc:$fd), (ins RcDst:$fs),
90 !strconcat(asmstr, " $fd, $fs"), []>;
9191
9292
9393 multiclass FFR1_4 funct, string asmstr, SDNode FOp> {
94 def _S32 : FFR<0x11, funct, 0x0, (outs FGR32:$fd),
95 (ins FGR32:$fs, FGR32:$ft),
94 def _S32 : FFR<0x11, funct, 0x0, (outs FGR32:$fd),
95 (ins FGR32:$fs, FGR32:$ft),
9696 !strconcat(asmstr, ".s $fd, $fs, $ft"),
9797 [(set FGR32:$fd, (FOp FGR32:$fs, FGR32:$ft))]>;
9898
99 def _D32 : FFR<0x11, funct, 0x1, (outs AFGR64:$fd),
100 (ins AFGR64:$fs, AFGR64:$ft),
99 def _D32 : FFR<0x11, funct, 0x1, (outs AFGR64:$fd),
100 (ins AFGR64:$fs, AFGR64:$ft),
101101 !strconcat(asmstr, ".d $fd, $fs, $ft"),
102102 [(set AFGR64:$fd, (FOp AFGR64:$fs, AFGR64:$ft))]>,
103103 Requires<[In32BitMode]>;
114114 defm TRUNC_W : FFR1_1<0b001101, "trunc.w">;
115115 defm CVTW : FFR1_1<0b100100, "cvt.w">;
116116
117 defm FABS : FFR1_2<0b000101, "abs", fabs>;
118 defm FNEG : FFR1_2<0b000111, "neg", fneg>;
117 defm FABS : FFR1_2<0b000101, "abs", fabs>;
118 defm FNEG : FFR1_2<0b000111, "neg", fneg>;
119119 defm FSQRT : FFR1_2<0b000100, "sqrt", fsqrt>;
120120
121121 /// Convert to Single Precison
139139 def TRUNC_LD : FFR1_3<0b001001, 0x1, AFGR64, AFGR64, "trunc.l">;
140140
141141 /// Convert to long signed integer
142 def CVTL_S : FFR1_3<0b100101, 0x0, FGR32, FGR32, "cvt.l">;
143 def CVTL_D : FFR1_3<0b100101, 0x1, AFGR64, AFGR64, "cvt.l">;
144
145 /// Convert to Double Precison
146 def CVTD_S32 : FFR1_3<0b100001, 0x0, AFGR64, FGR32, "cvt.d.s">;
147 def CVTD_W32 : FFR1_3<0b100001, 0x2, AFGR64, FGR32, "cvt.d.w">;
148 def CVTD_L32 : FFR1_3<0b100001, 0x3, AFGR64, AFGR64, "cvt.d.l">;
149
142 def CVTL_S : FFR1_3<0b100101, 0x0, FGR32, FGR32, "cvt.l">;
143 def CVTL_D : FFR1_3<0b100101, 0x1, AFGR64, AFGR64, "cvt.l">;
144
145 /// Convert to Double Precison
146 def CVTD_S32 : FFR1_3<0b100001, 0x0, AFGR64, FGR32, "cvt.d.s">;
147 def CVTD_W32 : FFR1_3<0b100001, 0x2, AFGR64, FGR32, "cvt.d.w">;
148 def CVTD_L32 : FFR1_3<0b100001, 0x3, AFGR64, AFGR64, "cvt.d.l">;
149
150150 /// Convert to Single Precison
151151 def CVTS_D32 : FFR1_3<0b100000, 0x1, FGR32, AFGR64, "cvt.s.d">;
152 def CVTS_L32 : FFR1_3<0b100000, 0x3, FGR32, AFGR64, "cvt.s.l">;
152 def CVTS_L32 : FFR1_3<0b100000, 0x3, FGR32, AFGR64, "cvt.s.l">;
153153 }
154154 }
155155
156156 // The odd-numbered registers are only referenced when doing loads,
157157 // stores, and moves between floating-point and integer registers.
158 // When defining instructions, we reference all 32-bit registers,
158 // When defining instructions, we reference all 32-bit registers,
159159 // regardless of register aliasing.
160160 let fd = 0 in {
161161 /// Move Control Registers From/To CPU Registers
164164
165165 def CTC1 : FFR<0x11, 0x0, 0x6, (outs CCR:$rt), (ins CPURegs:$fs),
166166 "ctc1 $fs, $rt", []>;
167
167
168168 def MFC1 : FFR<0x11, 0x00, 0x00, (outs CPURegs:$rt), (ins FGR32:$fs),
169169 "mfc1 $rt, $fs", []>;
170170
179179
180180 /// Floating Point Memory Instructions
181181 let Predicates = [IsNotSingleFloat, IsNotMipsI] in {
182 def LDC1 : FFI<0b110101, (outs AFGR64:$ft), (ins mem:$addr),
182 def LDC1 : FFI<0b110101, (outs AFGR64:$ft), (ins mem:$addr),
183183 "ldc1 $ft, $addr", [(set AFGR64:$ft, (load addr:$addr))]>;
184184
185 def SDC1 : FFI<0b111101, (outs), (ins AFGR64:$ft, mem:$addr),
185 def SDC1 : FFI<0b111101, (outs), (ins AFGR64:$ft, mem:$addr),
186186 "sdc1 $ft, $addr", [(store AFGR64:$ft, addr:$addr)]>;
187187 }
188188
189189 // LWC1 and SWC1 can always be emited with odd registers.
190190 def LWC1 : FFI<0b110001, (outs FGR32:$ft), (ins mem:$addr), "lwc1 $ft, $addr",
191 [(set FGR32:$ft, (load addr:$addr))]>;
191 [(set FGR32:$ft, (load addr:$addr))]>;
192192 def SWC1 : FFI<0b111001, (outs), (ins FGR32:$ft, mem:$addr), "swc1 $ft, $addr",
193 [(store FGR32:$ft, addr:$addr)]>;
193 [(store FGR32:$ft, addr:$addr)]>;
194194
195195 /// Floating-point Aritmetic
196196 defm FADD : FFR1_4<0x10, "add", fadd>;
201201 //===----------------------------------------------------------------------===//
202202 // Floating Point Branch Codes
203203 //===----------------------------------------------------------------------===//
204 // Mips branch codes. These correspond to condcode in MipsInstrInfo.h.
204 // Mips branch codes. These correspond to condcode in MipsInstrInfo.h.
205205 // They must be kept in synch.
206206 def MIPS_BRANCH_F : PatLeaf<(i32 0)>;
207207 def MIPS_BRANCH_T : PatLeaf<(i32 1)>;
210210
211211 /// Floating Point Branch of False/True (Likely)
212212 let isBranch=1, isTerminator=1, hasDelaySlot=1, base=0x8, Uses=[FCR31] in {
213 class FBRANCH : FFI<0x11, (outs),
213 class FBRANCH : FFI<0x11, (outs),
214214 (ins brtarget:$dst), !strconcat(asmstr, " $dst"),
215215 [(MipsFPBrcond op, bb:$dst, FCR31)]>;
216216 }
222222 //===----------------------------------------------------------------------===//
223223 // Floating Point Flag Conditions
224224 //===----------------------------------------------------------------------===//
225 // Mips condition codes. They must correspond to condcode in MipsInstrInfo.h.
225 // Mips condition codes. They must correspond to condcode in MipsInstrInfo.h.
226226 // They must be kept in synch.
227227 def MIPS_FCOND_F : PatLeaf<(i32 0)>;
228228 def MIPS_FCOND_UN : PatLeaf<(i32 1)>;
245245 let hasDelaySlot = 1, Defs=[FCR31] in {
246246 def FCMP_S32 : FCC<0x0, (outs), (ins FGR32:$fs, FGR32:$ft, condcode:$cc),
247247 "c.$cc.s $fs, $ft",
248 [(set FCR31, (MipsFPCmp FGR32:$fs, FGR32:$ft, imm:$cc))]>;
249
248 [(set FCR31, (MipsFPCmp FGR32:$fs, FGR32:$ft, imm:$cc))]>;
249
250250 def FCMP_D32 : FCC<0x1, (outs), (ins AFGR64:$fs, AFGR64:$ft, condcode:$cc),
251251 "c.$cc.d $fs, $ft",
252252 [(set FCR31, (MipsFPCmp AFGR64:$fs, AFGR64:$ft, imm:$cc))]>,
257257 // Floating Point Pseudo-Instructions
258258 //===----------------------------------------------------------------------===//
259259
260 // For some explanation, see Select_CC at MipsInstrInfo.td. We also embedd a
260 // For some explanation, see Select_CC at MipsInstrInfo.td. We also embedd a
261261 // condiciton code to enable easy handling by the Custom Inserter.
262262 let usesCustomInserter = 1, Uses=[FCR31] in {
263 class PseudoFPSelCC :
264 MipsPseudo<(outs RC:$dst),
265 (ins CPURegs:$CmpRes, RC:$T, RC:$F, condcode:$cc), asmstr,
263 class PseudoFPSelCC :
264 MipsPseudo<(outs RC:$dst),
265 (ins CPURegs:$CmpRes, RC:$T, RC:$F, condcode:$cc), asmstr,
266266 [(set RC:$dst, (MipsFPSelectCC CPURegs:$CmpRes, RC:$T, RC:$F,
267267 imm:$cc))]>;
268268 }
277277
278278 // The values to be selected and the condition test is done with fp.
279279 def Select_FCC_S32 : PseudoFPSelCC;
280 def Select_FCC_D32 : PseudoFPSelCC,
280 def Select_FCC_D32 : PseudoFPSelCC,
281281 Requires<[In32BitMode]>;
282282
283 def MOVCCRToCCR : MipsPseudo<(outs CCR:$dst), (ins CCR:$src),
284 "# MOVCCRToCCR", []>;
283 def MOVCCRToCCR : MipsPseudo<(outs CCR:$dst), (ins CCR:$src),
284 "# MOVCCRToCCR", []>;
285285
286286 //===----------------------------------------------------------------------===//
287287 // Floating Point Patterns
305305 def : Pat<(i32 (bitconvert FGR32:$src)), (MFC1 FGR32:$src)>;
306306 def : Pat<(f32 (bitconvert CPURegs:$src)), (MTC1 CPURegs:$src)>;
307307
308 let Predicates = [In32BitMode] in {
308 let Predicates = [In32BitMode] in {
309309 def : Pat<(f32 (fround AFGR64:$src)), (CVTS_D32 AFGR64:$src)>;
310310 def : Pat<(f64 (fextend FGR32:$src)), (CVTD_S32 FGR32:$src)>;
311311 }
2121 //===----------------------------------------------------------------------===//
2222
2323 // Generic Mips Format
24 class MipsInst pattern,
25 InstrItinClass itin>: Instruction
24 class MipsInst pattern,
25 InstrItinClass itin>: Instruction
2626 {
2727 field bits<32> Inst;
2828
3131 bits<6> opcode;
3232
3333 // Top 5 bits are the 'opcode' field
34 let Inst{31-26} = opcode;
35
34 let Inst{31-26} = opcode;
35
3636 dag OutOperandList = outs;
3737 dag InOperandList = ins;
3838
5151
5252 class FR op, bits<6> _funct, dag outs, dag ins, string asmstr,
5353 list pattern, InstrItinClass itin>:
54 MipsInst
54 MipsInst
5555 {
5656 bits<5> rd;
5757 bits<5> rs;
6363 let funct = _funct;
6464
6565 let Inst{25-21} = rs;
66 let Inst{20-16} = rt;
66 let Inst{20-16} = rt;
6767 let Inst{15-11} = rd;
6868 let Inst{10-6} = shamt;
6969 let Inst{5-0} = funct;
7474 //===----------------------------------------------------------------------===//
7575
7676 class FI op, dag outs, dag ins, string asmstr, list pattern,
77 InstrItinClass itin>: MipsInst
77 InstrItinClass itin>: MipsInst
7878 {
7979 bits<5> rt;
8080 bits<5> rs;
8383 let opcode = op;
8484
8585 let Inst{25-21} = rs;
86 let Inst{20-16} = rt;
86 let Inst{20-16} = rt;
8787 let Inst{15-0} = imm16;
8888 }
8989
9292 //===----------------------------------------------------------------------===//
9393
9494 class FJ op, dag outs, dag ins, string asmstr, list pattern,
95 InstrItinClass itin>: MipsInst
95 InstrItinClass itin>: MipsInst
9696 {
9797 bits<26> addr;
9898
9999 let opcode = op;
100
100
101101 let Inst{25-0} = addr;
102102 }
103103
118118 // Format FR instruction class in Mips : <|opcode|fmt|ft|fs|fd|funct|>
119119 //===----------------------------------------------------------------------===//
120120
121 class FFR op, bits<6> _funct, bits<5> _fmt, dag outs, dag ins,
122 string asmstr, list pattern> :
123 MipsInst
121 class FFR op, bits<6> _funct, bits<5> _fmt, dag outs, dag ins,
122 string asmstr, list pattern> :
123 MipsInst
124124 {
125125 bits<5> fd;
126126 bits<5> fs;
133133 let fmt = _fmt;
134134
135135 let Inst{25-21} = fmt;
136 let Inst{20-16} = ft;
136 let Inst{20-16} = ft;
137137 let Inst{15-11} = fs;
138138 let Inst{10-6} = fd;
139139 let Inst{5-0} = funct;
143143 // Format FI instruction class in Mips : <|opcode|base|ft|immediate|>
144144 //===----------------------------------------------------------------------===//
145145
146 class FFI op, dag outs, dag ins, string asmstr, list pattern>:
147 MipsInst
146 class FFI op, dag outs, dag ins, string asmstr, list pattern>:
147 MipsInst
148148 {
149149 bits<5> ft;
150150 bits<5> base;
153153 let opcode = op;
154154
155155 let Inst{25-21} = base;
156 let Inst{20-16} = ft;
156 let Inst{20-16} = ft;
157157 let Inst{15-0} = imm16;
158158 }
159159
161161 // Compare instruction class in Mips : <|010001|fmt|ft|fs|0000011|condcode|>
162162 //===----------------------------------------------------------------------===//
163163
164 class FCC _fmt, dag outs, dag ins, string asmstr, list pattern> :
165 MipsInst
164 class FCC _fmt, dag outs, dag ins, string asmstr, list pattern> :
165 MipsInst
166166 {
167167 bits<5> fs;
168168 bits<5> ft;
173173 let fmt = _fmt;
174174
175175 let Inst{25-21} = fmt;
176 let Inst{20-16} = ft;
176 let Inst{20-16} = ft;
177177 let Inst{15-11} = fs;
178178 let Inst{10-6} = 0;
179179 let Inst{5-4} = 0b11;
3535 /// not, return 0. This predicate must return 0 if the instruction has
3636 /// any side effects other than loading from the stack slot.
3737 unsigned MipsInstrInfo::
38 isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
38 isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
3939 {
4040 if ((MI->getOpcode() == Mips::LW) || (MI->getOpcode() == Mips::LWC1) ||
4141 (MI->getOpcode() == Mips::LDC1)) {
5656 /// not, return 0. This predicate must return 0 if the instruction has
5757 /// any side effects other than storing to the stack slot.
5858 unsigned MipsInstrInfo::
59 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
59 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
6060 {
6161 if ((MI->getOpcode() == Mips::SW) || (MI->getOpcode() == Mips::SWC1) ||
6262 (MI->getOpcode() == Mips::SDC1)) {
7373 /// insertNoop - If data hazard condition is found insert the target nop
7474 /// instruction.
7575 void MipsInstrInfo::
76 insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
76 insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
7777 {
7878 DebugLoc DL;
7979 BuildMI(MBB, MI, DL, get(Mips::NOP));
135135 .addReg(SrcReg, getKillRegState(KillSrc));
136136 return;
137137 }
138
138
139139 if (Mips::AFGR64RegClass.contains(DestReg, SrcReg)) {
140140 BuildMI(MBB, I, DL, get(Mips::FMOV_D32), DestReg)
141141 .addReg(SrcReg, getKillRegState(KillSrc));
152152
153153 void MipsInstrInfo::
154154 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
155 unsigned SrcReg, bool isKill, int FI,
155 unsigned SrcReg, bool isKill, int FI,
156156 const TargetRegisterClass *RC,
157157 const TargetRegisterInfo *TRI) const {
158158 DebugLoc DL;
159159 if (I != MBB.end()) DL = I->getDebugLoc();
160160
161 if (RC == Mips::CPURegsRegisterClass)
161 if (RC == Mips::CPURegsRegisterClass)
162162 BuildMI(MBB, I, DL, get(Mips::SW)).addReg(SrcReg, getKillRegState(isKill))
163163 .addImm(0).addFrameIndex(FI);
164164 else if (RC == Mips::FGR32RegisterClass)
170170 .addReg(SrcReg, getKillRegState(isKill))
171171 .addImm(0).addFrameIndex(FI);
172172 } else {
173 const TargetRegisterInfo *TRI =
173 const TargetRegisterInfo *TRI =
174174 MBB.getParent()->getTarget().getRegisterInfo();
175175 const unsigned *SubSet = TRI->getSubRegisters(SrcReg);
176176 BuildMI(MBB, I, DL, get(Mips::SWC1))
188188 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
189189 unsigned DestReg, int FI,
190190 const TargetRegisterClass *RC,
191 const TargetRegisterInfo *TRI) const
191 const TargetRegisterInfo *TRI) const
192192 {
193193 DebugLoc DL;
194194 if (I != MBB.end()) DL = I->getDebugLoc();
195195
196 if (RC == Mips::CPURegsRegisterClass)
196 if (RC == Mips::CPURegsRegisterClass)
197197 BuildMI(MBB, I, DL, get(Mips::LW), DestReg).addImm(0).addFrameIndex(FI);
198198 else if (RC == Mips::FGR32RegisterClass)
199199 BuildMI(MBB, I, DL, get(Mips::LWC1), DestReg).addImm(0).addFrameIndex(FI);
201201 if (!TM.getSubtarget().isMips1()) {
202202 BuildMI(MBB, I, DL, get(Mips::LDC1), DestReg).addImm(0).addFrameIndex(FI);
203203 } else {
204 const TargetRegisterInfo *TRI =
204 const TargetRegisterInfo *TRI =
205205 MBB.getParent()->getTarget().getRegisterInfo();
206206 const unsigned *SubSet = TRI->getSubRegisters(DestReg);
207207 BuildMI(MBB, I, DL, get(Mips::LWC1), SubSet[0])
217217 // Branch Analysis
218218 //===----------------------------------------------------------------------===//
219219
220 /// GetCondFromBranchOpc - Return the Mips CC that matches
220 /// GetCondFromBranchOpc - Return the Mips CC that matches
221221 /// the correspondent Branch instruction opcode.
222 static Mips::CondCode GetCondFromBranchOpc(unsigned BrOpc)
222 static Mips::CondCode GetCondFromBranchOpc(unsigned BrOpc)
223223 {
224224 switch (BrOpc) {
225225 default: return Mips::COND_INVALID;
230230 case Mips::BLTZ : return Mips::COND_LZ;
231231 case Mips::BLEZ : return Mips::COND_LEZ;
232232
233 // We dont do fp branch analysis yet!
234 case Mips::BC1T :
233 // We dont do fp branch analysis yet!
234 case Mips::BC1T :
235235 case Mips::BC1F : return Mips::COND_INVALID;
236236 }
237237 }
238238
239239 /// GetCondBranchFromCond - Return the Branch instruction
240240 /// opcode that matches the cc.
241 unsigned Mips::GetCondBranchFromCond(Mips::CondCode CC)
241 unsigned Mips::GetCondBranchFromCond(Mips::CondCode CC)
242242 {
243243 switch (CC) {
244244 default: llvm_unreachable("Illegal condition code!");
285285 }
286286 }
287287
288 /// GetOppositeBranchCondition - Return the inverse of the specified
288 /// GetOppositeBranchCondition - Return the inverse of the specified
289289 /// condition, e.g. turning COND_E to COND_NE.
290 Mips::CondCode Mips::GetOppositeBranchCondition(Mips::CondCode CC)
290 Mips::CondCode Mips::GetOppositeBranchCondition(Mips::CondCode CC)
291291 {
292292 switch (CC) {
293293 default: llvm_unreachable("Illegal condition code!");
316316 }
317317 }
318318
319 bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
319 bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
320320 MachineBasicBlock *&TBB,
321321 MachineBasicBlock *&FBB,
322322 SmallVectorImpl &Cond,
323 bool AllowModify) const
323 bool AllowModify) const
324324 {
325325 // If the block has no terminators, it just falls into the block after it.
326326 MachineBasicBlock::iterator I = MBB.end();
334334 }
335335 if (!isUnpredicatedTerminator(I))
336336 return false;
337
337
338338 // Get the last instruction in the block.
339339 MachineInstr *LastInst = I;
340
340
341341 // If there is only one terminator instruction, process it.
342342 unsigned LastOpc = LastInst->getOpcode();
343343 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
369369 return false;
370370 }
371371 }
372
372
373373 // Get the instruction before it if it is a terminator.
374374 MachineInstr *SecondLastInst = I;
375
375
376376 // If there are three terminators, we don't know what sort of block this is.
377377 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
378378 return true;
394394 FBB = LastInst->getOperand(0).getMBB();
395395 return false;
396396 }
397
398 // If the block ends with two unconditional branches, handle it. The last
397
398 // If the block ends with two unconditional branches, handle it. The last
399399 // one is not executed, so remove it.
400400 if ((SecondLastOpc == Mips::J) && (LastOpc == Mips::J)) {
401401 TBB = SecondLastInst->getOperand(0).getMBB();
410410 }
411411
412412 unsigned MipsInstrInfo::
413 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
413 InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
414414 MachineBasicBlock *FBB,
415415 const SmallVectorImpl &Cond,
416416 DebugLoc DL) const {
436436 BuildMI(&MBB, DL, TID).addReg(Cond[1].getReg())
437437 .addMBB(TBB);
438438
439 }
439 }
440440 return 1;
441441 }
442
442
443443 // Two-way Conditional branch.
444444 unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
445445 const TargetInstrDesc &TID = get(Opc);
455455 }
456456
457457 unsigned MipsInstrInfo::
458 RemoveBranch(MachineBasicBlock &MBB) const
458 RemoveBranch(MachineBasicBlock &MBB) const
459459 {
460460 MachineBasicBlock::iterator I = MBB.end();
461461 if (I == MBB.begin()) return 0;
465465 return 0;
466466 --I;
467467 }
468 if (I->getOpcode() != Mips::J &&
468 if (I->getOpcode() != Mips::J &&
469469 GetCondFromBranchOpc(I->getOpcode()) == Mips::COND_INVALID)
470470 return 0;
471
471
472472 // Remove the branch.
473473 I->eraseFromParent();
474
474
475475 I = MBB.end();
476
476
477477 if (I == MBB.begin()) return 1;
478478 --I;
479479 if (GetCondFromBranchOpc(I->getOpcode()) == Mips::COND_INVALID)
480480 return 1;
481
481
482482 // Remove the branch.
483483 I->eraseFromParent();
484484 return 2;
485485 }
486486
487 /// ReverseBranchCondition - Return the inverse opcode of the
487 /// ReverseBranchCondition - Return the inverse opcode of the
488488 /// specified Branch instruction.
489489 bool MipsInstrInfo::
490 ReverseBranchCondition(SmallVectorImpl &Cond) const
491 {
492 assert( (Cond.size() == 3 || Cond.size() == 2) &&
490 ReverseBranchCondition(SmallVectorImpl &Cond) const
491 {
492 assert( (Cond.size() == 3 || Cond.size() == 2) &&
493493 "Invalid Mips branch condition!");
494494 Cond[0].setImm(GetOppositeBranchCondition((Mips::CondCode)Cond[0].getImm()));
495495 return false;
8080 COND_NE,
8181 COND_INVALID
8282 };
83
83
8484 // Turn condition code into conditional branch opcode.
8585 unsigned GetCondBranchFromCond(CondCode CC);
8686
8989 CondCode GetOppositeBranchCondition(Mips::CondCode CC);
9090
9191 /// MipsCCToString - Map each FP condition code to its string
92 inline static const char *MipsFCCToString(Mips::CondCode CC)
92 inline static const char *MipsFCCToString(Mips::CondCode CC)
9393 {
9494 switch (CC) {
9595 default: llvm_unreachable("Unknown condition code");
9797 case FCOND_T: return "f";
9898 case FCOND_UN:
9999 case FCOND_OR: return "un";
100 case FCOND_EQ:
100 case FCOND_EQ:
101101 case FCOND_NEQ: return "eq";
102102 case FCOND_UEQ:
103103 case FCOND_OGL: return "ueq";
137137 enum TOF {
138138 //===------------------------------------------------------------------===//
139139 // Mips Specific MachineOperand flags.
140
140
141141 MO_NO_FLAG,
142142
143143 /// MO_GOT - Represents the offset into the global offset table at which
144144 /// the address the relocation entry symbol resides during execution.
145145 MO_GOT,
146146
147 /// MO_GOT_CALL - Represents the offset into the global offset table at
148 /// which the address of a call site relocation entry symbol resides
147 /// MO_GOT_CALL - Represents the offset into the global offset table at
148 /// which the address of a call site relocation entry symbol resides
149149 /// during execution. This is different from the above since this flag
150150 /// can only be present in call instructions.
151151 MO_GOT_CALL,
152152
153 /// MO_GPREL - Represents the offset from the current gp value to be used
153 /// MO_GPREL - Represents the offset from the current gp value to be used
154154 /// for the relocatable object file being produced.
155155 MO_GPREL,
156156
157157 /// MO_ABS_HILO - Represents the hi or low part of an absolute symbol
158 /// address.
158 /// address.
159159 MO_ABS_HILO
160160
161161 };
180180 /// any side effects other than loading from the stack slot.
181181 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
182182 int &FrameIndex) const;
183
183
184184 /// isStoreToStackSlot - If the specified machine instruction is a direct
185185 /// store to a stack slot, return the virtual or physical register number of
186186 /// the source reg along with the FrameIndex of the loaded stack slot. If
188188 /// any side effects other than storing to the stack slot.
189189 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
190190 int &FrameIndex) const;
191
191
192192 /// Branch Analysis
193193 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
194194 MachineBasicBlock *&FBB,
219219 bool ReverseBranchCondition(SmallVectorImpl &Cond) const;
220220
221221 /// Insert nop instruction when hazard condition is found
222 virtual void insertNoop(MachineBasicBlock &MBB,
222 virtual void insertNoop(MachineBasicBlock &MBB,
223223 MachineBasicBlock::iterator MI) const;
224224
225225 /// getGlobalBaseReg - Return a virtual register initialized with the
2525 SDTCisInt<4>]>;
2626 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
2727 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
28 def SDT_MipsMAddMSub : SDTypeProfile<0, 4,
28 def SDT_MipsMAddMSub : SDTypeProfile<0, 4,
2929 [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
30 SDTCisSameAs<1, 2>,
30 SDTCisSameAs<1, 2>,
3131 SDTCisSameAs<2, 3>]>;
3232
3333
164164 let rd = 0, shamt = 0, Defs = [HI, LO], Uses = [HI, LO] in
165165 class MArithR func, string instr_asm, SDNode op> :
166166 FR<0x1c, func, (outs), (ins CPURegs:$rs, CPURegs:$rt),
167 !strconcat(instr_asm, "\t$rs, $rt"),
167 !strconcat(instr_asm, "\t$rs, $rt"),
168168 [(op CPURegs:$rs, CPURegs:$rt, LO, HI)], IIImul>;
169169
170170 // Logical
184184 [(set CPURegs:$dst, (not (or CPURegs:$b, CPURegs:$c)))], IIAlu>;
185185
186186 // Shifts
187 class LogicR_shift_rotate_imm func, bits<5> _rs, string instr_asm,
187 class LogicR_shift_rotate_imm func, bits<5> _rs, string instr_asm,
188188 SDNode OpNode>:
189189 FR<0x00, func, (outs CPURegs:$dst), (ins CPURegs:$b, shamt:$c),
190190 !strconcat(instr_asm, "\t$dst, $b, $c"),
192192 let rs = _rs;
193193 }
194194
195 class LogicR_shift_rotate_reg func, bits<5> _shamt, string instr_asm,
195 class LogicR_shift_rotate_reg func, bits<5> _shamt, string instr_asm,
196196 SDNode OpNode>:
197197 FR<0x00, func, (outs CPURegs:$dst), (ins CPURegs:$c, CPURegs:$b),
198198 !strconcat(instr_asm, "\t$dst, $b, $c"),
1818
1919 namespace llvm {
2020 class Target;
21
21
2222 class MipsMCAsmInfo : public MCAsmInfo {
2323 public:
2424 explicit MipsMCAsmInfo(const Target &T, StringRef TT);
3737
3838 using namespace llvm;
3939
40 MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST,
40 MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST,
4141 const TargetInstrInfo &tii)
4242 : MipsGenRegisterInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
4343 Subtarget(ST), TII(tii) {}
4545 /// getRegisterNumbering - Given the enum value for some register, e.g.
4646 /// Mips::RA, return the number that it corresponds to (e.g. 31).
4747 unsigned MipsRegisterInfo::
48 getRegisterNumbering(unsigned RegEnum)
48 getRegisterNumbering(unsigned RegEnum)
4949 {
5050 switch (RegEnum) {
5151 case Mips::ZERO : case Mips::F0 : case Mips::D0 : return 0;
8181 case Mips::FP : case Mips::F30: case Mips::D15: return 30;
8282 case Mips::RA : case Mips::F31: return 31;
8383 default: llvm_unreachable("Unknown register number!");
84 }
84 }
8585 return 0; // Not reached
8686 }
8787
8888 unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
8989
9090 //===----------------------------------------------------------------------===//
91 // Callee Saved Registers methods
91 // Callee Saved Registers methods
9292 //===----------------------------------------------------------------------===//
9393
9494 /// Mips Callee Saved Registers
9595 const unsigned* MipsRegisterInfo::
96 getCalleeSavedRegs(const MachineFunction *MF) const
96 getCalleeSavedRegs(const MachineFunction *MF) const
9797 {
9898 // Mips callee-save register range is $16-$23, $f20-$f30
9999 static const unsigned SingleFloatOnlyCalleeSavedRegs[] = {
100 Mips::S0, Mips::S1, Mips::S2, Mips::S3,
100 Mips::S0, Mips::S1, Mips::S2, Mips::S3,
101101 Mips::S4, Mips::S5, Mips::S6, Mips::S7,
102 Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24, Mips::F25,
102 Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24, Mips::F25,
103103 Mips::F26, Mips::F27, Mips::F28, Mips::F29, Mips::F30, 0
104104 };
105105
106106 static const unsigned BitMode32CalleeSavedRegs[] = {
107 Mips::S0, Mips::S1, Mips::S2, Mips::S3,
107 Mips::S0, Mips::S1, Mips::S2, Mips::S3,
108108 Mips::S4, Mips::S5, Mips::S6, Mips::S7,
109109 Mips::F20, Mips::F22, Mips::F24, Mips::F26, Mips::F28, Mips::F30, 0
110110 };
131131 if (!Subtarget.isSingleFloat())
132132 for (unsigned FReg=(Mips::F0)+1; FReg < Mips::F30; FReg+=2)
133133 Reserved.set(FReg);
134
134
135135 return Reserved;
136136 }
137137
138 // This function eliminate ADJCALLSTACKDOWN,
138 // This function eliminate ADJCALLSTACKDOWN,
139139 // ADJCALLSTACKUP pseudo instructions
140140 void MipsRegisterInfo::
141141 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
156156 unsigned i = 0;
157157 while (!MI.getOperand(i).isFI()) {
158158 ++i;
159 assert(i < MI.getNumOperands() &&
159 assert(i < MI.getNumOperands() &&
160160 "Instr doesn't have FrameIndex operand!");
161161 }
162162
2525 struct MipsRegisterInfo : public MipsGenRegisterInfo {
2626 const MipsSubtarget &Subtarget;
2727 const TargetInstrInfo &TII;
28
28
2929 MipsRegisterInfo(const MipsSubtarget &Subtarget, const TargetInstrInfo &tii);
3030
3131 /// getRegisterNumbering - Given the enum value for some register, e.g.
1616 let Namespace = "Mips";
1717 }
1818
19 class MipsRegWithSubRegs subregs>
19 class MipsRegWithSubRegs subregs>
2020 : RegisterWithSubRegs {
2121 field bits<5> Num;
2222 let Namespace = "Mips";
8282 def SP : MipsGPRReg< 29, "SP">, DwarfRegNum<[29]>;
8383 def FP : MipsGPRReg< 30, "FP">, DwarfRegNum<[30]>;
8484 def RA : MipsGPRReg< 31, "RA">, DwarfRegNum<[31]>;
85
85
8686 /// Mips Single point precision FPU Registers
8787 def F0 : FPR< 0, "F0">, DwarfRegNum<[32]>;
8888 def F1 : FPR< 1, "F1">, DwarfRegNum<[33]>;
116116 def F29 : FPR<29, "F29">, DwarfRegNum<[61]>;
117117 def F30 : FPR<30, "F30">, DwarfRegNum<[62]>;
118118 def F31 : FPR<31, "F31">, DwarfRegNum<[63]>;
119
119
120120 /// Mips Double point precision FPU Registers (aliased
121121 /// with the single precision to hold 64 bit values)
122122 def D0 : AFPR< 0, "F0", [F0, F1]>, DwarfRegNum<[32]>;
148148 // Register Classes
149149 //===----------------------------------------------------------------------===//
150150
151 def CPURegs : RegisterClass<"Mips", [i32], 32,
151 def CPURegs : RegisterClass<"Mips", [i32], 32,
152152 // Return Values and Arguments
153153 [V0, V1, A0, A1, A2, A3,
154154 // Not preserved across procedure calls
155 T0, T1, T2, T3, T4, T5, T6, T7, T8, T9,
155 T0, T1, T2, T3, T4, T5, T6, T7, T8, T9,
156156 // Callee save
157157 S0, S1, S2, S3, S4, S5, S6, S7,
158158 // Reserved
172172
173173 // 64bit fp:
174174 // * FGR64 - 32 64-bit registers
175 // * AFGR64 - 16 32-bit even registers (32-bit FP Mode)
175 // * AFGR64 - 16 32-bit even registers (32-bit FP Mode)
176176 //
177177 // 32bit fp:
178178 // * FGR32 - 16 32-bit even registers
179179 // * FGR32 - 32 32-bit registers (single float only mode)
180 def FGR32 : RegisterClass<"Mips", [f32], 32,
180 def FGR32 : RegisterClass<"Mips", [f32], 32,
181181 // Return Values and Arguments
182182 [F0, F1, F2, F3, F12, F13, F14, F15,
183183 // Not preserved across procedure calls
184 F4, F5, F6, F7, F8, F9, F10, F11, F16, F17, F18, F19,
184 F4, F5, F6, F7, F8, F9, F10, F11, F16, F17, F18, F19,
185185 // Callee save
186186 F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30,
187187 // Reserved
194194 let MethodBodies = [{
195195
196196 static const unsigned MIPS_FGR32[] = {
197 Mips::F0, Mips::F1, Mips::F2, Mips::F3, Mips::F12, Mips::F13,
198 Mips::F14, Mips::F15, Mips::F4, Mips::F5, Mips::F6, Mips::F7,
199 Mips::F8, Mips::F9, Mips::F10, Mips::F11, Mips::F16, Mips::F17,
200 Mips::F18, Mips::F19, Mips::F20, Mips::F21, Mips::F22, Mips::F23,
201 Mips::F24, Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29,
197 Mips::F0, Mips::F1, Mips::F2, Mips::F3, Mips::F12, Mips::F13,
198 Mips::F14, Mips::F15, Mips::F4, Mips::F5, Mips::F6, Mips::F7,
199 Mips::F8, Mips::F9, Mips::F10, Mips::F11, Mips::F16, Mips::F17,
200 Mips::F18, Mips::F19, Mips::F20, Mips::F21, Mips::F22, Mips::F23,
201 Mips::F24, Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29,
202202 Mips::F30
203203 };
204204
205205 static const unsigned MIPS_SVR4_FGR32[] = {
206 Mips::F0, Mips::F2, Mips::F12, Mips::F14, Mips::F4,
207 Mips::F6, Mips::F8, Mips::F10, Mips::F16, Mips::F18,
206 Mips::F0, Mips::F2, Mips::F12, Mips::F14, Mips::F4,
207 Mips::F6, Mips::F8, Mips::F10, Mips::F16, Mips::F18,
208208 Mips::F20, Mips::F22, Mips::F24, Mips::F26, Mips::F28, Mips::F30,
209209 };
210210
216216 if (Subtarget.isSingleFloat())
217217 return MIPS_FGR32;
218218 else
219 return MIPS_SVR4_FGR32;
219 return MIPS_SVR4_FGR32;
220220 }
221221
222222 FGR32Class::iterator
232232 }];
233233 }
234234
235 def AFGR64 : RegisterClass<"Mips", [f64], 64,
235 def AFGR64 : RegisterClass<"Mips", [f64], 64,
236236 // Return Values and Arguments
237237 [D0, D1, D6, D7,
238238 // Not preserved across procedure calls
239 D2, D3, D4, D5, D8, D9,
239 D2, D3, D4, D5, D8, D9,
240240 // Callee save
241241 D10, D11, D12, D13, D14,
242242 // Reserved
1313 def IMULDIV : FuncUnit;
1414
1515 //===----------------------------------------------------------------------===//
16 // Instruction Itinerary classes used for Mips
16 // Instruction Itinerary classes used for Mips
1717 //===----------------------------------------------------------------------===//
1818 def IIAlu : InstrItinClass;
1919 def IILoad : InstrItinClass;
1616 using namespace llvm;
1717
1818 MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &FS,
19 bool little) :
19 bool little) :
2020 MipsArchVersion(Mips1), MipsABI(O32), IsLittle(little), IsSingleFloat(false),
2121 IsFP64bit(false), IsGP64bit(false), HasVFPU(false), IsLinux(true),
2222 HasSEInReg(false), HasCondMov(false), HasMulDivAdd(false), HasMinMax(false),
3232 if (TT.find("linux") == std::string::npos)
3333 IsLinux = false;
3434
35 // When only the target triple is specified and is
35 // When only the target triple is specified and is
3636 // a allegrex target, set the features. We also match
3737 // big and little endian allegrex cores (dont really
3838 // know if a big one exists)
2525 public:
2626 enum MipsABIEnum {
2727 O32, O64, N32, N64, EABI
28 };
28 };
2929
3030 protected:
3131
3333 Mips1, Mips2, Mips3, Mips4, Mips32, Mips32r2
3434 };
3535
36 // Mips architecture version
36 // Mips architecture version
3737 MipsArchEnum MipsArchVersion;
3838
39 // Mips supported ABIs
39 // Mips supported ABIs
4040 MipsABIEnum MipsABI;
4141
4242 // IsLittle - The target is Little Endian
6060 bool IsLinux;
6161
6262 /// Features related to the presence of specific instructions.
63
63
6464 // HasSEInReg - SEB and SEH (signext in register) instructions.
6565 bool HasSEInReg;
6666
6767 // HasCondMov - Conditional mov (MOVZ, MOVN) instructions.
6868 bool HasCondMov;
6969
70 // HasMulDivAdd - Multiply add and sub (MADD, MADDu, MSUB, MSUBu)
70 // HasMulDivAdd - Multiply add and sub (MADD, MADDu, MSUB, MSUBu)
7171 // instructions.
7272 bool HasMulDivAdd;
7373
9292 /// This constructor initializes the data members to match that
9393 /// of the specified triple.
9494 MipsSubtarget(const std::string &TT, const std::string &FS, bool little);
95
96 /// ParseSubtargetFeatures - Parses features string setting specified
95
96 /// ParseSubtargetFeatures - Parses features string setting specified
9797 /// subtarget options. Definition of function is auto generated by tblgen.
9898 std::string ParseSubtargetFeatures(const std::string &FS,
9999 const std::string &CPU);
100100
101101 bool isMips1() const { return MipsArchVersion == Mips1; }
102 bool isMips32() const { return MipsArchVersion >= Mips32; }
102 bool isMips32() const { return MipsArchVersion >= Mips32; }
103103 bool isMips32r2() const { return MipsArchVersion == Mips32r2; }
104104
105105 bool isLittle() const { return IsLittle; }
1717 const MCSection *SmallDataSection;
1818 const MCSection *SmallBSSSection;
1919 public:
20
20
2121 void Initialize(MCContext &Ctx, const TargetMachine &TM);
2222
23
23
2424 /// IsGlobalInSmallSection - Return true if this global address should be
2525 /// placed into small data/bss section.
2626 bool IsGlobalInSmallSection(const GlobalValue *GV,
2727 const TargetMachine &TM, SectionKind Kind)const;
2828 bool IsGlobalInSmallSection(const GlobalValue *GV,
29 const TargetMachine &TM) const;
30
29 const TargetMachine &TM) const;
30
3131 const MCSection *SelectSectionForGlobal(const GlobalValue *GV,
3232 SectionKind Kind,
3333 Mangler *Mang,
3434 const TargetMachine &TM) const;
35
35
3636 // TODO: Classify globals as mips wishes.
3737 };
3838 } // end namespace llvm
1313
1414 Target llvm::TheMipsTarget, llvm::TheMipselTarget;
1515
16 extern "C" void LLVMInitializeMipsTargetInfo() {
16 extern "C" void LLVMInitializeMipsTargetInfo() {
1717 RegisterTarget X(TheMipsTarget, "mips", "Mips");
1818
1919 RegisterTarget Y(TheMipselTarget, "mipsel", "Mipsel");