llvm.org GIT mirror llvm / 80e5f43
[X86] combineCarryThroughADD - add support for X86::COND_A commutations (PR24545) As discussed on PR24545, we should try to commute X86::COND_A 'icmp ugt' cases to X86::COND_B 'icmp ult' to more optimally bind the carry flag output to a SBB instruction. Differential Revision: https://reviews.llvm.org/D57281 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352289 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Pilgrim 1 year, 26 days ago
2 changed file(s) with 28 addition(s) and 13 deletion(s). Raw diff Collapse all Expand all
3487534875 // When legalizing carry, we create carries via add X, -1
3487634876 // If that comes from an actual carry, via setcc, we use the
3487734877 // carry directly.
34878 static SDValue combineCarryThroughADD(SDValue EFLAGS) {
34878 static SDValue combineCarryThroughADD(SDValue EFLAGS, SelectionDAG &DAG) {
3487934879 if (EFLAGS.getOpcode() == X86ISD::ADD) {
3488034880 if (isAllOnesConstant(EFLAGS.getOperand(1))) {
3488134881 SDValue Carry = EFLAGS.getOperand(0);
3488834888 Carry = Carry.getOperand(0);
3488934889 if (Carry.getOpcode() == X86ISD::SETCC ||
3489034890 Carry.getOpcode() == X86ISD::SETCC_CARRY) {
34891 if (Carry.getConstantOperandVal(0) == X86::COND_B)
34892 return Carry.getOperand(1);
34891 // TODO: Merge this code with equivalent in combineAddOrSubToADCOrSBB?
34892 uint64_t CarryCC = Carry.getConstantOperandVal(0);
34893 SDValue CarryOp1 = Carry.getOperand(1);
34894 if (CarryCC == X86::COND_B)
34895 return CarryOp1;
34896 if (CarryCC == X86::COND_A) {
34897 // Try to convert COND_A into COND_B in an attempt to facilitate
34898 // materializing "setb reg".
34899 //
34900 // Do not flip "e > c", where "c" is a constant, because Cmp
34901 // instruction cannot take an immediate as its first operand.
34902 //
34903 if (CarryOp1.getOpcode() == X86ISD::SUB && CarryOp1.hasOneUse() &&
34904 CarryOp1.getValueType().isInteger() &&
34905 !isa(CarryOp1.getOperand(1))) {
34906 SDValue SubCommute =
34907 DAG.getNode(X86ISD::SUB, SDLoc(CarryOp1), CarryOp1->getVTList(),
34908 CarryOp1.getOperand(1), CarryOp1.getOperand(0));
34909 return SDValue(SubCommute.getNode(), CarryOp1.getResNo());
34910 }
34911 }
3489334912 }
3489434913 }
3489534914 }
3490434923 SelectionDAG &DAG,
3490534924 const X86Subtarget &Subtarget) {
3490634925 if (CC == X86::COND_B)
34907 if (SDValue Flags = combineCarryThroughADD(EFLAGS))
34926 if (SDValue Flags = combineCarryThroughADD(EFLAGS, DAG))
3490834927 return Flags;
3490934928
3491034929 if (SDValue R = checkBoolTestSetCCCombine(EFLAGS, CC))
4055740576 }
4055840577
4055940578 static SDValue combineSBB(SDNode *N, SelectionDAG &DAG) {
40560 if (SDValue Flags = combineCarryThroughADD(N->getOperand(2))) {
40579 if (SDValue Flags = combineCarryThroughADD(N->getOperand(2), DAG)) {
4056140580 MVT VT = N->getSimpleValueType(0);
4056240581 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
4056340582 return DAG.getNode(X86ISD::SBB, SDLoc(N), VTs,
4060040619 return DCI.CombineTo(N, Res1, CarryOut);
4060140620 }
4060240621
40603 if (SDValue Flags = combineCarryThroughADD(N->getOperand(2))) {
40622 if (SDValue Flags = combineCarryThroughADD(N->getOperand(2), DAG)) {
4060440623 MVT VT = N->getSimpleValueType(0);
4060540624 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
4060640625 return DAG.getNode(X86ISD::ADC, SDLoc(N), VTs,
125125 ; X86: # %bb.0:
126126 ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
127127 ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
128 ; X86-NEXT: movl (%ecx), %edx
129 ; X86-NEXT: cmpl {{[0-9]+}}(%esp), %edx
130 ; X86-NEXT: seta %dl
131 ; X86-NEXT: addb $-1, %dl
128 ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
129 ; X86-NEXT: cmpl (%ecx), %edx
132130 ; X86-NEXT: sbbl 4(%ecx), %eax
133131 ; X86-NEXT: setb %al
134132 ; X86-NEXT: retl
135133 ;
136134 ; X64-LABEL: PR24545:
137135 ; X64: # %bb.0:
138 ; X64-NEXT: cmpl %edi, (%rdx)
139 ; X64-NEXT: seta %al
140 ; X64-NEXT: addb $-1, %al
136 ; X64-NEXT: cmpl (%rdx), %edi
141137 ; X64-NEXT: sbbl 4(%rdx), %esi
142138 ; X64-NEXT: setb %al
143139 ; X64-NEXT: retq