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Revert [AArch64] Add support for Transactional Memory Extension (TME) This reverts r366322 (git commit 4b8da3a503e434ddbc08ecf66582475765f449bc) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366355 91177308-0d34-0410-b5e6-96231b3b80d8 Momchil Velikov 3 months ago
15 changed file(s) with 12 addition(s) and 251 deletion(s). Raw diff Collapse all Expand all
702702 def int_aarch64_subp : Intrinsic<[llvm_i64_ty], [llvm_ptr_ty, llvm_ptr_ty],
703703 [IntrNoMem]>;
704704 }
705
706 // Transactional Memory Extension (TME) Intrinsics
707 let TargetPrefix = "aarch64" in {
708 def int_aarch64_tstart : GCCBuiltin<"__builtin_arm_tstart">,
709 Intrinsic<[llvm_i64_ty]>;
710
711 def int_aarch64_tcommit : GCCBuiltin<"__builtin_arm_tcommit">, Intrinsic<[]>;
712
713 def int_aarch64_tcancel : GCCBuiltin<"__builtin_arm_tcancel">,
714 Intrinsic<[], [llvm_i64_ty],
715 [ImmArg<0>, IntrNoMem, IntrHasSideEffects,
716 IntrNoReturn]>;
717
718 def int_aarch64_ttest : GCCBuiltin<"__builtin_arm_ttest">,
719 Intrinsic<[llvm_i64_ty], [],
720 [IntrNoMem, IntrHasSideEffects]>;
721 }
7878 AARCH64_ARCH_EXT_NAME("ssbs", AArch64::AEK_SSBS, "+ssbs", "-ssbs")
7979 AARCH64_ARCH_EXT_NAME("sb", AArch64::AEK_SB, "+sb", "-sb")
8080 AARCH64_ARCH_EXT_NAME("predres", AArch64::AEK_PREDRES, "+predres", "-predres")
81 AARCH64_ARCH_EXT_NAME("tme", AArch64::AEK_TME, "+tme", "-tme")
8281 #undef AARCH64_ARCH_EXT_NAME
8382
8483 #ifndef AARCH64_CPU_NAME
5353 AEK_SVE2SM4 = 1 << 25,
5454 AEK_SVE2SHA3 = 1 << 26,
5555 AEK_BITPERM = 1 << 27,
56 AEK_TME = 1 << 28,
5756 };
5857
5958 enum class ArchKind {
343343
344344 def FeatureMTE : SubtargetFeature<"mte", "HasMTE",
345345 "true", "Enable Memory Tagging Extension" >;
346
347 def FeatureTME : SubtargetFeature<"tme", "HasTME",
348 "true", "Enable Transactional Memory Extension" >;
349346
350347 //===----------------------------------------------------------------------===//
351348 // Architectures.
713713 let ParserMatchClass = LogicalImm64NotOperand;
714714 }
715715
716 // iXX_imm0_65535 predicates - True if the immediate is in the range [0,65535].
717 let ParserMatchClass = AsmImmRange<0, 65535>, PrintMethod = "printImmHex" in {
718 def i32_imm0_65535 : Operand, ImmLeaf
716 // imm0_65535 predicate - True if the immediate is in the range [0,65535].
717 def imm0_65535 : Operand, ImmLeaf
719718 return ((uint32_t)Imm) < 65536;
720 }]>;
721
722 def i64_imm0_65535 : Operand, ImmLeaf
723 return ((uint64_t)Imm) < 65536;
724 }]>;
719 }]> {
720 let ParserMatchClass = AsmImmRange<0, 65535>;
721 let PrintMethod = "printImmHex";
725722 }
726723
727724 // imm0_255 predicate - True if the immediate is in the range [0,255].
10821079 Sched<[WriteSys]> {
10831080 bits<5> Rt;
10841081 let Inst{4-0} = Rt;
1085 }
1086
1087 // System instructions for transactional memory extension
1088 class TMBaseSystemI CRm, bits<3> op2, dag oops, dag iops,
1089 string asm, string operands, list pattern>
1090 : BaseSystemI,
1091 Sched<[WriteSys]> {
1092 let Inst{20-12} = 0b000110011;
1093 let Inst{11-8} = CRm;
1094 let Inst{7-5} = op2;
1095 let DecoderMethod = "";
1096
1097 let mayLoad = 1;
1098 let mayStore = 1;
1099 }
1100
1101 // System instructions for transactional memory - single input operand
1102 class TMSystemI CRm, string asm, list pattern>
1103 : TMBaseSystemI<0b1, CRm, 0b011,
1104 (outs GPR64:$Rt), (ins), asm, "\t$Rt", pattern> {
1105 bits<5> Rt;
1106 let Inst{4-0} = Rt;
1107 }
1108
1109 // System instructions for transactional memory - no operand
1110 class TMSystemINoOperand CRm, string asm, list pattern>
1111 : TMBaseSystemI<0b0, CRm, 0b011, (outs), (ins), asm, "", pattern> {
1112 let Inst{4-0} = 0b11111;
1113 }
1114
1115 // System instructions for exit from transactions
1116 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
1117 class TMSystemException op1, string asm, list pattern>
1118 : I<(outs), (ins i64_imm0_65535:$imm), asm, "\t$imm", "", pattern>,
1119 Sched<[WriteSys]> {
1120 bits<16> imm;
1121 let Inst{31-24} = 0b11010100;
1122 let Inst{23-21} = op1;
1123 let Inst{20-5} = imm;
1124 let Inst{4-0} = 0b00000;
11251082 }
11261083
11271084 // Hint instructions that take both a CRm and a 3-bit immediate.
41284085
41294086 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
41304087 class ExceptionGeneration op1, bits<2> ll, string asm>
4131 : I<(outs), (ins i32_imm0_65535:$imm), asm, "\t$imm", "", []>,
4088 : I<(outs), (ins imm0_65535:$imm), asm, "\t$imm", "", []>,
41324089 Sched<[WriteSys]> {
41334090 bits<16> imm;
41344091 let Inst{31-24} = 0b11010100;
132132 AssemblerPredicate<"FeatureBranchTargetId", "bti">;
133133 def HasMTE : Predicate<"Subtarget->hasMTE()">,
134134 AssemblerPredicate<"FeatureMTE", "mte">;
135 def HasTME : Predicate<"Subtarget->hasTME()">,
136 AssemblerPredicate<"FeatureTME", "tme">;
137135 def IsLE : Predicate<"Subtarget->isLittleEndian()">;
138136 def IsBE : Predicate<"!Subtarget->isLittleEndian()">;
139137 def IsWindows : Predicate<"Subtarget->isTargetWindows()">;
799797 (SYSxt imm0_7:$op1, sys_cr_op:$Cn,
800798 sys_cr_op:$Cm, imm0_7:$op2, XZR)>;
801799
802
803 let Predicates = [HasTME] in {
804
805 def TSTART : TMSystemI<0b0000, "tstart", [(set GPR64:$Rt, (int_aarch64_tstart))]>;
806
807 def TCOMMIT : TMSystemINoOperand<0b0000, "tcommit", [(int_aarch64_tcommit)]>;
808
809 let mayLoad = 0, mayStore = 0 in {
810 def TTEST : TMSystemI<0b0001, "ttest", [(set GPR64:$Rt, (int_aarch64_ttest))]>;
811 def TCANCEL : TMSystemException<0b011, "tcancel", [(int_aarch64_tcancel i64_imm0_65535:$imm)]> {
812 let isBarrier = 1;
813 }
814 }
815 } // HasTME
816
817800 //===----------------------------------------------------------------------===//
818801 // Move immediate instructions.
819802 //===----------------------------------------------------------------------===//
825808 defm MOVZ : MoveImmediate<0b10, "movz">;
826809
827810 // First group of aliases covers an implicit "lsl #0".
828 def : InstAlias<"movk $dst, $imm", (MOVKWi GPR32:$dst, i32_imm0_65535:$imm, 0), 0>;
829 def : InstAlias<"movk $dst, $imm", (MOVKXi GPR64:$dst, i32_imm0_65535:$imm, 0), 0>;
830 def : InstAlias<"movn $dst, $imm", (MOVNWi GPR32:$dst, i32_imm0_65535:$imm, 0)>;
831 def : InstAlias<"movn $dst, $imm", (MOVNXi GPR64:$dst, i32_imm0_65535:$imm, 0)>;
832 def : InstAlias<"movz $dst, $imm", (MOVZWi GPR32:$dst, i32_imm0_65535:$imm, 0)>;
833 def : InstAlias<"movz $dst, $imm", (MOVZXi GPR64:$dst, i32_imm0_65535:$imm, 0)>;
811 def : InstAlias<"movk $dst, $imm", (MOVKWi GPR32:$dst, imm0_65535:$imm, 0), 0>;
812 def : InstAlias<"movk $dst, $imm", (MOVKXi GPR64:$dst, imm0_65535:$imm, 0), 0>;
813 def : InstAlias<"movn $dst, $imm", (MOVNWi GPR32:$dst, imm0_65535:$imm, 0)>;
814 def : InstAlias<"movn $dst, $imm", (MOVNXi GPR64:$dst, imm0_65535:$imm, 0)>;
815 def : InstAlias<"movz $dst, $imm", (MOVZWi GPR32:$dst, imm0_65535:$imm, 0)>;
816 def : InstAlias<"movz $dst, $imm", (MOVZXi GPR64:$dst, imm0_65535:$imm, 0)>;
834817
835818 // Next, we have various ELF relocations with the ":XYZ_g0:sym" syntax.
836819 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
133133 bool HasBTI = false;
134134 bool HasRandGen = false;
135135 bool HasMTE = false;
136 bool HasTME = false;
137136
138137 // Arm SVE2 extensions
139138 bool HasSVE2AES = false;
380379 bool hasBTI() const { return HasBTI; }
381380 bool hasRandGen() const { return HasRandGen; }
382381 bool hasMTE() const { return HasMTE; }
383 bool hasTME() const { return HasTME; }
384382 // Arm SVE2 extensions
385383 bool hasSVE2AES() const { return HasSVE2AES; }
386384 bool hasSVE2SM4() const { return HasSVE2SM4; }
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test/CodeGen/AArch64/tme-tcancel.ll less more
None ; RUN: llc %s -o - | FileCheck %s
1
2 target triple = "aarch64-unknown-unknown-eabi"
3
4 define void @test_tcancel() #0 {
5 tail call void @llvm.aarch64.tcancel(i64 0) #1
6 unreachable
7 }
8
9 declare void @llvm.aarch64.tcancel(i64 immarg) #1
10
11 attributes #0 = { "target-features"="+tme" }
12 attributes #1 = { nounwind noreturn }
13
14 ; CHECK-LABEL: test_tcancel
15 ; CHECK: tcancel
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test/CodeGen/AArch64/tme-tcommit.ll less more
None ; RUN: llc %s -o - | FileCheck %s
1
2 target triple = "aarch64-unknown-unknown-eabi"
3
4 define void @test_tcommit() #0 {
5 tail call void @llvm.aarch64.tcommit()
6 ret void
7 }
8
9 declare void @llvm.aarch64.tcommit() #1
10
11 attributes #0 = { "target-features"="+tme" }
12 attributes #1 = { nounwind }
13
14 ; CHECK-LABEL: test_tcommit
15 ; CHECK: tcommit
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test/CodeGen/AArch64/tme-tstart.ll less more
None ; RUN: llc %s -o - | FileCheck %s
1
2 target triple = "aarch64-unknown-unknown-eabi"
3
4 define i64 @test_tstart() #0 {
5 %r = tail call i64 @llvm.aarch64.tstart()
6 ret i64 %r
7 }
8
9 declare i64 @llvm.aarch64.tstart() #1
10
11 attributes #0 = { "target-features"="+tme" }
12 attributes #1 = { nounwind }
13
14 ; CHECK-LABEL: test_tstart
15 ; CHECK: tstart x
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test/CodeGen/AArch64/tme-ttest.ll less more
None ; RUN: llc %s -o - | FileCheck %s
1
2 target triple = "aarch64-unknown-unknown-eabi"
3
4 define i64 @test_ttest() #0 {
5 %r = tail call i64 @llvm.aarch64.ttest()
6 ret i64 %r
7 }
8
9 declare i64 @llvm.aarch64.ttest() #1
10
11 attributes #0 = { "target-features"="+tme" }
12 attributes #1 = { nounwind }
13
14 ; CHECK-LABEL: test_ttest
15 ; CHECK: ttest x
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test/MC/AArch64/tme-error.s less more
None // Tests for transactional memory extension instructions
1 // RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+tme < %s 2>&1 | FileCheck %s
2
3 tstart
4 // CHECK: error: too few operands for instruction
5 // CHECK-NEXT: tstart
6 tstart x4, x5
7 // CHECK: error: invalid operand for instruction
8 // CHECK-NEXT: tstart x4, x5
9 tstart x4, #1
10 // CHECK: error: invalid operand for instruction
11 // CHECK-NEXT: tstart x4, #1
12 tstart sp
13 // CHECK: error: invalid operand for instruction
14 // CHECK-NEXT: tstart sp
15
16 ttest
17 // CHECK: error: too few operands for instruction
18 // CHECK-NEXT: ttest
19 ttest x4, x5
20 // CHECK: error: invalid operand for instruction
21 // CHECK-NEXT: ttest x4, x5
22 ttest x4, #1
23 // CHECK: error: invalid operand for instruction
24 // CHECK-NEXT: ttest x4, #1
25 ttest sp
26 // CHECK: error: invalid operand for instruction
27 // CHECK-NEXT: ttest sp
28
29 tcommit x4
30 // CHECK: error: invalid operand for instruction
31 // CHECK-NEXT: tcommit x4
32 tcommit sp
33 // CHECK: error: invalid operand for instruction
34 // CHECK-NEXT: tcommit sp
35
36
37 tcancel
38 // CHECK: error: too few operands for instruction
39 // CHECK-NEXT tcancel
40 tcancel x0
41 // CHECK: error: immediate must be an integer in range [0, 65535]
42 // CHECK-NEXT tcancel
43 tcancel #65536
44 // CHECK: error: immediate must be an integer in range [0, 65535]
45 // CHECK-NEXT: tcancel #65536
46
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test/MC/AArch64/tme.s less more
None // Tests for transaction memory extension instructions
1 //
2 // RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+tme < %s | FileCheck %s
3 // RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=-tme < %s 2>&1 | FileCheck %s --check-prefix=NOTME
4
5 tstart x3
6 ttest x4
7 tcommit
8 tcancel #0x1234
9
10 // CHECK: tstart x3 // encoding: [0x63,0x30,0x23,0xd5]
11 // CHECK: ttest x4 // encoding: [0x64,0x31,0x23,0xd5]
12 // CHECK: tcommit // encoding: [0x7f,0x30,0x03,0xd5]
13 // CHECK: tcancel #0x1234 // encoding: [0x80,0x46,0x62,0xd4]
14
15
16 // NOTME: instruction requires: tme
17 // NOTME-NEXT: tstart x3
18 // NOTME: instruction requires: tme
19 // NOTME-NEXT: ttest x4
20 // NOTME: instruction requires: tme
21 // NOTME-NEXT: tcommit
22 // NOTME: instruction requires: tme
23 // NOTME-NEXT: tcancel #0x1234
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test/MC/Disassembler/AArch64/tme.txt less more
None # Tests for transaction memory extension instructions
1 # RUN: llvm-mc -triple=aarch64 -mattr=+tme -disassemble < %s | FileCheck %s
2 # RUN: not llvm-mc -triple=aarch64 -mattr=-tme -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOTME
3
4 [0x63,0x30,0x23,0xd5]
5 [0x64,0x31,0x23,0xd5]
6 [0x7f,0x30,0x03,0xd5]
7 [0x80,0x46,0x62,0xd4]
8
9 # CHECK: tstart x3
10 # CHECK: ttest x4
11 # CHECK: tcommit
12 # CHECK: tcancel #0x1234
13
14 # NOTEME: mrs
15 # NOTEME-NEXT: mrs
16 # NOTEME-NEXT: msr
17 # NOTME: warning: invalid instruction encoding
18 # NOTME-NEXT: [0x80,0x46,0x62,0xd4]
11181118 {"rcpc", "norcpc", "+rcpc", "-rcpc" },
11191119 {"rng", "norng", "+rand", "-rand"},
11201120 {"memtag", "nomemtag", "+mte", "-mte"},
1121 {"tme", "notme", "+tme", "-tme"},
11221121 {"ssbs", "nossbs", "+ssbs", "-ssbs"},
11231122 {"sb", "nosb", "+sb", "-sb"},
11241123 {"predres", "nopredres", "+predres", "-predres"}