llvm.org GIT mirror llvm / 8095580
Suppress '(x < y) ? a : 0 -> (x < y) & a' transform on X86 architectures with dedicated mask registers. Patch by Aleksey Bader. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196386 91177308-0d34-0410-b5e6-96231b3b80d8 Cameron McInally 6 years ago
2 changed file(s) with 19 addition(s) and 7 deletion(s). Raw diff Collapse all Expand all
1700917009 // Simplify vector selection if the selector will be produced by CMPP*/PCMP*.
1701017010 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
1701117011 // Check if SETCC has already been promoted
17012 TLI.getSetCCResultType(*DAG.getContext(), VT) == Cond.getValueType()) {
17012 TLI.getSetCCResultType(*DAG.getContext(), VT) == CondVT &&
17013 // Check that condition value type matches vselect operand type
17014 CondVT == VT) {
1701317015
1701417016 assert(Cond.getValueType().isVector() &&
1701517017 "vector select expects a vector selector!");
1701617018
17017 EVT IntVT = Cond.getValueType();
1701817019 bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
1701917020 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
1702017021
1702917030 ISD::CondCode NewCC =
1703017031 ISD::getSetCCInverse(cast(CC)->get(),
1703117032 Cond.getOperand(0).getValueType().isInteger());
17032 Cond = DAG.getSetCC(DL, IntVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
17033 Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1), NewCC);
1703317034 std::swap(LHS, RHS);
1703417035 TValIsAllOnes = FValIsAllOnes;
1703517036 FValIsAllZeros = TValIsAllZeros;
1704217043 if (TValIsAllOnes && FValIsAllZeros)
1704317044 Ret = Cond;
1704417045 else if (TValIsAllOnes)
17045 Ret = DAG.getNode(ISD::OR, DL, IntVT, Cond,
17046 DAG.getNode(ISD::BITCAST, DL, IntVT, RHS));
17046 Ret = DAG.getNode(ISD::OR, DL, CondVT, Cond,
17047 DAG.getNode(ISD::BITCAST, DL, CondVT, RHS));
1704717048 else if (FValIsAllZeros)
17048 Ret = DAG.getNode(ISD::AND, DL, IntVT, Cond,
17049 DAG.getNode(ISD::BITCAST, DL, IntVT, LHS));
17049 Ret = DAG.getNode(ISD::AND, DL, CondVT, Cond,
17050 DAG.getNode(ISD::BITCAST, DL, CondVT, LHS));
1705017051
1705117052 return DAG.getNode(ISD::BITCAST, DL, VT, Ret);
1705217053 }
0 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s
1
2 ; CHECK-LABEL: test
3 ; CHECK: vmovdqu32
4 ; CHECK: ret
5 define <16 x i32> @test() {
6 entry:
7 %0 = icmp slt <16 x i32> undef, undef
8 %1 = select <16 x i1> %0, <16 x i32> undef, <16 x i32> zeroinitializer
9 ret <16 x i32> %1
10 }