llvm.org GIT mirror llvm / 8030f1e
AMDGPU/GlobalISel: Define InstrMappings for G_FCMP Patch by Tom Stellard git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326587 91177308-0d34-0410-b5e6-96231b3b80d8 Matt Arsenault 2 years ago
2 changed file(s) with 78 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
311311 unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
312312 unsigned BankID = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI);
313313 OpdsMapping[0] = OpdsMapping[1] = AMDGPU::getValueMapping(BankID, Size);
314 break;
315 }
316 case AMDGPU::G_FCMP: {
317 unsigned Size = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
318 unsigned Op2Bank = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI);
319 OpdsMapping[0] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 1);
320 OpdsMapping[1] = nullptr; // Predicate Operand.
321 OpdsMapping[2] = AMDGPU::getValueMapping(Op2Bank, Size);
322 OpdsMapping[3] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, Size);
314323 break;
315324 }
316325 case AMDGPU::G_GEP: {
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -global-isel %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
2 # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -global-isel %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
3
4 ---
5 name: fcmp_ss
6 legalized: true
7
8 body: |
9 bb.0:
10 liveins: $sgpr0, $sgpr1
11 ; CHECK-LABEL: name: fcmp_ss
12 ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
13 ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
14 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
15 ; CHECK: [[FCMP:%[0-9]+]]:sgpr(s1) = G_FCMP floatpred(uge), [[COPY]](s32), [[COPY2]]
16 %0:_(s32) = COPY $sgpr0
17 %1:_(s32) = COPY $sgpr1
18 %2:_(s1) = G_FCMP floatpred(uge), %0(s32), %1
19 ...
20
21 ---
22 name: fcmp_sv
23 legalized: true
24
25 body: |
26 bb.0:
27 liveins: $sgpr0, $vgpr0
28 ; CHECK-LABEL: name: fcmp_sv
29 ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
30 ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
31 ; CHECK: [[FCMP:%[0-9]+]]:sgpr(s1) = G_FCMP floatpred(uge), [[COPY]](s32), [[COPY1]]
32 %0:_(s32) = COPY $sgpr0
33 %1:_(s32) = COPY $vgpr0
34 %2:_(s1) = G_FCMP floatpred(uge), %0, %1
35 ...
36
37 ---
38 name: fcmp_vs
39 legalized: true
40
41 body: |
42 bb.0:
43 liveins: $sgpr0, $vgpr0
44 ; CHECK-LABEL: name: fcmp_vs
45 ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
46 ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
47 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
48 ; CHECK: [[FCMP:%[0-9]+]]:sgpr(s1) = G_FCMP floatpred(uge), [[COPY1]](s32), [[COPY2]]
49 %0:_(s32) = COPY $sgpr0
50 %1:_(s32) = COPY $vgpr0
51 %2:_(s1) = G_FCMP floatpred(uge), %1, %0
52 ...
53
54 ---
55 name: fcmp_vv
56 legalized: true
57
58 body: |
59 bb.0:
60 liveins: $vgpr0, $vgpr1
61 ; CHECK-LABEL: name: fcmp_vv
62 ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
63 ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
64 ; CHECK: [[ICMP:%[0-9]+]]:sgpr(s1) = G_ICMP floatpred(uge), [[COPY]](s32), [[COPY1]]
65 %0:_(s32) = COPY $vgpr0
66 %1:_(s32) = COPY $vgpr1
67 %2:_(s1) = G_ICMP floatpred(uge), %0, %1
68 ...