llvm.org GIT mirror llvm / 7fdc66b
Add boolean simplification support from CMOV - If a boolean value is generated from CMOV and tested as boolean value, simplify the use of test result by referencing the original condition. RDRAND intrinisc is one of such cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163516 91177308-0d34-0410-b5e6-96231b3b80d8 Michael Liao 8 years ago
2 changed file(s) with 60 addition(s) and 14 deletion(s). Raw diff Collapse all Expand all
1415714157 if (SetCC.getOpcode() == ISD::ZERO_EXTEND)
1415814158 SetCC = SetCC.getOperand(0);
1415914159
14160 // Quit if not SETCC.
14161 // FIXME: So far we only handle the boolean value generated from SETCC. If
14162 // there is other ways to generate boolean values, we need handle them here
14163 // as well.
14164 if (SetCC.getOpcode() != X86ISD::SETCC)
14165 return SDValue();
14166
14167 // Set the condition code or opposite one if necessary.
14168 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
14169 if (needOppositeCond)
14170 CC = X86::GetOppositeBranchCondition(CC);
14171
14172 return SetCC.getOperand(1);
14160 switch (SetCC.getOpcode()) {
14161 case X86ISD::SETCC:
14162 // Set the condition code or opposite one if necessary.
14163 CC = X86::CondCode(SetCC.getConstantOperandVal(0));
14164 if (needOppositeCond)
14165 CC = X86::GetOppositeBranchCondition(CC);
14166 return SetCC.getOperand(1);
14167 case X86ISD::CMOV: {
14168 // Check whether false/true value has canonical one, i.e. 0 or 1.
14169 ConstantSDNode *FVal = dyn_cast(SetCC.getOperand(0));
14170 ConstantSDNode *TVal = dyn_cast(SetCC.getOperand(1));
14171 // Quit if true value is not a constant.
14172 if (!TVal)
14173 return SDValue();
14174 // Quit if false value is not a constant.
14175 if (!FVal) {
14176 // A special case for rdrand, where 0 is set if false cond is found.
14177 SDValue Op = SetCC.getOperand(0);
14178 if (Op.getOpcode() != X86ISD::RDRAND)
14179 return SDValue();
14180 }
14181 // Quit if false value is not the constant 0 or 1.
14182 bool FValIsFalse = true;
14183 if (FVal && FVal->getZExtValue() != 0) {
14184 if (FVal->getZExtValue() != 1)
14185 return SDValue();
14186 // If FVal is 1, opposite cond is needed.
14187 needOppositeCond = !needOppositeCond;
14188 FValIsFalse = false;
14189 }
14190 // Quit if TVal is not the constant opposite of FVal.
14191 if (FValIsFalse && TVal->getZExtValue() != 1)
14192 return SDValue();
14193 if (!FValIsFalse && TVal->getZExtValue() != 0)
14194 return SDValue();
14195 CC = X86::CondCode(SetCC.getConstantOperandVal(2));
14196 if (needOppositeCond)
14197 CC = X86::GetOppositeBranchCondition(CC);
14198 return SetCC.getOperand(3);
14199 }
14200 }
14201
14202 return SDValue();
1417314203 }
1417414204
1417514205 /// checkFlaggedOrCombine - DAG combination on X86ISD::OR, i.e. with EFLAGS
None ; RUN: llc < %s -march=x86-64 -mattr=+sse41,-avx | FileCheck %s
0 ; RUN: llc < %s -march=x86-64 -mattr=+sse41,-avx,+rdrand | FileCheck %s
11
22 define i32 @foo(<2 x i64> %c, i32 %a, i32 %b) {
33 %t1 = call i32 @llvm.x86.sse41.ptestz(<2 x i64> %c, <2 x i64> %c)
3838 ; CHECK: ret
3939 }
4040
41 define i32 @rnd(i32 %arg) nounwind uwtable {
42 %1 = tail call { i32, i32 } @llvm.x86.rdrand.32() nounwind
43 %2 = extractvalue { i32, i32 } %1, 0
44 %3 = extractvalue { i32, i32 } %1, 1
45 %4 = icmp eq i32 %3, 0
46 %5 = select i1 %4, i32 0, i32 %arg
47 %6 = add i32 %5, %2
48 ret i32 %6
49 ; CHECK: rnd
50 ; CHECK: rdrand
51 ; CHECK: cmov
52 ; CHECK-NOT: cmov
53 ; CHECK: ret
54 }
55
4156 declare i32 @llvm.x86.sse41.ptestz(<2 x i64>, <2 x i64>) nounwind readnone
57 declare { i32, i32 } @llvm.x86.rdrand.32() nounwind