llvm.org GIT mirror llvm / 7fd7ca4
Fix addrmode1 instruction encodings; fix bx_ret encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56277 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 11 years ago
3 changed file(s) with 50 addition(s) and 38 deletion(s). Raw diff Collapse all Expand all
259259 break;
260260 }
261261 case ARMII::BranchMisc: {
262 // Set bit[19:8] to 0xFFF
263 Binary |= 0xfff << 8;
262 if (TID.Opcode == ARM::BX)
263 abort(); // FIXME
264264 if (TID.Opcode == ARM::BX_RET)
265265 Binary |= 0xe; // the return register is LR
266266 else
150150 let Inst{24} = 1; // L bit
151151 let Inst{25-27} = {1,0,1};
152152 }
153 class ABLXI opcod, dag oops, dag iops, Format f, string asm,
154 list pattern>
155 : XI
156 "", pattern> {
157 let Inst{4-7} = {1,1,0,0};
158 let Inst{20-27} = {0,1,0,0,1,0,0,0};
159 }
160153 // FIXME: BX
161154 class AXIx2 opcod, dag oops, dag iops, Format f, string asm,
162155 list pattern>
519519 //
520520
521521 let isReturn = 1, isTerminator = 1 in
522 def BX_RET : AI<0x1, (outs), (ins), BranchMisc, "bx", " lr", [(ARMretflag)]>;
522 def BX_RET : AI<0x0, (outs), (ins), BranchMisc, "bx", " lr", [(ARMretflag)]> {
523 let Inst{4-7} = {1,0,0,0};
524 let Inst{8-19} = {1,1,1,1,1,1,1,1,1,1,1,1};
525 let Inst{20-27} = {0,1,0,0,1,0,0,0};
526 }
523527
524528 // FIXME: remove when we have a way to marking a MI with these properties.
525529 // FIXME: $dst1 should be a def. But the extra ops must be in the end of the
542546 [(ARMcall_pred tglobaladdr:$func)]>;
543547
544548 // ARMv5T and above
545 def BLX : ABLXI<0x2, (outs), (ins GPR:$func, variable_ops), BranchMisc,
549 def BLX : AXI<0x0, (outs), (ins GPR:$func, variable_ops), BranchMisc,
546550 "blx $func",
547 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T]>;
551 [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T]> {
552 let Inst{4-7} = {1,1,0,0};
553 let Inst{8-19} = {1,1,1,1,1,1,1,1,1,1,1,1};
554 let Inst{20-27} = {0,1,0,0,1,0,0,0};
555 }
556
548557 let Uses = [LR] in {
549558 // ARMv4T
550559 def BX : AXIx2<0x0, (outs), (ins GPR:$func, variable_ops),
742751 // Move Instructions.
743752 //
744753
745 def MOVr : AsI1<0xD, (outs GPR:$dst), (ins GPR:$src), DPRdReg,
754 def MOVr : AsI1<{1,0,1,1}, (outs GPR:$dst), (ins GPR:$src), DPRdReg,
746755 "mov", " $dst, $src", []>;
747 def MOVs : AsI1<0xD, (outs GPR:$dst), (ins so_reg:$src), DPRdSoReg,
756 def MOVs : AsI1<{1,0,1,1}, (outs GPR:$dst), (ins so_reg:$src), DPRdSoReg,
748757 "mov", " $dst, $src", [(set GPR:$dst, so_reg:$src)]>;
749758
750759 let isReMaterializable = 1 in
751 def MOVi : AsI1<0xD, (outs GPR:$dst), (ins so_imm:$src), DPRdIm,
760 def MOVi : AsI1<{1,0,1,1}, (outs GPR:$dst), (ins so_imm:$src), DPRdIm,
752761 "mov", " $dst, $src", [(set GPR:$dst, so_imm:$src)]>;
753762
754 def MOVrx : AsI1<0xD, (outs GPR:$dst), (ins GPR:$src), DPRdMisc,
763 def MOVrx : AsI1<{1,0,1,1}, (outs GPR:$dst), (ins GPR:$src), DPRdMisc,
755764 "mov", " $dst, $src, rrx",
756765 [(set GPR:$dst, (ARMrrx GPR:$src))]>;
757766
759768 // due to flag operands.
760769
761770 let Defs = [CPSR] in {
762 def MOVsrl_flag : AI1<0xD, (outs GPR:$dst), (ins GPR:$src), DPRdMisc,
771 def MOVsrl_flag : AI1<{1,0,1,1}, (outs GPR:$dst), (ins GPR:$src), DPRdMisc,
763772 "mov", "s $dst, $src, lsr #1",
764773 [(set GPR:$dst, (ARMsrl_flag GPR:$src))]>;
765 def MOVsra_flag : AI1<0xD, (outs GPR:$dst), (ins GPR:$src), DPRdMisc,
774 def MOVsra_flag : AI1<{1,0,1,1}, (outs GPR:$dst), (ins GPR:$src), DPRdMisc,
766775 "mov", "s $dst, $src, asr #1",
767776 [(set GPR:$dst, (ARMsra_flag GPR:$src))]>;
768777 }
810819 // Arithmetic Instructions.
811820 //
812821
813 defm ADD : AsI1_bin_irs<0x4, "add", BinOpFrag<(add node:$LHS, node:$RHS)>>;
814 defm SUB : AsI1_bin_irs<0x2, "sub", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
822 defm ADD : AsI1_bin_irs<{0,0,1,0}, "add",
823 BinOpFrag<(add node:$LHS, node:$RHS)>>;
824 defm SUB : AsI1_bin_irs<{0,1,0,0}, "sub",
825 BinOpFrag<(sub node:$LHS, node:$RHS)>>;
815826
816827 // ADD and SUB with 's' bit set.
817 defm ADDS : ASI1_bin_s_irs<0x4, "add", BinOpFrag<(addc node:$LHS, node:$RHS)>>;
818 defm SUBS : ASI1_bin_s_irs<0x2, "sub", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
828 defm ADDS : ASI1_bin_s_irs<{0,0,1,0}, "add",
829 BinOpFrag<(addc node:$LHS, node:$RHS)>>;
830 defm SUBS : ASI1_bin_s_irs<{0,1,0,0}, "sub",
831 BinOpFrag<(subc node:$LHS, node:$RHS)>>;
819832
820833 // FIXME: Do not allow ADC / SBC to be predicated for now.
821 defm ADC : AsXI1_bin_c_irs<0x5, "adc", BinOpFrag<(adde node:$LHS, node:$RHS)>>;
822 defm SBC : AsXI1_bin_c_irs<0x6, "sbc", BinOpFrag<(sube node:$LHS, node:$RHS)>>;
834 defm ADC : AsXI1_bin_c_irs<{1,0,1,0}, "adc",
835 BinOpFrag<(adde node:$LHS, node:$RHS)>>;
836 defm SBC : AsXI1_bin_c_irs<{0,1,1,0}, "sbc",
837 BinOpFrag<(sube node:$LHS, node:$RHS)>>;
823838
824839 // These don't define reg/reg forms, because they are handled above.
825 def RSBri : AsI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPRIm,
840 def RSBri : AsI1<{1,1,0,0}, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPRIm,
826841 "rsb", " $dst, $a, $b",
827842 [(set GPR:$dst, (sub so_imm:$b, GPR:$a))]>;
828843
829 def RSBrs : AsI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPRSoReg,
844 def RSBrs : AsI1<{1,1,0,0}, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPRSoReg,
830845 "rsb", " $dst, $a, $b",
831846 [(set GPR:$dst, (sub so_reg:$b, GPR:$a))]>;
832847
833848 // RSB with 's' bit set.
834849 let Defs = [CPSR] in {
835 def RSBSri : AI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPRIm,
850 def RSBSri : AI1<{1,1,0,0}, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPRIm,
836851 "rsb", "s $dst, $a, $b",
837852 [(set GPR:$dst, (subc so_imm:$b, GPR:$a))]>;
838 def RSBSrs : AI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPRSoReg,
853 def RSBSrs : AI1<{1,1,0,0}, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPRSoReg,
839854 "rsb", "s $dst, $a, $b",
840855 [(set GPR:$dst, (subc so_reg:$b, GPR:$a))]>;
841856 }
842857
843858 // FIXME: Do not allow RSC to be predicated for now. But they can set CPSR.
844859 let Uses = [CPSR] in {
845 def RSCri : AXI1<0x7, (outs GPR:$dst), (ins GPR:$a, so_imm:$b, cc_out:$s),
860 def RSCri : AXI1<{1,1,1,0}, (outs GPR:$dst), (ins GPR:$a, so_imm:$b, cc_out:$s),
846861 DPRIm, "rsc${s} $dst, $a, $b",
847862 [(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>;
848 def RSCrs : AXI1<0x7, (outs GPR:$dst), (ins GPR:$a, so_reg:$b, cc_out:$s),
863 def RSCrs : AXI1<{1,1,1,0}, (outs GPR:$dst), (ins GPR:$a, so_reg:$b, cc_out:$s),
849864 DPRSoReg, "rsc${s} $dst, $a, $b",
850865 [(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>;
851866 }
870885 // Bitwise Instructions.
871886 //
872887
873 defm AND : AsI1_bin_irs<0x0, "and", BinOpFrag<(and node:$LHS, node:$RHS)>>;
874 defm ORR : AsI1_bin_irs<0xC, "orr", BinOpFrag<(or node:$LHS, node:$RHS)>>;
875 defm EOR : AsI1_bin_irs<0x1, "eor", BinOpFrag<(xor node:$LHS, node:$RHS)>>;
876 defm BIC : AsI1_bin_irs<0xE, "bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
877
878 def MVNr : AsI1<0xE, (outs GPR:$dst), (ins GPR:$src), DPRdReg,
888 defm AND : AsI1_bin_irs<{0,0,0,0}, "and",
889 BinOpFrag<(and node:$LHS, node:$RHS)>>;
890 defm ORR : AsI1_bin_irs<{0,0,1,1}, "orr",
891 BinOpFrag<(or node:$LHS, node:$RHS)>>;
892 defm EOR : AsI1_bin_irs<{1,0,0,0}, "eor",
893 BinOpFrag<(xor node:$LHS, node:$RHS)>>;
894 defm BIC : AsI1_bin_irs<{0,1,1,1}, "bic",
895 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
896
897 def MVNr : AsI1<{1,1,1,1}, (outs GPR:$dst), (ins GPR:$src), DPRdReg,
879898 "mvn", " $dst, $src", [(set GPR:$dst, (not GPR:$src))]>;
880 def MVNs : AsI1<0xE, (outs GPR:$dst), (ins so_reg:$src), DPRdSoReg,
899 def MVNs : AsI1<{1,1,1,1}, (outs GPR:$dst), (ins so_reg:$src), DPRdSoReg,
881900 "mvn", " $dst, $src", [(set GPR:$dst, (not so_reg:$src))]>;
882901 let isReMaterializable = 1 in
883 def MVNi : AsI1<0xE, (outs GPR:$dst), (ins so_imm:$imm), DPRdIm,
902 def MVNi : AsI1<{1,1,1,1}, (outs GPR:$dst), (ins so_imm:$imm), DPRdIm,
884903 "mvn", " $dst, $imm", [(set GPR:$dst, so_imm_not:$imm)]>;
885904
886905 def : ARMPat<(and GPR:$src, so_imm_not:$imm),