llvm.org GIT mirror llvm / 7fb8b0c
Update more places to use target specific nodes for vector shifts instead of intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148685 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 8 years ago
1 changed file(s) with 19 addition(s) and 42 deletion(s). Raw diff Collapse all Expand all
99339933 // AhiBlo = __builtin_ia32_psllqi256( AhiBlo, 32 );
99349934 // return AloBlo + AloBhi + AhiBlo;
99359935
9936 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9937 DAG.getConstant(Intrinsic::x86_avx2_psrli_q, MVT::i32),
9938 A, DAG.getConstant(32, MVT::i32));
9939 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9940 DAG.getConstant(Intrinsic::x86_avx2_psrli_q, MVT::i32),
9941 B, DAG.getConstant(32, MVT::i32));
9936 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A,
9937 DAG.getConstant(32, MVT::i32));
9938 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B,
9939 DAG.getConstant(32, MVT::i32));
99429940 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
99439941 DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32),
99449942 A, B);
99489946 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
99499947 DAG.getConstant(Intrinsic::x86_avx2_pmulu_dq, MVT::i32),
99509948 Ahi, B);
9951 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9952 DAG.getConstant(Intrinsic::x86_avx2_pslli_q, MVT::i32),
9953 AloBhi, DAG.getConstant(32, MVT::i32));
9954 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9955 DAG.getConstant(Intrinsic::x86_avx2_pslli_q, MVT::i32),
9956 AhiBlo, DAG.getConstant(32, MVT::i32));
9949 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi,
9950 DAG.getConstant(32, MVT::i32));
9951 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo,
9952 DAG.getConstant(32, MVT::i32));
99579953 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
99589954 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
99599955 return Res;
99719967 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 );
99729968 // return AloBlo + AloBhi + AhiBlo;
99739969
9974 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9975 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9976 A, DAG.getConstant(32, MVT::i32));
9977 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9978 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32),
9979 B, DAG.getConstant(32, MVT::i32));
9970 SDValue Ahi = DAG.getNode(X86ISD::VSRLI, dl, VT, A,
9971 DAG.getConstant(32, MVT::i32));
9972 SDValue Bhi = DAG.getNode(X86ISD::VSRLI, dl, VT, B,
9973 DAG.getConstant(32, MVT::i32));
99809974 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
99819975 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
99829976 A, B);
99869980 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
99879981 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32),
99889982 Ahi, B);
9989 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9990 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9991 AloBhi, DAG.getConstant(32, MVT::i32));
9992 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
9993 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32),
9994 AhiBlo, DAG.getConstant(32, MVT::i32));
9983 AloBhi = DAG.getNode(X86ISD::VSHLI, dl, VT, AloBhi,
9984 DAG.getConstant(32, MVT::i32));
9985 AhiBlo = DAG.getNode(X86ISD::VSHLI, dl, VT, AhiBlo,
9986 DAG.getConstant(32, MVT::i32));
99959987 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi);
99969988 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo);
99979989 return Res;
1368713679 // Validate that the Mask operand is a vector sra node.
1368813680 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but
1368913681 // there is no psrai.b
13690 SDValue SraSrc, SraC;
13691 if (Mask.getOpcode() == ISD::INTRINSIC_WO_CHAIN) {
13692 switch (cast(Mask.getOperand(0))->getZExtValue()) {
13693 case Intrinsic::x86_sse2_psrai_w:
13694 case Intrinsic::x86_sse2_psrai_d:
13695 case Intrinsic::x86_avx2_psrai_w:
13696 case Intrinsic::x86_avx2_psrai_d:
13697 break;
13698 default: return SDValue();
13699 }
13700
13701 SraSrc = Mask.getOperand(1);
13702 SraC = Mask.getOperand(2);
13703 } else if (Mask.getOpcode() == X86ISD::VSRAI) {
13704 SraSrc = Mask.getOperand(0);
13705 SraC = Mask.getOperand(1);
13706 } else
13682 if (Mask.getOpcode() != X86ISD::VSRAI)
1370713683 return SDValue();
1370813684
1370913685 // Check that the SRA is all signbits.
13686 SDValue SraC = Mask.getOperand(1);
1371013687 unsigned SraAmt = cast(SraC)->getZExtValue();
1371113688 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits();
1371213689 if ((SraAmt + 1) != EltBits)
1372413701 X.getValueType() == MaskVT && Y.getValueType() == MaskVT) {
1372513702 assert((EltBits == 8 || EltBits == 16 || EltBits == 32) &&
1372613703 "Unsupported VT for PSIGN");
13727 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, SraSrc);
13704 Mask = DAG.getNode(X86ISD::PSIGN, DL, MaskVT, X, Mask.getOperand(0));
1372813705 return DAG.getNode(ISD::BITCAST, DL, VT, Mask);
1372913706 }
1373013707 // PBLENDVB only available on SSE 4.1