llvm.org GIT mirror llvm / 7f9dbc4
AMDGPU/GlobalISel: Legality and RegBankInfo for G_{INSERT|EXTRACT}_VECTOR_ELT git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327269 91177308-0d34-0410-b5e6-96231b3b80d8 Matt Arsenault 2 years ago
6 changed file(s) with 462 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
106106 setAction({G_LOAD, 1, S64}, Legal);
107107 setAction({G_STORE, 1, S64}, Legal);
108108
109 for (unsigned Op : {G_EXTRACT_VECTOR_ELT, G_INSERT_VECTOR_ELT}) {
110 getActionDefinitionsBuilder(Op)
111 .legalIf([=](const LegalityQuery &Query) {
112 const LLT &VecTy = Query.Types[1];
113 const LLT &IdxTy = Query.Types[2];
114 return VecTy.getSizeInBits() % 32 == 0 &&
115 VecTy.getSizeInBits() <= 512 &&
116 IdxTy.getSizeInBits() == 32;
117 });
118 }
119
109120 // FIXME: Doesn't handle extract of illegal sizes.
110121 getActionDefinitionsBuilder(G_EXTRACT)
111122 .unsupportedIf([=](const LegalityQuery &Query) {
4747 (void)RBVGPR;
4848 assert(&RBVGPR == &AMDGPU::VGPRRegBank);
4949
50 }
51
52 static bool isConstant(const MachineOperand &MO, int64_t &C) {
53 const MachineFunction *MF = MO.getParent()->getParent()->getParent();
54 const MachineRegisterInfo &MRI = MF->getRegInfo();
55 const MachineInstr *Def = MRI.getVRegDef(MO.getReg());
56 if (!Def)
57 return false;
58
59 if (Def->getOpcode() == AMDGPU::G_CONSTANT) {
60 C = Def->getOperand(1).getCImm()->getSExtValue();
61 return true;
62 }
63
64 if (Def->getOpcode() == AMDGPU::COPY)
65 return isConstant(Def->getOperand(1), C);
66
67 return false;
5068 }
5169
5270 unsigned AMDGPURegisterBankInfo::copyCost(const RegisterBank &Dst,
412430 OpdsMapping[1] = nullptr; // Predicate Operand.
413431 OpdsMapping[2] = AMDGPU::getValueMapping(Op2Bank, Size);
414432 OpdsMapping[3] = AMDGPU::getValueMapping(Op3Bank, Size);
433 break;
434 }
435
436
437 case AMDGPU::G_EXTRACT_VECTOR_ELT: {
438 unsigned IdxOp = 2;
439 int64_t Imm;
440 // XXX - Do we really need to fully handle these? The constant case should
441 // be legalized away before RegBankSelect?
442
443 unsigned OutputBankID = isSALUMapping(MI) && isConstant(MI.getOperand(IdxOp), Imm) ?
444 AMDGPU::SGPRRegBankID : AMDGPU::VGPRRegBankID;
445
446 unsigned IdxBank = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI);
447 OpdsMapping[0] = AMDGPU::getValueMapping(OutputBankID, MRI.getType(MI.getOperand(0).getReg()).getSizeInBits());
448 OpdsMapping[1] = AMDGPU::getValueMapping(OutputBankID, MRI.getType(MI.getOperand(1).getReg()).getSizeInBits());
449
450 // The index can be either if the source vector is VGPR.
451 OpdsMapping[2] = AMDGPU::getValueMapping(IdxBank, MRI.getType(MI.getOperand(2).getReg()).getSizeInBits());
452 break;
453 }
454 case AMDGPU::G_INSERT_VECTOR_ELT: {
455 // XXX - Do we really need to fully handle these? The constant case should
456 // be legalized away before RegBankSelect?
457
458 int64_t Imm;
459
460 unsigned IdxOp = MI.getOpcode() == AMDGPU::G_EXTRACT_VECTOR_ELT ? 2 : 3;
461 unsigned BankID = isSALUMapping(MI) && isConstant(MI.getOperand(IdxOp), Imm) ?
462 AMDGPU::SGPRRegBankID : AMDGPU::VGPRRegBankID;
463
464
465
466 // TODO: Can do SGPR indexing, which would obviate the need for the
467 // isConstant check.
468 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
469 unsigned Size = getSizeInBits(MI.getOperand(i).getReg(), MRI, *TRI);
470 OpdsMapping[i] = AMDGPU::getValueMapping(BankID, Size);
471 }
472
473
415474 break;
416475 }
417476 case AMDGPU::G_INTRINSIC: {
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -global-isel %s -o - | FileCheck %s
2
3 ---
4 name: extract_vector_elt_0_v2i32
5
6 body: |
7 bb.0:
8 liveins: $vgpr0_vgpr1
9 ; CHECK-LABEL: name: extract_vector_elt_0_v2i32
10 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
11 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
12 ; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s32>), [[C]](s32)
13 ; CHECK: $vgpr0 = COPY [[EVEC]](s32)
14 %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
15 %1:_(s32) = G_CONSTANT i32 0
16 %2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %1
17 $vgpr0 = COPY %2
18 ...
19 ---
20 name: extract_vector_elt_0_v3i32
21
22 body: |
23 bb.0:
24 liveins: $vgpr0_vgpr1_vgpr2
25 ; CHECK-LABEL: name: extract_vector_elt_0_v3i32
26 ; CHECK: [[COPY:%[0-9]+]]:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
27 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
28 ; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<3 x s32>), [[C]](s32)
29 ; CHECK: $vgpr0 = COPY [[EVEC]](s32)
30 %0:_(<3 x s32>) = COPY $vgpr0_vgpr1_vgpr2
31 %1:_(s32) = G_CONSTANT i32 0
32 %2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %1
33 $vgpr0 = COPY %2
34 ...
35 ---
36 name: extract_vector_elt_0_v4i32
37
38 body: |
39 bb.0:
40 liveins: $vgpr0_vgpr1_vgpr2_vgpr3
41 ; CHECK-LABEL: name: extract_vector_elt_0_v4i32
42 ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
43 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
44 ; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<4 x s32>), [[C]](s32)
45 ; CHECK: $vgpr0 = COPY [[EVEC]](s32)
46 %0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
47 %1:_(s32) = G_CONSTANT i32 0
48 %2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %1
49 $vgpr0 = COPY %2
50 ...
51
52 ---
53 name: extract_vector_elt_0_v5i32
54
55 body: |
56 bb.0:
57 liveins: $vgpr0
58 ; CHECK-LABEL: name: extract_vector_elt_0_v5i32
59 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
60 ; CHECK: [[MV:%[0-9]+]]:_(<5 x s32>) = G_MERGE_VALUES [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32)
61 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
62 ; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[MV]](<5 x s32>), [[C]](s32)
63 ; CHECK: $vgpr0 = COPY [[EVEC]](s32)
64 %0:_(s32) = COPY $vgpr0
65 %1:_(<5 x s32>) = G_MERGE_VALUES %0, %0, %0, %0, %0
66 %2:_(s32) = G_CONSTANT i32 0
67 %3:_(s32) = G_EXTRACT_VECTOR_ELT %1, %2
68 $vgpr0 = COPY %3
69 ...
70
71 ---
72 name: extract_vector_elt_0_v6i32
73
74 body: |
75 bb.0:
76 liveins: $vgpr0
77 ; CHECK-LABEL: name: extract_vector_elt_0_v6i32
78 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
79 ; CHECK: [[MV:%[0-9]+]]:_(<6 x s32>) = G_MERGE_VALUES [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32)
80 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
81 ; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[MV]](<6 x s32>), [[C]](s32)
82 ; CHECK: $vgpr0 = COPY [[EVEC]](s32)
83 %0:_(s32) = COPY $vgpr0
84 %1:_(<6 x s32>) = G_MERGE_VALUES %0, %0, %0, %0, %0, %0
85 %2:_(s32) = G_CONSTANT i32 0
86 %3:_(s32) = G_EXTRACT_VECTOR_ELT %1, %2
87 $vgpr0 = COPY %3
88 ...
89
90 ---
91 name: extract_vector_elt_0_v7i32
92
93 body: |
94 bb.0:
95 liveins: $vgpr0
96 ; CHECK-LABEL: name: extract_vector_elt_0_v7i32
97 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
98 ; CHECK: [[MV:%[0-9]+]]:_(<7 x s32>) = G_MERGE_VALUES [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32)
99 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
100 ; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[MV]](<7 x s32>), [[C]](s32)
101 ; CHECK: $vgpr0 = COPY [[EVEC]](s32)
102 %0:_(s32) = COPY $vgpr0
103 %1:_(<7 x s32>) = G_MERGE_VALUES %0, %0, %0, %0, %0, %0, %0
104 %2:_(s32) = G_CONSTANT i32 0
105 %3:_(s32) = G_EXTRACT_VECTOR_ELT %1, %2
106 $vgpr0 = COPY %3
107 ...
108
109 ---
110 name: extract_vector_elt_0_v8i32
111
112 body: |
113 bb.0:
114 liveins: $vgpr0
115 ; CHECK-LABEL: name: extract_vector_elt_0_v8i32
116 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
117 ; CHECK: [[MV:%[0-9]+]]:_(<8 x s32>) = G_MERGE_VALUES [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32)
118 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
119 ; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[MV]](<8 x s32>), [[C]](s32)
120 ; CHECK: $vgpr0 = COPY [[EVEC]](s32)
121 %0:_(s32) = COPY $vgpr0
122 %1:_(<8 x s32>) = G_MERGE_VALUES %0, %0, %0, %0, %0, %0, %0, %0
123 %2:_(s32) = G_CONSTANT i32 0
124 %3:_(s32) = G_EXTRACT_VECTOR_ELT %1, %2
125 $vgpr0 = COPY %3
126 ...
127
128 ---
129 name: extract_vector_elt_0_v16i32
130
131 body: |
132 bb.0:
133 liveins: $vgpr0
134 ; CHECK-LABEL: name: extract_vector_elt_0_v16i32
135 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
136 ; CHECK: [[MV:%[0-9]+]]:_(<16 x s32>) = G_MERGE_VALUES [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32), [[COPY]](s32)
137 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
138 ; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[MV]](<16 x s32>), [[C]](s32)
139 ; CHECK: $vgpr0 = COPY [[EVEC]](s32)
140 %0:_(s32) = COPY $vgpr0
141 %1:_(<16 x s32>) = G_MERGE_VALUES %0, %0, %0, %0, %0, %0, %0, %0, %0, %0, %0, %0, %0, %0, %0, %0
142 %2:_(s32) = G_CONSTANT i32 0
143 %3:_(s32) = G_EXTRACT_VECTOR_ELT %1, %2
144 $vgpr0 = COPY %3
145 ...
146
147 ---
148 name: extract_vector_elt_var_v2i32
149
150 body: |
151 bb.0:
152 liveins: $vgpr0_vgpr1, $vgpr2
153 ; CHECK-LABEL: name: extract_vector_elt_var_v2i32
154 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
155 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
156 ; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s32>), [[COPY1]](s32)
157 ; CHECK: $vgpr0 = COPY [[EVEC]](s32)
158 %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
159 %1:_(s32) = COPY $vgpr2
160 %2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %1
161 $vgpr0 = COPY %2
162 ...
163
164 ---
165 name: extract_vector_elt_var_v8i32
166
167 body: |
168 bb.0:
169 liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
170 ; CHECK-LABEL: name: extract_vector_elt_var_v8i32
171 ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
172 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
173 ; CHECK: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<8 x s32>), [[COPY1]](s32)
174 ; CHECK: $vgpr0 = COPY [[EVEC]](s32)
175 %0:_(<8 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
176 %1:_(s32) = COPY $vgpr2
177 %2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %1
178 $vgpr0 = COPY %2
179 ...
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -global-isel %s -o - | FileCheck %s
2
3 ---
4 name: insert_vector_elt_0_v2i32
5
6 body: |
7 bb.0:
8 liveins: $vgpr0_vgpr1, $vgpr2
9 ; CHECK-LABEL: name: insert_vector_elt_0_v2i32
10 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
11 ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
12 ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
13 ; CHECK: [[IVEC:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[COPY1]](s32), [[C]](s32)
14 ; CHECK: $vgpr0_vgpr1 = COPY [[IVEC]](<2 x s32>)
15 %0:_(<2 x s32>) = COPY $vgpr0_vgpr1
16 %1:_(s32) = COPY $vgpr2
17 %2:_(s32) = G_CONSTANT i32 0
18 %3:_(<2 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
19 $vgpr0_vgpr1 = COPY %3
20 ...
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -global-isel %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
2
3 ---
4 name: extract_vector_elt_0_v2i32_s
5 legalized: true
6
7 body: |
8 bb.0:
9 liveins: $sgpr0_sgpr1
10 ; CHECK-LABEL: name: extract_vector_elt_0_v2i32_s
11 ; CHECK: [[COPY:%[0-9]+]]:sgpr(<2 x s32>) = COPY $sgpr0_sgpr1
12 ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
13 ; CHECK: [[EVEC:%[0-9]+]]:sgpr(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s32>), [[C]](s32)
14 ; CHECK: $vgpr0 = COPY [[EVEC]](s32)
15 %0:_(<2 x s32>) = COPY $sgpr0_sgpr1
16 %1:_(s32) = G_CONSTANT i32 0
17 %2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %1
18 $vgpr0 = COPY %2
19 ...
20
21
22 ---
23 name: extract_vector_elt_0_v4i32_s
24 legalized: true
25
26 body: |
27 bb.0:
28 liveins: $sgpr0_sgpr1_sgpr2_sgpr3
29 ; CHECK-LABEL: name: extract_vector_elt_0_v4i32_s
30 ; CHECK: [[COPY:%[0-9]+]]:sgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
31 ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
32 ; CHECK: [[EVEC:%[0-9]+]]:sgpr(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<4 x s32>), [[C]](s32)
33 ; CHECK: $vgpr0 = COPY [[EVEC]](s32)
34 %0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
35 %1:_(s32) = G_CONSTANT i32 0
36 %2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %1
37 $vgpr0 = COPY %2
38 ...
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -global-isel %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
2
3 ---
4 name: insert_vector_elt_v4i32_s_s_k
5 legalized: true
6
7 body: |
8 bb.0:
9 liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr5
10 ; CHECK-LABEL: name: insert_vector_elt_v4i32_s_s_k
11 ; CHECK: [[COPY:%[0-9]+]]:sgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
12 ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
13 ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
14 ; CHECK: [[IVEC:%[0-9]+]]:sgpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[COPY1]](s32), [[C]](s32)
15 ; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[IVEC]](<4 x s32>)
16 %0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
17 %1:_(s32) = COPY $sgpr5
18 %2:_(s32) = G_CONSTANT i32 0
19 %3:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
20 $sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3
21 ...
22
23 ---
24 name: insert_vector_elt_v4i32_v_s_k
25 legalized: true
26
27 body: |
28 bb.0:
29 liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr5
30 ; CHECK-LABEL: name: insert_vector_elt_v4i32_v_s_k
31 ; CHECK: [[COPY:%[0-9]+]]:vgpr(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
32 ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
33 ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
34 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
35 ; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
36 ; CHECK: [[IVEC:%[0-9]+]]:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[COPY2]](s32), [[COPY3]](s32)
37 ; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[IVEC]](<4 x s32>)
38 %0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
39 %1:_(s32) = COPY $sgpr5
40 %2:_(s32) = G_CONSTANT i32 0
41 %3:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
42 $sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3
43 ...
44
45 ---
46 name: insert_vector_elt_v4i32_s_v_k
47 legalized: true
48
49 body: |
50 bb.0:
51 liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $vgpr5
52 ; CHECK-LABEL: name: insert_vector_elt_v4i32_s_v_k
53 ; CHECK: [[COPY:%[0-9]+]]:sgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
54 ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr2
55 ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
56 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(<4 x s32>) = COPY [[COPY]](<4 x s32>)
57 ; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
58 ; CHECK: [[IVEC:%[0-9]+]]:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY2]], [[COPY1]](s32), [[COPY3]](s32)
59 ; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[IVEC]](<4 x s32>)
60 %0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
61 %1:_(s32) = COPY $vgpr2
62 %2:_(s32) = G_CONSTANT i32 0
63 %3:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
64 $sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3
65 ...
66
67 ---
68 name: insert_vector_elt_var_v4i32_s_s_s
69 legalized: true
70
71 body: |
72 bb.0:
73 liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr5, $sgpr6
74 ; CHECK-LABEL: name: insert_vector_elt_var_v4i32_s_s_s
75 ; CHECK: [[COPY:%[0-9]+]]:sgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
76 ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
77 ; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr6
78 ; CHECK: [[COPY3:%[0-9]+]]:vgpr(<4 x s32>) = COPY [[COPY]](<4 x s32>)
79 ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
80 ; CHECK: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)
81 ; CHECK: [[IVEC:%[0-9]+]]:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY3]], [[COPY4]](s32), [[COPY5]](s32)
82 ; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[IVEC]](<4 x s32>)
83 %0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
84 %1:_(s32) = COPY $sgpr5
85 %2:_(s32) = COPY $sgpr6
86 %3:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
87 $sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3
88 ...
89
90 ---
91 name: insert_vector_elt_var_v4i32_s_s_v
92 legalized: true
93
94 body: |
95 bb.0:
96 liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr5, $vgpr6
97 ; CHECK-LABEL: name: insert_vector_elt_var_v4i32_s_s_v
98 ; CHECK: [[COPY:%[0-9]+]]:sgpr(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
99 ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
100 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr6
101 ; CHECK: [[COPY3:%[0-9]+]]:vgpr(<4 x s32>) = COPY [[COPY]](<4 x s32>)
102 ; CHECK: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
103 ; CHECK: [[IVEC:%[0-9]+]]:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY3]], [[COPY4]](s32), [[COPY2]](s32)
104 ; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[IVEC]](<4 x s32>)
105 %0:_(<4 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
106 %1:_(s32) = COPY $sgpr5
107 %2:_(s32) = COPY $vgpr6
108 %3:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
109 $sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3
110 ...
111
112 ---
113 name: insert_vector_elt_var_v4i32_v_s_v
114 legalized: true
115
116 body: |
117 bb.0:
118 liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr5, $vgpr6
119 ; CHECK-LABEL: name: insert_vector_elt_var_v4i32_v_s_v
120 ; CHECK: [[COPY:%[0-9]+]]:vgpr(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
121 ; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr5
122 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr6
123 ; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
124 ; CHECK: [[IVEC:%[0-9]+]]:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[COPY3]](s32), [[COPY2]](s32)
125 ; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[IVEC]](<4 x s32>)
126 %0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
127 %1:_(s32) = COPY $sgpr5
128 %2:_(s32) = COPY $vgpr6
129 %3:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
130 $sgpr0_sgpr1_sgpr2_sgpr3 = COPY %3
131 ...
132
133 ---
134 name: insert_vector_elt_var_v4i32_v_v_v
135 legalized: true
136
137 body: |
138 bb.0:
139 liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr5, $vgpr6
140 ; CHECK-LABEL: name: insert_vector_elt_var_v4i32_v_v_v
141 ; CHECK: [[COPY:%[0-9]+]]:vgpr(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
142 ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr5
143 ; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr6
144 ; CHECK: [[IVEC:%[0-9]+]]:vgpr(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], [[COPY1]](s32), [[COPY2]](s32)
145 ; CHECK: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[IVEC]](<4 x s32>)
146 %0:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
147 %1:_(s32) = COPY $vgpr5
148 %2:_(s32) = COPY $vgpr6
149 %3:_(<4 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
150 $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %3
151 ...