llvm.org GIT mirror llvm / 7f0f287
Merging r322106: ------------------------------------------------------------------------ r322106 | abataev | 2018-01-09 11:08:22 -0800 (Tue, 09 Jan 2018) | 11 lines [COST]Fix PR35865: Fix cost model evaluation for shuffle on X86. Summary: If the vector type is transformed to non-vector single type, the compile may crash trying to get vector information about non-vector type. Reviewers: RKSimon, spatel, mkuper, hfinkel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41862 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@322680 91177308-0d34-0410-b5e6-96231b3b80d8 Hans Wennborg 1 year, 8 months ago
2 changed file(s) with 29 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
753753 // type remains the same.
754754 if (Kind == TTI::SK_PermuteSingleSrc && LT.first != 1) {
755755 MVT LegalVT = LT.second;
756 if (LegalVT.getVectorElementType().getSizeInBits() ==
756 if (LegalVT.isVector() &&
757 LegalVT.getVectorElementType().getSizeInBits() ==
757758 Tp->getVectorElementType()->getPrimitiveSizeInBits() &&
758759 LegalVT.getVectorNumElements() < Tp->getVectorNumElements()) {
759760
0 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
1 ; RUN: opt -slp-vectorizer < %s -S -o - -mtriple=x86_64-apple-macosx10.10.0 -mcpu=core2 | FileCheck %s
2
3 define void @_Z10fooConvertPDv4_xS0_S0_PKS_() {
4 ; CHECK-LABEL: @_Z10fooConvertPDv4_xS0_S0_PKS_(
5 ; CHECK-NEXT: entry:
6 ; CHECK-NEXT: [[TMP0:%.*]] = extractelement <16 x half> undef, i32 4
7 ; CHECK-NEXT: [[CONV_I_4_I:%.*]] = fpext half [[TMP0]] to float
8 ; CHECK-NEXT: [[TMP1:%.*]] = bitcast float [[CONV_I_4_I]] to i32
9 ; CHECK-NEXT: [[VECINS_I_4_I:%.*]] = insertelement <8 x i32> undef, i32 [[TMP1]], i32 4
10 ; CHECK-NEXT: [[TMP2:%.*]] = extractelement <16 x half> undef, i32 5
11 ; CHECK-NEXT: [[CONV_I_5_I:%.*]] = fpext half [[TMP2]] to float
12 ; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[CONV_I_5_I]] to i32
13 ; CHECK-NEXT: [[VECINS_I_5_I:%.*]] = insertelement <8 x i32> [[VECINS_I_4_I]], i32 [[TMP3]], i32 5
14 ; CHECK-NEXT: ret void
15 ;
16 entry:
17 %0 = extractelement <16 x half> undef, i32 4
18 %conv.i.4.i = fpext half %0 to float
19 %1 = bitcast float %conv.i.4.i to i32
20 %vecins.i.4.i = insertelement <8 x i32> undef, i32 %1, i32 4
21 %2 = extractelement <16 x half> undef, i32 5
22 %conv.i.5.i = fpext half %2 to float
23 %3 = bitcast float %conv.i.5.i to i32
24 %vecins.i.5.i = insertelement <8 x i32> %vecins.i.4.i, i32 %3, i32 5
25 ret void
26 }