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[AMDGPU][MC][GFX9] Corrected encoding of ttmp registers, disabled tba/tma See bugs 35494 and 35559: https://bugs.llvm.org/show_bug.cgi?id=35494 https://bugs.llvm.org/show_bug.cgi?id=35559 Reviewers: vpykhtin, artem.tamazov, arsenm Differential Revision: https://reviews.llvm.org/D41007 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320375 91177308-0d34-0410-b5e6-96231b3b80d8 Dmitry Preobrazhensky 2 years ago
14 changed file(s) with 403 addition(s) and 84 deletion(s). Raw diff Collapse all Expand all
25772577
25782578 bool AMDGPUAsmParser::subtargetHasRegister(const MCRegisterInfo &MRI,
25792579 unsigned RegNo) const {
2580
2581 for (MCRegAliasIterator R(AMDGPU::TTMP12_TTMP13_TTMP14_TTMP15, &MRI, true);
2582 R.isValid(); ++R) {
2583 if (*R == RegNo)
2584 return isGFX9();
2585 }
2586
2587 switch (RegNo) {
2588 case AMDGPU::TBA:
2589 case AMDGPU::TBA_LO:
2590 case AMDGPU::TBA_HI:
2591 case AMDGPU::TMA:
2592 case AMDGPU::TMA_LO:
2593 case AMDGPU::TMA_HI:
2594 return !isGFX9();
2595 default:
2596 break;
2597 }
2598
25802599 if (isCI())
25812600 return true;
25822601
249249 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst);
250250 if (SDst != -1) {
251251 // VOPC - insert VCC register as sdst
252 insertNamedMCOperand(MI, MCOperand::createReg(AMDGPU::VCC),
252 insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC),
253253 AMDGPU::OpName::sdst);
254254 } else {
255255 // VOP1/2 - insert omod if present in instruction
276276
277277 inline
278278 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const {
279 return MCOperand::createReg(RegId);
279 return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI));
280280 }
281281
282282 inline
570570 }
571571 }
572572
573 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const {
574 using namespace AMDGPU::EncValues;
575
576 unsigned TTmpMin = isGFX9() ? TTMP_GFX9_MIN : TTMP_VI_MIN;
577 unsigned TTmpMax = isGFX9() ? TTMP_GFX9_MAX : TTMP_VI_MAX;
578
579 return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1;
580 }
581
573582 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val) const {
574583 using namespace AMDGPU::EncValues;
575584
582591 assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning.
583592 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN);
584593 }
585 if (TTMP_MIN <= Val && Val <= TTMP_MAX) {
586 return createSRegOperand(getTtmpClassId(Width), Val - TTMP_MIN);
594
595 int TTmpIdx = getTTmpIdx(Val);
596 if (TTmpIdx >= 0) {
597 return createSRegOperand(getTtmpClassId(Width), TTmpIdx);
587598 }
588599
589600 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX)
611622 using namespace AMDGPU;
612623
613624 switch (Val) {
614 case 102: return createRegOperand(getMCReg(FLAT_SCR_LO, STI));
615 case 103: return createRegOperand(getMCReg(FLAT_SCR_HI, STI));
625 case 102: return createRegOperand(FLAT_SCR_LO);
626 case 103: return createRegOperand(FLAT_SCR_HI);
616627 // ToDo: no support for xnack_mask_lo/_hi register
617628 case 104:
618629 case 105: break;
619630 case 106: return createRegOperand(VCC_LO);
620631 case 107: return createRegOperand(VCC_HI);
621 case 108: return createRegOperand(TBA_LO);
622 case 109: return createRegOperand(TBA_HI);
623 case 110: return createRegOperand(TMA_LO);
624 case 111: return createRegOperand(TMA_HI);
632 case 108: assert(!isGFX9()); return createRegOperand(TBA_LO);
633 case 109: assert(!isGFX9()); return createRegOperand(TBA_HI);
634 case 110: assert(!isGFX9()); return createRegOperand(TMA_LO);
635 case 111: assert(!isGFX9()); return createRegOperand(TMA_HI);
625636 case 124: return createRegOperand(M0);
626637 case 126: return createRegOperand(EXEC_LO);
627638 case 127: return createRegOperand(EXEC_HI);
644655 using namespace AMDGPU;
645656
646657 switch (Val) {
647 case 102: return createRegOperand(getMCReg(FLAT_SCR, STI));
658 case 102: return createRegOperand(FLAT_SCR);
648659 case 106: return createRegOperand(VCC);
649 case 108: return createRegOperand(TBA);
650 case 110: return createRegOperand(TMA);
660 case 108: assert(!isGFX9()); return createRegOperand(TBA);
661 case 110: assert(!isGFX9()); return createRegOperand(TMA);
651662 case 126: return createRegOperand(EXEC);
652663 default: break;
653664 }
671682 return createSRegOperand(getSgprClassId(Width),
672683 Val - SDWA9EncValues::SRC_SGPR_MIN);
673684 }
685 if (SDWA9EncValues::SRC_TTMP_MIN <= Val &&
686 Val <= SDWA9EncValues::SRC_TTMP_MAX) {
687 return createSRegOperand(getTtmpClassId(Width),
688 Val - SDWA9EncValues::SRC_TTMP_MIN);
689 }
674690
675691 return decodeSpecialReg32(Val - SDWA9EncValues::SRC_SGPR_MIN);
676692 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) {
694710 "SDWAVopcDst should be present only on GFX9");
695711 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) {
696712 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK;
697 if (Val > AMDGPU::EncValues::SGPR_MAX) {
713
714 int TTmpIdx = getTTmpIdx(Val);
715 if (TTmpIdx >= 0) {
716 return createSRegOperand(getTtmpClassId(OPW64), TTmpIdx);
717 } else if (Val > AMDGPU::EncValues::SGPR_MAX) {
698718 return decodeSpecialReg64(Val);
699719 } else {
700720 return createSRegOperand(getSgprClassId(OPW64), Val);
702722 } else {
703723 return createRegOperand(AMDGPU::VCC);
704724 }
725 }
726
727 bool AMDGPUDisassembler::isVI() const {
728 return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
729 }
730
731 bool AMDGPUDisassembler::isGFX9() const {
732 return STI.getFeatureBits()[AMDGPU::FeatureGFX9];
705733 }
706734
707735 //===----------------------------------------------------------------------===//
110110 MCOperand decodeSDWASrc16(unsigned Val) const;
111111 MCOperand decodeSDWASrc32(unsigned Val) const;
112112 MCOperand decodeSDWAVopcDst(unsigned Val) const;
113 };
113
114 int getTTmpIdx(unsigned Val) const;
115
116 bool isVI() const;
117 bool isGFX9() const;
118 };
114119
115120 //===----------------------------------------------------------------------===//
116121 // AMDGPUSymbolizer
343343 } else if (MRI.getRegClass(AMDGPU::SReg_512RegClassID).contains(RegNo)) {
344344 O << 's';
345345 NumRegs = 16;
346 } else if (MRI.getRegClass(AMDGPU::TTMP_64RegClassID).contains(RegNo)) {
347 O << "ttmp";
348 NumRegs = 2;
349 // Trap temps start at offset 112. TODO: Get this from tablegen.
350 RegIdx -= 112;
351 } else if (MRI.getRegClass(AMDGPU::TTMP_128RegClassID).contains(RegNo)) {
352 O << "ttmp";
353 NumRegs = 4;
354 // Trap temps start at offset 112. TODO: Get this from tablegen.
355 RegIdx -= 112;
356346 } else {
357347 O << getRegisterName(RegNo);
358348 return;
193193 enum {
194194 SGPR_MIN = 0,
195195 SGPR_MAX = 101,
196 TTMP_MIN = 112,
197 TTMP_MAX = 123,
196 TTMP_VI_MIN = 112,
197 TTMP_VI_MAX = 123,
198 TTMP_GFX9_MIN = 108,
199 TTMP_GFX9_MAX = 123,
198200 INLINE_INTEGER_C_MIN = 128,
199201 INLINE_INTEGER_C_POSITIVE_MAX = 192, // 64
200202 INLINE_INTEGER_C_MAX = 208,
367369 SRC_VGPR_MAX = 255,
368370 SRC_SGPR_MIN = 256,
369371 SRC_SGPR_MAX = 357,
372 SRC_TTMP_MIN = 364,
373 SRC_TTMP_MAX = 379,
370374 };
371375
372376 } // namespace SDWA
171171 reserveRegisterTuples(Reserved, AMDGPU::TTMP6_TTMP7);
172172 reserveRegisterTuples(Reserved, AMDGPU::TTMP8_TTMP9);
173173 reserveRegisterTuples(Reserved, AMDGPU::TTMP10_TTMP11);
174 reserveRegisterTuples(Reserved, AMDGPU::TTMP12_TTMP13);
175 reserveRegisterTuples(Reserved, AMDGPU::TTMP14_TTMP15);
174176
175177 const SISubtarget &ST = MF.getSubtarget();
176178
7676 let HWEncoding = 110;
7777 }
7878
79 def TTMP0 : SIReg <"ttmp0", 112>;
80 def TTMP1 : SIReg <"ttmp1", 113>;
81 def TTMP2 : SIReg <"ttmp2", 114>;
82 def TTMP3 : SIReg <"ttmp3", 115>;
83 def TTMP4 : SIReg <"ttmp4", 116>;
84 def TTMP5 : SIReg <"ttmp5", 117>;
85 def TTMP6 : SIReg <"ttmp6", 118>;
86 def TTMP7 : SIReg <"ttmp7", 119>;
87 def TTMP8 : SIReg <"ttmp8", 120>;
88 def TTMP9 : SIReg <"ttmp9", 121>;
89 def TTMP10 : SIReg <"ttmp10", 122>;
90 def TTMP11 : SIReg <"ttmp11", 123>;
79 foreach Index = 0-15 in {
80 def TTMP#Index#_vi : SIReg<"ttmp"#Index, !add(112, Index)>;
81 def TTMP#Index#_gfx9 : SIReg<"ttmp"#Index, !add(108, Index)>;
82 def TTMP#Index : SIReg<"", 0>;
83 }
9184
9285 multiclass FLAT_SCR_LOHI_m ci_e, bits<16> vi_e> {
9386 def _ci : SIReg;
191184
192185 // Trap handler TMP 32-bit registers
193186 def TTMP_32 : RegisterClass<"AMDGPU", [i32, f32, v2i16, v2f16], 32,
194 (add (sequence "TTMP%u", 0, 11))> {
187 (add (sequence "TTMP%u", 0, 15))> {
195188 let isAllocatable = 0;
196189 }
197190
206199 (add (decimate (shl TTMP_32, 1), 4)),
207200 (add (decimate (shl TTMP_32, 2), 4)),
208201 (add (decimate (shl TTMP_32, 3), 4))]>;
202
203 class TmpRegTuples
204 bit Is64Bit,
205 int Index0,
206 int Index1 = !add(Index0, 1),
207 int Index2 = !add(Index0, !if(Is64Bit, 1, 2)),
208 int Index3 = !add(Index0, !if(Is64Bit, 1, 3)),
209 string name = "ttmp["#Index0#":"#Index3#"]",
210 Register r0 = !cast("TTMP"#Index0#tgt),
211 Register r1 = !cast("TTMP"#Index1#tgt),
212 Register r2 = !cast("TTMP"#Index2#tgt),
213 Register r3 = !cast("TTMP"#Index3#tgt)> :
214 RegisterWithSubRegs {
215 let SubRegIndices = !if(Is64Bit, [sub0, sub1], [sub0, sub1, sub2, sub3]);
216 let HWEncoding = r0.HWEncoding;
217 }
218
219 foreach Index = {0, 2, 4, 6, 8, 10, 12, 14} in {
220 def TTMP#Index#_TTMP#!add(Index,1)#_vi : TmpRegTuples<"_vi", 1, Index>;
221 def TTMP#Index#_TTMP#!add(Index,1)#_gfx9 : TmpRegTuples<"_gfx9", 1, Index>;
222 }
223
224 foreach Index = {0, 4, 8, 12} in {
225 def TTMP#Index#_TTMP#!add(Index,1)#
226 _TTMP#!add(Index,2)#
227 _TTMP#!add(Index,3)#_vi : TmpRegTuples<"_vi", 0, Index>;
228 def TTMP#Index#_TTMP#!add(Index,1)#
229 _TTMP#!add(Index,2)#
230 _TTMP#!add(Index,3)#_gfx9 : TmpRegTuples<"_gfx9", 0, Index>;
231 }
209232
210233 // VGPR 32-bit registers
211234 // i16/f16 only on VI+
568568 return false;
569569 }
570570
571 #define MAP_REG2REG \
572 using namespace AMDGPU; \
573 switch(Reg) { \
574 default: return Reg; \
575 CASE_CI_VI(FLAT_SCR) \
576 CASE_CI_VI(FLAT_SCR_LO) \
577 CASE_CI_VI(FLAT_SCR_HI) \
578 CASE_VI_GFX9(TTMP0) \
579 CASE_VI_GFX9(TTMP1) \
580 CASE_VI_GFX9(TTMP2) \
581 CASE_VI_GFX9(TTMP3) \
582 CASE_VI_GFX9(TTMP4) \
583 CASE_VI_GFX9(TTMP5) \
584 CASE_VI_GFX9(TTMP6) \
585 CASE_VI_GFX9(TTMP7) \
586 CASE_VI_GFX9(TTMP8) \
587 CASE_VI_GFX9(TTMP9) \
588 CASE_VI_GFX9(TTMP10) \
589 CASE_VI_GFX9(TTMP11) \
590 CASE_VI_GFX9(TTMP12) \
591 CASE_VI_GFX9(TTMP13) \
592 CASE_VI_GFX9(TTMP14) \
593 CASE_VI_GFX9(TTMP15) \
594 CASE_VI_GFX9(TTMP0_TTMP1) \
595 CASE_VI_GFX9(TTMP2_TTMP3) \
596 CASE_VI_GFX9(TTMP4_TTMP5) \
597 CASE_VI_GFX9(TTMP6_TTMP7) \
598 CASE_VI_GFX9(TTMP8_TTMP9) \
599 CASE_VI_GFX9(TTMP10_TTMP11) \
600 CASE_VI_GFX9(TTMP12_TTMP13) \
601 CASE_VI_GFX9(TTMP14_TTMP15) \
602 CASE_VI_GFX9(TTMP0_TTMP1_TTMP2_TTMP3) \
603 CASE_VI_GFX9(TTMP4_TTMP5_TTMP6_TTMP7) \
604 CASE_VI_GFX9(TTMP8_TTMP9_TTMP10_TTMP11) \
605 CASE_VI_GFX9(TTMP12_TTMP13_TTMP14_TTMP15) \
606 }
607
608 #define CASE_CI_VI(node) \
609 assert(!isSI(STI)); \
610 case node: return isCI(STI) ? node##_ci : node##_vi;
611
612 #define CASE_VI_GFX9(node) \
613 case node: return isGFX9(STI) ? node##_gfx9 : node##_vi;
614
571615 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI) {
572
573 switch(Reg) {
574 default: break;
575 case AMDGPU::FLAT_SCR:
576 assert(!isSI(STI));
577 return isCI(STI) ? AMDGPU::FLAT_SCR_ci : AMDGPU::FLAT_SCR_vi;
578
579 case AMDGPU::FLAT_SCR_LO:
580 assert(!isSI(STI));
581 return isCI(STI) ? AMDGPU::FLAT_SCR_LO_ci : AMDGPU::FLAT_SCR_LO_vi;
582
583 case AMDGPU::FLAT_SCR_HI:
584 assert(!isSI(STI));
585 return isCI(STI) ? AMDGPU::FLAT_SCR_HI_ci : AMDGPU::FLAT_SCR_HI_vi;
586 }
587 return Reg;
588 }
616 MAP_REG2REG
617 }
618
619 #undef CASE_CI_VI
620 #undef CASE_VI_GFX9
621
622 #define CASE_CI_VI(node) case node##_ci: case node##_vi: return node;
623 #define CASE_VI_GFX9(node) case node##_vi: case node##_gfx9: return node;
589624
590625 unsigned mc2PseudoReg(unsigned Reg) {
591 switch (Reg) {
592 case AMDGPU::FLAT_SCR_ci:
593 case AMDGPU::FLAT_SCR_vi:
594 return FLAT_SCR;
595
596 case AMDGPU::FLAT_SCR_LO_ci:
597 case AMDGPU::FLAT_SCR_LO_vi:
598 return AMDGPU::FLAT_SCR_LO;
599
600 case AMDGPU::FLAT_SCR_HI_ci:
601 case AMDGPU::FLAT_SCR_HI_vi:
602 return AMDGPU::FLAT_SCR_HI;
603
604 default:
605 return Reg;
606 }
607 }
626 MAP_REG2REG
627 }
628
629 #undef CASE_CI_VI
630 #undef CASE_VI_GFX9
631 #undef MAP_REG2REG
608632
609633 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo) {
610634 assert(OpNo < Desc.NumOperands);
None // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx901 -show-encoding %s 2>&1 | FileCheck -check-prefix=GFX9 %s
0 // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s 2>&1 | FileCheck -check-prefix=GFX9 %s
11
22 v_pk_add_f16 v1, -17, v2
33 // GFX9: :19: error: invalid operand for instruction
None // RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s --check-prefix=SICI
1 // RUN: llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck %s --check-prefix=SICI
2 // RUN: llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s | FileCheck %s --check-prefix=VI
0 // RUN: not llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s --check-prefix=SICI
1 // RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck %s --check-prefix=SICI
2 // RUN: not llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s | FileCheck %s --check-prefix=VI
3 // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck %s --check-prefix=GFX9
4
5 // RUN: not llvm-mc -arch=amdgcn -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSICIVI
6 // RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSICIVI
7 // RUN: not llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSICIVI
8 // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOGFX9
39
410 //===----------------------------------------------------------------------===//
511 // Trap Handler related - 32 bit registers
814 s_add_u32 ttmp0, ttmp0, 4
915 // SICI: s_add_u32 ttmp0, ttmp0, 4 ; encoding: [0x70,0x84,0x70,0x80]
1016 // VI: s_add_u32 ttmp0, ttmp0, 4 ; encoding: [0x70,0x84,0x70,0x80]
17 // GFX9: s_add_u32 ttmp0, ttmp0, 4 ; encoding: [0x6c,0x84,0x6c,0x80]
1118
1219 s_add_u32 ttmp4, 8, ttmp4
1320 // SICI: s_add_u32 ttmp4, 8, ttmp4 ; encoding: [0x88,0x74,0x74,0x80]
1421 // VI: s_add_u32 ttmp4, 8, ttmp4 ; encoding: [0x88,0x74,0x74,0x80]
22 // GXF9: s_add_u32 ttmp4, 8, ttmp4 ; encoding: [0x88,0x70,0x70,0x80]
1523
1624 s_add_u32 ttmp4, ttmp4, 0x00000100
1725 // SICI: s_add_u32 ttmp4, ttmp4, 0x100 ; encoding: [0x74,0xff,0x74,0x80,0x00,0x01,0x00,0x00]
1826 // VI: s_add_u32 ttmp4, ttmp4, 0x100 ; encoding: [0x74,0xff,0x74,0x80,0x00,0x01,0x00,0x00]
27 // GXF9: s_add_u32 ttmp4, ttmp4, 0x100 ; encoding: [0x70,0xff,0x70,0x80,0x00,0x01,0x00,0x00]
1928
2029 s_add_u32 ttmp4, ttmp4, 4
2130 // SICI: s_add_u32 ttmp4, ttmp4, 4 ; encoding: [0x74,0x84,0x74,0x80]
2231 // VI: s_add_u32 ttmp4, ttmp4, 4 ; encoding: [0x74,0x84,0x74,0x80]
32 // GXF9: s_add_u32 ttmp4, ttmp4, 4 ; encoding: [0x70,0x84,0x70,0x80]
2333
2434 s_add_u32 ttmp4, ttmp8, ttmp4
2535 // SICI: s_add_u32 ttmp4, ttmp8, ttmp4 ; encoding: [0x78,0x74,0x74,0x80]
2636 // VI: s_add_u32 ttmp4, ttmp8, ttmp4 ; encoding: [0x78,0x74,0x74,0x80]
37 // GXF9: s_add_u32 ttmp4, ttmp8, ttmp4 ; encoding: [0x74,0x70,0x70,0x80]
2738
2839 s_and_b32 ttmp10, ttmp8, 0x00000080
2940 // SICI: s_and_b32 ttmp10, ttmp8, 0x80 ; encoding: [0x78,0xff,0x7a,0x87,0x80,0x00,0x00,0x00]
3041 // VI: s_and_b32 ttmp10, ttmp8, 0x80 ; encoding: [0x78,0xff,0x7a,0x86,0x80,0x00,0x00,0x00]
42 // GXF9: s_and_b32 ttmp10, ttmp8, 0x80 ; encoding: [0x74,0xff,0x74,0x86,0x80,0x00,0x00,0x00]
3143
3244 s_and_b32 ttmp9, tma_hi, 0x0000ffff
3345 // SICI: s_and_b32 ttmp9, tma_hi, 0xffff ; encoding: [0x6f,0xff,0x79,0x87,0xff,0xff,0x00,0x00]
3446 // VI: s_and_b32 ttmp9, tma_hi, 0xffff ; encoding: [0x6f,0xff,0x79,0x86,0xff,0xff,0x00,0x00]
47 // NOGFX9: error: not a valid operand
3548
3649 s_and_b32 ttmp9, ttmp9, 0x000001ff
3750 // SICI: s_and_b32 ttmp9, ttmp9, 0x1ff ; encoding: [0x79,0xff,0x79,0x87,0xff,0x01,0x00,0x00]
3851 // VI: s_and_b32 ttmp9, ttmp9, 0x1ff ; encoding: [0x79,0xff,0x79,0x86,0xff,0x01,0x00,0x00]
52 // GXF9: s_and_b32 ttmp9, ttmp9, 0x1ff ; encoding: [0x75,0xff,0x75,0x86,0xff,0x01,0x00,0x00]
3953
4054 s_and_b32 ttmp9, tma_lo, 0xffff0000
4155 // SICI: s_and_b32 ttmp9, tma_lo, 0xffff0000 ; encoding: [0x6e,0xff,0x79,0x87,0x00,0x00,0xff,0xff]
4256 // VI: s_and_b32 ttmp9, tma_lo, 0xffff0000 ; encoding: [0x6e,0xff,0x79,0x86,0x00,0x00,0xff,0xff]
57 // NOGFX9: error: not a valid operand
4358
4459 s_and_b32 ttmp9, ttmp9, ttmp8
4560 // SICI: s_and_b32 ttmp9, ttmp9, ttmp8 ; encoding: [0x79,0x78,0x79,0x87]
4661 // VI: s_and_b32 ttmp9, ttmp9, ttmp8 ; encoding: [0x79,0x78,0x79,0x86]
62 // GXF9: s_and_b32 ttmp9, ttmp9, ttmp8 ; encoding: [0x75,0x78,0x75,0x86]
4763
4864 s_and_b32 ttmp8, ttmp1, 0x01000000
4965 // SICI: s_and_b32 ttmp8, ttmp1, 0x1000000 ; encoding: [0x71,0xff,0x78,0x87,0x00,0x00,0x00,0x01]
5066 // VI: s_and_b32 ttmp8, ttmp1, 0x1000000 ; encoding: [0x71,0xff,0x78,0x86,0x00,0x00,0x00,0x01]
67 // GXF9: s_and_b32 ttmp8, ttmp1, 0x1000000 ; encoding: [0x6d,0xff,0x74,0x86,0x00,0x00,0x00,0x01]
5168
5269 s_cmp_eq_i32 ttmp8, 0
5370 // SICI: s_cmp_eq_i32 ttmp8, 0 ; encoding: [0x78,0x80,0x00,0xbf]
5471 // VI: s_cmp_eq_i32 ttmp8, 0 ; encoding: [0x78,0x80,0x00,0xbf]
72 // GXF9: s_cmp_eq_i32 ttmp8, 0 ; encoding: [0x74,0x80,0x00,0xbf]
5573
5674 s_cmp_eq_i32 ttmp8, 0x000000fe
5775 // SICI: s_cmp_eq_i32 ttmp8, 0xfe ; encoding: [0x78,0xff,0x00,0xbf,0xfe,0x00,0x00,0x00]
5876 // VI: s_cmp_eq_i32 ttmp8, 0xfe ; encoding: [0x78,0xff,0x00,0xbf,0xfe,0x00,0x00,0x00]
77 // GXF9: s_cmp_eq_i32 ttmp8, 0xfe ; encoding: [0x74,0xff,0x00,0xbf,0xfe,0x00,0x00,0x00]
5978
6079 s_lshr_b32 ttmp8, ttmp8, 12
6180 // SICI: s_lshr_b32 ttmp8, ttmp8, 12 ; encoding: [0x78,0x8c,0x78,0x90]
6281 // VI: s_lshr_b32 ttmp8, ttmp8, 12 ; encoding: [0x78,0x8c,0x78,0x8f]
82 // GXF9: s_lshr_b32 ttmp8, ttmp8, 12 ; encoding: [0x74,0x8c,0x74,0x8f]
6383
6484 v_mov_b32_e32 v1, ttmp8
6585 // SICI: v_mov_b32_e32 v1, ttmp8 ; encoding: [0x78,0x02,0x02,0x7e]
6686 // VI: v_mov_b32_e32 v1, ttmp8 ; encoding: [0x78,0x02,0x02,0x7e]
87 // GXF9: v_mov_b32_e32 v1, ttmp8 ; encoding: [0x74,0x02,0x02,0x7e]
6788
6889 s_mov_b32 m0, ttmp8
6990 // SICI: s_mov_b32 m0, ttmp8 ; encoding: [0x78,0x03,0xfc,0xbe]
7091 // VI: s_mov_b32 m0, ttmp8 ; encoding: [0x78,0x00,0xfc,0xbe]
92 // GXF9: s_mov_b32 m0, ttmp8 ; encoding: [0x74,0x00,0xfc,0xbe]
7193
7294 s_mov_b32 ttmp10, 0
7395 // SICI: s_mov_b32 ttmp10, 0 ; encoding: [0x80,0x03,0xfa,0xbe]
7496 // VI: s_mov_b32 ttmp10, 0 ; encoding: [0x80,0x00,0xfa,0xbe]
97 // GXF9: s_mov_b32 ttmp10, 0 ; encoding: [0x80,0x00,0xf6,0xbe]
7598
7699 s_mov_b32 ttmp11, 0x01024fac
77100 // SICI: s_mov_b32 ttmp11, 0x1024fac ; encoding: [0xff,0x03,0xfb,0xbe,0xac,0x4f,0x02,0x01]
78101 // VI: s_mov_b32 ttmp11, 0x1024fac ; encoding: [0xff,0x00,0xfb,0xbe,0xac,0x4f,0x02,0x01]
102 // GXF9: s_mov_b32 ttmp11, 0x1024fac ; encoding: [0xff,0x00,0xf7,0xbe,0xac,0x4f,0x02,0x01]
79103
80104 s_mov_b32 ttmp8, m0
81105 // SICI: s_mov_b32 ttmp8, m0 ; encoding: [0x7c,0x03,0xf8,0xbe]
82106 // VI: s_mov_b32 ttmp8, m0 ; encoding: [0x7c,0x00,0xf8,0xbe]
107 // GXF9: s_mov_b32 ttmp8, m0 ; encoding: [0x7c,0x00,0xf4,0xbe]
83108
84109 s_mov_b32 ttmp8, tma_lo
85110 // SICI: s_mov_b32 ttmp8, tma_lo ; encoding: [0x6e,0x03,0xf8,0xbe]
86111 // VI: s_mov_b32 ttmp8, tma_lo ; encoding: [0x6e,0x00,0xf8,0xbe]
112 // NOGFX9: error: not a valid operand
87113
88114 s_mul_i32 ttmp8, 0x00000324, ttmp8
89115 // SICI: s_mul_i32 ttmp8, 0x324, ttmp8 ; encoding: [0xff,0x78,0x78,0x93,0x24,0x03,0x00,0x00]
90116 // VI: s_mul_i32 ttmp8, 0x324, ttmp8 ; encoding: [0xff,0x78,0x78,0x92,0x24,0x03,0x00,0x00]
117 // GXF9: s_mul_i32 ttmp8, 0x324, ttmp8 ; encoding: [0xff,0x74,0x74,0x92,0x24,0x03,0x00,0x00]
91118
92119 s_or_b32 ttmp9, ttmp9, 0x00280000
93120 // SICI: s_or_b32 ttmp9, ttmp9, 0x280000 ; encoding: [0x79,0xff,0x79,0x88,0x00,0x00,0x28,0x00]
94121 // VI: s_or_b32 ttmp9, ttmp9, 0x280000 ; encoding: [0x79,0xff,0x79,0x87,0x00,0x00,0x28,0x00]
122 // GXF9: s_or_b32 ttmp9, ttmp9, 0x280000 ; encoding: [0x75,0xff,0x75,0x87,0x00,0x00,0x28,0x00]
123
124 // ttmp12..ttmp15 (GFX9 only)
125
126 s_add_u32 ttmp0, ttmp12, 4
127 // NOSICIVI: error: not a valid operand
128 // GFX9: s_add_u32 ttmp0, ttmp12, 4 ; encoding: [0x78,0x84,0x6c,0x80]
129
130 s_add_u32 ttmp0, ttmp13, 4
131 // NOSICIVI: error: not a valid operand
132 // GFX9: s_add_u32 ttmp0, ttmp13, 4 ; encoding: [0x79,0x84,0x6c,0x80]
133
134 s_add_u32 ttmp0, ttmp14, 4
135 // NOSICIVI: error: not a valid operand
136 // GFX9: s_add_u32 ttmp0, ttmp14, 4 ; encoding: [0x7a,0x84,0x6c,0x80]
137
138 s_add_u32 ttmp0, ttmp15, 4
139 // NOSICIVI: error: not a valid operand
140 // GFX9: s_add_u32 ttmp0, ttmp15, 4 ; encoding: [0x7b,0x84,0x6c,0x80]
95141
96142 //===----------------------------------------------------------------------===//
97143 // Trap Handler related - Pairs and quadruples of registers
100146 s_mov_b64 ttmp[4:5], exec
101147 // SICI: s_mov_b64 ttmp[4:5], exec ; encoding: [0x7e,0x04,0xf4,0xbe]
102148 // VI: s_mov_b64 ttmp[4:5], exec ; encoding: [0x7e,0x01,0xf4,0xbe]
149 // GFX9: s_mov_b64 ttmp[4:5], exec ; encoding: [0x7e,0x01,0xf0,0xbe]
103150
104151 s_mov_b64 [ttmp4,ttmp5], exec
105152 // SICI: s_mov_b64 ttmp[4:5], exec ; encoding: [0x7e,0x04,0xf4,0xbe]
106153 // VI: s_mov_b64 ttmp[4:5], exec ; encoding: [0x7e,0x01,0xf4,0xbe]
154 // GFX9: s_mov_b64 ttmp[4:5], exec ; encoding: [0x7e,0x01,0xf0,0xbe]
107155
108156 s_mov_b64 exec, [ttmp4,ttmp5]
109157 // SICI: s_mov_b64 exec, ttmp[4:5] ; encoding: [0x74,0x04,0xfe,0xbe]
110158 // VI: s_mov_b64 exec, ttmp[4:5] ; encoding: [0x74,0x01,0xfe,0xbe]
159 // GFX9: s_mov_b64 exec, ttmp[4:5] ; encoding: [0x70,0x01,0xfe,0xbe]
111160
112161 s_mov_b64 tba, ttmp[4:5]
113162 // SICI: s_mov_b64 tba, ttmp[4:5] ; encoding: [0x74,0x04,0xec,0xbe]
114163 // VI: s_mov_b64 tba, ttmp[4:5] ; encoding: [0x74,0x01,0xec,0xbe]
164 // NOGFX9: error: not a valid operand
115165
116166 s_mov_b64 ttmp[4:5], tba
117167 // SICI: s_mov_b64 ttmp[4:5], tba ; encoding: [0x6c,0x04,0xf4,0xbe]
118168 // VI: s_mov_b64 ttmp[4:5], tba ; encoding: [0x6c,0x01,0xf4,0xbe]
169 // NOGFX9: error: not a valid operand
119170
120171 s_mov_b64 tma, ttmp[4:5]
121172 // SICI: s_mov_b64 tma, ttmp[4:5] ; encoding: [0x74,0x04,0xee,0xbe]
122173 // VI: s_mov_b64 tma, ttmp[4:5] ; encoding: [0x74,0x01,0xee,0xbe]
174 // NOGFX9: error: not a valid operand
123175
124176 s_mov_b64 ttmp[4:5], tma
125177 // SICI: s_mov_b64 ttmp[4:5], tma ; encoding: [0x6e,0x04,0xf4,0xbe]
126178 // VI: s_mov_b64 ttmp[4:5], tma ; encoding: [0x6e,0x01,0xf4,0xbe]
127
179 // NOGFX9: error: not a valid operand
180
181 // ttmp12..ttmp15 (GFX9 only)
182
183 s_mov_b64 ttmp[12:13], exec
184 // NOSICIVI: error: not a valid operand
185 // GFX9: s_mov_b64 ttmp[12:13], exec ; encoding: [0x7e,0x01,0xf8,0xbe]
186
187 s_mov_b64 ttmp[14:15], exec
188 // NOSICIVI: error: not a valid operand
189 // GFX9: s_mov_b64 ttmp[14:15], exec ; encoding: [0x7e,0x01,0xfa,0xbe]
128190
129191 //===----------------------------------------------------------------------===//
130192 // Trap Handler related - Some specific instructions
133195 s_setpc_b64 [ttmp2,ttmp3]
134196 // SICI: s_setpc_b64 ttmp[2:3] ; encoding: [0x72,0x20,0x80,0xbe]
135197 // VI: s_setpc_b64 ttmp[2:3] ; encoding: [0x72,0x1d,0x80,0xbe]
198 // GFX9: s_setpc_b64 ttmp[2:3] ; encoding: [0x6e,0x1d,0x80,0xbe]
136199
137200 v_readfirstlane_b32 ttmp8, v1
138201 // SICI: v_readfirstlane_b32 ttmp8, v1 ; encoding: [0x01,0x05,0xf0,0x7e]
139202 // VI: v_readfirstlane_b32 ttmp8, v1 ; encoding: [0x01,0x05,0xf0,0x7e]
140
141 buffer_atomic_inc v1, off, ttmp[8:11], 56 glc
142 // SICI: buffer_atomic_inc v1, off, ttmp[8:11], 56 glc ; encoding: [0x00,0x40,0xf0,0xe0,0x00,0x01,0x1e,0xb8]
143 // VI: buffer_atomic_inc v1, off, ttmp[8:11], 56 glc ; encoding: [0x00,0x40,0x2c,0xe1,0x00,0x01,0x1e,0xb8]
203 // GFX9: v_readfirstlane_b32 ttmp8, v1 ; encoding: [0x01,0x05,0xe8,0x7e]
204
205 buffer_atomic_inc v1, off, ttmp[8:11], 56 glc
206 // SICI: buffer_atomic_inc v1, off, ttmp[8:11], 56 glc ; encoding: [0x00,0x40,0xf0,0xe0,0x00,0x01,0x1e,0xb8]
207 // VI: buffer_atomic_inc v1, off, ttmp[8:11], 56 glc ; encoding: [0x00,0x40,0x2c,0xe1,0x00,0x01,0x1e,0xb8]
208 // GFX9: buffer_atomic_inc v1, off, ttmp[8:11], 56 glc ; encoding: [0x00,0x40,0x2c,0xe1,0x00,0x01,0x1d,0xb8]
209
210 // ttmp12..ttmp15 (GFX9 only)
211
212 buffer_atomic_inc v1, off, ttmp[12:15], 56 glc
213 // NOSICIVI: error: not a valid operand
214 // GFX9: buffer_atomic_inc v1, off, ttmp[12:15], 56 glc ; encoding: [0x00,0x40,0x2c,0xe1,0x00,0x01,0x1e,0xb8]
None // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx901 -show-encoding %s 2>&1 | FileCheck -check-prefix=GCN %s
0 // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s 2>&1 | FileCheck -check-prefix=GCN %s
11 // RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s 2>&1 | FileCheck -check-prefix=GCN %s
22 // RUN: not llvm-mc -arch=amdgcn -mcpu=hawaii -show-encoding %s 2>&1 | FileCheck -check-prefix=GCN %s
33
693693
694694 // NOSICI: error:
695695 // NOVI: error:
696 // GFX9: v_mov_b32_sdwa v1, ttmp12 dst_sel:BYTE_0 dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x02,0x02,0x7e,0x78,0x10,0x86,0x06]
697 v_mov_b32_sdwa v1, ttmp12 dst_sel:BYTE_0 dst_unused:UNUSED_PRESERVE src0_sel:DWORD
698
699 // NOSICI: error:
700 // NOVI: error:
696701 // GFX9: v_add_f32_sdwa v0, s0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x00,0x00,0x02,0x00,0x06,0x85,0x02]
697702 v_add_f32 v0, s0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
698703
708713
709714 // NOSICI: error:
710715 // NOVI: error:
716 // NO: error: not a valid operand
717 v_add_f32 v0, v1, tba_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
718
719 // NOSICI: error:
720 // NOVI: error:
721 // NO: error: not a valid operand
722 v_add_f32 v0, v1, tma_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
723
724 // NOSICI: error:
725 // NOVI: error:
711726 // GFX9: v_cmp_eq_f32_sdwa vcc, s1, v2 src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x04,0x84,0x7c,0x01,0x00,0x85,0x02]
712727 v_cmp_eq_f32_sdwa vcc, s1, v2 src0_sel:WORD_1 src1_sel:BYTE_2
713728
718733
719734 // NOSICI: error:
720735 // NOVI: error:
736 // GFX9: v_cmp_eq_f32_sdwa ttmp[12:13], v1, v2 src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x04,0x84,0x7c,0x01,0xf8,0x05,0x02]
737 v_cmp_eq_f32_sdwa ttmp[12:13], v1, v2 src0_sel:WORD_1 src1_sel:BYTE_2
738
739 // NOSICI: error:
740 // NOVI: error:
741 // NO: error: not a valid operand
742 v_cmp_eq_f32_sdwa tba, v1, v2 src0_sel:WORD_1 src1_sel:BYTE_2
743
744 // NOSICI: error:
745 // NOVI: error:
746 // NO: error: not a valid operand
747 v_cmp_eq_f32_sdwa tma, v1, v2 src0_sel:WORD_1 src1_sel:BYTE_2
748
749 // NOSICI: error:
750 // NOVI: error:
751 // GFX9: v_cmp_eq_f32_sdwa vcc, v1, ttmp15 src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0xf6,0x84,0x7c,0x01,0x00,0x05,0x82]
752 v_cmp_eq_f32_sdwa vcc, v1, ttmp15 src0_sel:WORD_1 src1_sel:BYTE_2
753
754 // NOSICI: error:
755 // NOVI: error:
721756 // NOGFX9: error: invalid operand (violates constant bus restrictions)
722757 v_cmp_eq_f32_sdwa vcc, exec, vcc src0_sel:WORD_1 src1_sel:BYTE_2
723758
449449 # GFX9: v_mov_b32_sdwa v1, s2 dst_sel:BYTE_0 dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x02,0x02,0x7e,0x02,0x10,0x86,0x06]
450450 0xf9 0x02 0x02 0x7e 0x02 0x10 0x86 0x06
451451
452 # GFX9: v_mov_b32_sdwa v1, ttmp12 dst_sel:BYTE_0 dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x02,0x02,0x7e,0x78,0x10,0x86,0x06]
453 0xf9,0x02,0x02,0x7e,0x78,0x10,0x86,0x06
454
452455 # GFX9: v_mov_b32_sdwa v1, exec_lo dst_sel:BYTE_0 dst_unused:UNUSED_PRESERVE src0_sel:DWORD ; encoding: [0xf9,0x02,0x02,0x7e,0x7e,0x10,0x86,0x06]
453456 0xf9 0x02 0x02 0x7e 0x7e 0x10 0x86 0x06
454457
463466
464467 # GFX9: v_cmp_eq_f32_sdwa vcc, v1, s22 src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x2c,0x84,0x7c,0x01,0x00,0x05,0x82]
465468 0xf9 0x2c 0x84 0x7c 0x01 0x00 0x05 0x82
469
470 # GFX9: v_cmp_eq_f32_sdwa vcc, v1, ttmp15 src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0xf6,0x84,0x7c,0x01,0x00,0x05,0x82]
471 0xf9,0xf6,0x84,0x7c,0x01,0x00,0x05,0x82
466472
467473 #===------------------------------------------------------------------------===#
468474 # VOPC with arbitrary SGPR destination
471477 # GFX9: v_cmp_eq_f32_sdwa s[2:3], v1, v2 src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x04,0x84,0x7c,0x01,0x82,0x05,0x02]
472478 0xf9 0x04 0x84 0x7c 0x01 0x82 0x05 0x02
473479
480 # GFX9: v_cmp_eq_f32_sdwa ttmp[12:13], v1, v2 src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x04,0x84,0x7c,0x01,0xf8,0x05,0x02]
481 0xf9,0x04,0x84,0x7c,0x01,0xf8,0x05,0x02
482
474483 # GFX9: v_cmp_eq_f32_sdwa exec, v1, v2 src0_sel:WORD_1 src1_sel:BYTE_2 ; encoding: [0xf9,0x04,0x84,0x7c,0x01,0xfe,0x05,0x02]
475484 0xf9 0x04 0x84 0x7c 0x01 0xfe 0x05 0x02
476485
0 # RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck %s -check-prefix=GFX9
1
2 #===----------------------------------------------------------------------===#
3 # Trap Handler related - 32 bit registers
4 #===----------------------------------------------------------------------===#
5
6 # GFX9: s_add_u32 ttmp0, ttmp0, 4 ; encoding: [0x6c,0x84,0x6c,0x80]
7 0x6c,0x84,0x6c,0x80
8
9 # GFX9: s_add_u32 ttmp4, 8, ttmp4 ; encoding: [0x88,0x70,0x70,0x80]
10 0x88,0x70,0x70,0x80
11
12 # GFX9: s_add_u32 ttmp4, ttmp4, 0x100 ; encoding: [0x70,0xff,0x70,0x80,0x00,0x01,0x00,0x00]
13 0x70,0xff,0x70,0x80,0x00,0x01,0x00,0x00
14
15 # GFX9: s_add_u32 ttmp4, ttmp4, 4 ; encoding: [0x70,0x84,0x70,0x80]
16 0x70,0x84,0x70,0x80
17
18 # GFX9: s_add_u32 ttmp4, ttmp8, ttmp4 ; encoding: [0x74,0x70,0x70,0x80]
19 0x74,0x70,0x70,0x80
20
21 # GFX9: s_and_b32 ttmp10, ttmp8, 0x80 ; encoding: [0x74,0xff,0x76,0x86,0x80,0x00,0x00,0x00]
22 0x74,0xff,0x76,0x86,0x80,0x00,0x00,0x00
23
24 # GFX9: s_and_b32 ttmp9, ttmp9, 0x1ff ; encoding: [0x75,0xff,0x75,0x86,0xff,0x01,0x00,0x00]
25 0x75,0xff,0x75,0x86,0xff,0x01,0x00,0x00
26
27 # GFX9: s_and_b32 ttmp9, ttmp9, ttmp8 ; encoding: [0x75,0x74,0x75,0x86]
28 0x75,0x74,0x75,0x86
29
30 # GFX9: s_and_b32 ttmp8, ttmp1, 0x1000000 ; encoding: [0x6d,0xff,0x74,0x86,0x00,0x00,0x00,0x01]
31 0x6d,0xff,0x74,0x86,0x00,0x00,0x00,0x01
32
33 # GFX9: s_cmp_eq_i32 ttmp8, 0 ; encoding: [0x74,0x80,0x00,0xbf]
34 0x74,0x80,0x00,0xbf
35
36 # GFX9: s_cmp_eq_i32 ttmp8, 0xfe ; encoding: [0x74,0xff,0x00,0xbf,0xfe,0x00,0x00,0x00]
37 0x74,0xff,0x00,0xbf,0xfe,0x00,0x00,0x00
38
39 # GFX9: s_lshr_b32 ttmp8, ttmp8, 12 ; encoding: [0x74,0x8c,0x74,0x8f]
40 0x74,0x8c,0x74,0x8f
41
42 # GFX9: v_mov_b32_e32 v1, ttmp8 ; encoding: [0x74,0x02,0x02,0x7e]
43 0x74,0x02,0x02,0x7e
44
45 # GFX9: s_mov_b32 m0, ttmp8 ; encoding: [0x74,0x00,0xfc,0xbe]
46 0x74,0x00,0xfc,0xbe
47
48 # GFX9: s_mov_b32 ttmp10, 0 ; encoding: [0x80,0x00,0xf6,0xbe]
49 0x80,0x00,0xf6,0xbe
50
51 # GFX9: s_mov_b32 ttmp11, 0x1024fac ; encoding: [0xff,0x00,0xf7,0xbe,0xac,0x4f,0x02,0x01]
52 0xff,0x00,0xf7,0xbe,0xac,0x4f,0x02,0x01
53
54 # GFX9: s_mov_b32 ttmp8, m0 ; encoding: [0x7c,0x00,0xf4,0xbe]
55 0x7c,0x00,0xf4,0xbe
56
57 # GFX9: s_mul_i32 ttmp8, 0x324, ttmp8 ; encoding: [0xff,0x74,0x74,0x92,0x24,0x03,0x00,0x00]
58 0xff,0x74,0x74,0x92,0x24,0x03,0x00,0x00
59
60 # GFX9: s_or_b32 ttmp9, ttmp9, 0x280000 ; encoding: [0x75,0xff,0x75,0x87,0x00,0x00,0x28,0x00]
61 0x75,0xff,0x75,0x87,0x00,0x00,0x28,0x00
62
63 # GFX9: s_add_u32 ttmp0, ttmp12, 4 ; encoding: [0x78,0x84,0x6c,0x80]
64 0x78,0x84,0x6c,0x80
65
66 # GFX9: s_add_u32 ttmp0, ttmp13, 4 ; encoding: [0x79,0x84,0x6c,0x80]
67 0x79,0x84,0x6c,0x80
68
69 # GFX9: s_add_u32 ttmp0, ttmp14, 4 ; encoding: [0x7a,0x84,0x6c,0x80]
70 0x7a,0x84,0x6c,0x80
71
72 # GFX9: s_add_u32 ttmp0, ttmp15, 4 ; encoding: [0x7b,0x84,0x6c,0x80]
73 0x7b,0x84,0x6c,0x80
74
75 #===----------------------------------------------------------------------===#
76 # Trap Handler related - Pairs of registers
77 #===----------------------------------------------------------------------===#
78
79 # GFX9: s_mov_b64 ttmp[4:5], exec ; encoding: [0x7e,0x01,0xf0,0xbe]
80 0x7e,0x01,0xf0,0xbe
81
82 # GFX9: s_mov_b64 ttmp[4:5], exec ; encoding: [0x7e,0x01,0xf0,0xbe]
83 0x7e,0x01,0xf0,0xbe
84
85 # GFX9: s_mov_b64 exec, ttmp[4:5] ; encoding: [0x70,0x01,0xfe,0xbe]
86 0x70,0x01,0xfe,0xbe
87
88 # GFX9: s_mov_b64 ttmp[12:13], exec ; encoding: [0x7e,0x01,0xf8,0xbe]
89 0x7e,0x01,0xf8,0xbe
90
91 # GFX9: s_mov_b64 ttmp[14:15], exec ; encoding: [0x7e,0x01,0xfa,0xbe]
92 0x7e,0x01,0xfa,0xbe
93
94 #===----------------------------------------------------------------------===#
95 # Trap Handler related - Some specific instructions and quadruples of registers
96 #===----------------------------------------------------------------------===#
97
98 # GFX9: s_setpc_b64 ttmp[2:3] ; encoding: [0x6e,0x1d,0x80,0xbe]
99 0x6e,0x1d,0x80,0xbe
100
101 # GFX9: v_readfirstlane_b32 ttmp8, v1 ; encoding: [0x01,0x05,0xe8,0x7e]
102 0x01,0x05,0xe8,0x7e
103
104 # GFX9: buffer_atomic_inc v1, off, ttmp[8:11], 56 glc ; encoding: [0x00,0x40,0x2c,0xe1,0x00,0x01,0x1d,0xb8]
105 0x00,0x40,0x2c,0xe1,0x00,0x01,0x1d,0xb8
106
107 # GFX9: buffer_atomic_inc v1, off, ttmp[12:15], 56 glc ; encoding: [0x00,0x40,0x2c,0xe1,0x00,0x01,0x1e,0xb8]
108 0x00,0x40,0x2c,0xe1,0x00,0x01,0x1e,0xb8