llvm.org GIT mirror llvm / 7eb0d81
Allow PPC B and BLR to be if-converted into some predicated forms This enables us to form predicated branches (which are the same conditional branches we had before) and also a larger set of predicated returns (including instructions like bdnzlr which is a conditional return and loop-counter decrement all in one). At the moment, if conversion does not capture all possible opportunities. A simple example is provided in early-ret2.ll, where if conversion forms one predicated return, and then the PPCEarlyReturn pass picks up the other one. So, at least for now, we'll keep both mechanisms. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179134 91177308-0d34-0410-b5e6-96231b3b80d8 Hal Finkel 7 years ago
7 changed file(s) with 298 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
8282 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
8383 "bdnz $dst">;
8484 }
85 }
85
86 let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in {
87 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
88 "bdzlr", BrB, []>;
89 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
90 "bdnzlr", BrB, []>;
91 }
92 }
93
94
8695
8796 let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in {
8897 // Convenient aliases for call instructions
873873 DefMI->eraseFromParent();
874874
875875 return true;
876 }
877
878 bool PPCInstrInfo::isPredicated(const MachineInstr *MI) const {
879 unsigned OpC = MI->getOpcode();
880 switch (OpC) {
881 default:
882 return false;
883 case PPC::BCC:
884 case PPC::BCLR:
885 case PPC::BDZLR:
886 case PPC::BDZLR8:
887 case PPC::BDNZLR:
888 case PPC::BDNZLR8:
889 return true;
890 }
891 }
892
893 bool PPCInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
894 if (!MI->isTerminator())
895 return false;
896
897 // Conditional branch is a special case.
898 if (MI->isBranch() && !MI->isBarrier())
899 return true;
900
901 return !isPredicated(MI);
902 }
903
904 bool PPCInstrInfo::PredicateInstruction(
905 MachineInstr *MI,
906 const SmallVectorImpl &Pred) const {
907 unsigned OpC = MI->getOpcode();
908 if (OpC == PPC::BLR) {
909 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
910 bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
911 MI->setDesc(get(Pred[0].getImm() ?
912 (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR) :
913 (isPPC64 ? PPC::BDZLR8 : PPC::BDZLR)));
914 } else {
915 MI->setDesc(get(PPC::BCLR));
916 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
917 .addImm(Pred[0].getImm())
918 .addReg(Pred[1].getReg());
919 }
920
921 return true;
922 } else if (OpC == PPC::B) {
923 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
924 bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
925 MI->setDesc(get(Pred[0].getImm() ?
926 (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
927 (isPPC64 ? PPC::BDZ8 : PPC::BDZ)));
928 } else {
929 MachineBasicBlock *MBB = MI->getOperand(0).getMBB();
930 MI->RemoveOperand(0);
931
932 MI->setDesc(get(PPC::BCC));
933 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
934 .addImm(Pred[0].getImm())
935 .addReg(Pred[1].getReg())
936 .addMBB(MBB);
937 }
938
939 return true;
940 }
941
942 return false;
943 }
944
945 bool PPCInstrInfo::SubsumesPredicate(
946 const SmallVectorImpl &Pred1,
947 const SmallVectorImpl &Pred2) const {
948 assert(Pred1.size() == 2 && "Invalid PPC first predicate");
949 assert(Pred2.size() == 2 && "Invalid PPC second predicate");
950
951 if (Pred1[1].getReg() == PPC::CTR8 || Pred1[1].getReg() == PPC::CTR)
952 return false;
953 if (Pred2[1].getReg() == PPC::CTR8 || Pred2[1].getReg() == PPC::CTR)
954 return false;
955
956 PPC::Predicate P1 = (PPC::Predicate) Pred1[0].getImm();
957 PPC::Predicate P2 = (PPC::Predicate) Pred2[0].getImm();
958
959 if (P1 == P2)
960 return true;
961
962 // Does P1 subsume P2, e.g. GE subsumes GT.
963 if (P1 == PPC::PRED_LE &&
964 (P2 == PPC::PRED_LT || P2 == PPC::PRED_EQ))
965 return true;
966 if (P1 == PPC::PRED_GE &&
967 (P2 == PPC::PRED_GT || P2 == PPC::PRED_EQ))
968 return true;
969
970 return false;
971 }
972
973 bool PPCInstrInfo::DefinesPredicate(MachineInstr *MI,
974 std::vector &Pred) const {
975 // Note: At the present time, the contents of Pred from this function is
976 // unused by IfConversion. This implementation follows ARM by pushing the
977 // CR-defining operand. Because the 'DZ' and 'DNZ' count as types of
978 // predicate, instructions defining CTR or CTR8 are also included as
979 // predicate-defining instructions.
980
981 const TargetRegisterClass *RCs[] =
982 { &PPC::CRRCRegClass, &PPC::CRBITRCRegClass,
983 &PPC::CTRRCRegClass, &PPC::CTRRC8RegClass };
984
985 bool Found = false;
986 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
987 const MachineOperand &MO = MI->getOperand(i);
988 for (int c = 0; c < 2 && !Found; ++c) {
989 const TargetRegisterClass *RC = RCs[c];
990 for (TargetRegisterClass::iterator I = RC->begin(),
991 IE = RC->end(); I != IE; ++I) {
992 if ((MO.isRegMask() && MO.clobbersPhysReg(*I)) ||
993 (MO.isReg() && MO.isDef() && MO.getReg() == *I)) {
994 Pred.push_back(MO);
995 Found = true;
996 }
997 }
998 }
999 }
1000
1001 return Found;
1002 }
1003
1004 bool PPCInstrInfo::isPredicable(MachineInstr *MI) const {
1005 unsigned OpC = MI->getOpcode();
1006 switch (OpC) {
1007 default:
1008 return false;
1009 case PPC::B:
1010 case PPC::BLR:
1011 return true;
1012 }
8761013 }
8771014
8781015 /// GetInstSize - Return the number of bytes of code the specified
159159 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
160160 unsigned Reg, MachineRegisterInfo *MRI) const;
161161
162 // If conversion by predication (only supported by some branch instructions).
163 // All of the profitability checks always return true; it is always
164 // profitable to use the predicated branches.
165 virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB,
166 unsigned NumCycles, unsigned ExtraPredCycles,
167 const BranchProbability &Probability) const {
168 return true;
169 }
170
171 virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
172 unsigned NumT, unsigned ExtraT,
173 MachineBasicBlock &FMBB,
174 unsigned NumF, unsigned ExtraF,
175 const BranchProbability &Probability) const {
176 return true;
177 }
178
179 virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
180 unsigned NumCycles,
181 const BranchProbability
182 &Probability) const {
183 return true;
184 }
185
186 virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
187 MachineBasicBlock &FMBB) const {
188 return false;
189 }
190
191 // Predication support.
192 bool isPredicated(const MachineInstr *MI) const;
193
194 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
195
196 virtual
197 bool PredicateInstruction(MachineInstr *MI,
198 const SmallVectorImpl &Pred) const;
199
200 virtual
201 bool SubsumesPredicate(const SmallVectorImpl &Pred1,
202 const SmallVectorImpl &Pred2) const;
203
204 virtual bool DefinesPredicate(MachineInstr *MI,
205 std::vector &Pred) const;
206
207 virtual bool isPredicable(MachineInstr *MI) const;
208
162209 /// GetInstSize - Return the number of bytes of code the specified
163210 /// instruction may be. This returns the maximum number of bytes.
164211 ///
517517 let isReturn = 1, Uses = [LR, RM] in
518518 def BCLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$cond),
519519 "b${cond:cc}lr ${cond:reg}", BrB, []>;
520
521 let isReturn = 1, Defs = [CTR], Uses = [CTR, LR, RM] in {
522 def BDZLR : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
523 "bdzlr", BrB, []>;
524 def BDNZLR : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
525 "bdnzlr", BrB, []>;
526 }
520527 }
521528
522529 let Defs = [CTR], Uses = [CTR] in {
9292 virtual bool addPreRegAlloc();
9393 virtual bool addILPOpts();
9494 virtual bool addInstSelector();
95 virtual bool addPreSched2();
9596 virtual bool addPreEmitPass();
9697 };
9798 } // namespace
122123 return false;
123124 }
124125
126 bool PPCPassConfig::addPreSched2() {
127 if (getOptLevel() != CodeGenOpt::None)
128 addPass(&IfConverterID);
129
130 return true;
131 }
132
125133 bool PPCPassConfig::addPreEmitPass() {
126134 if (getOptLevel() != CodeGenOpt::None)
127135 addPass(createPPCEarlyReturnPass());
0 ; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s
1 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
2 target triple = "powerpc64-unknown-linux-gnu"
3
4 %struct.lua_TValue.17.692 = type { %union.Value.16.691, i32 }
5 %union.Value.16.691 = type { %union.GCObject.15.690* }
6 %union.GCObject.15.690 = type { %struct.lua_State.14.689 }
7 %struct.lua_State.14.689 = type { %union.GCObject.15.690*, i8, i8, i8, %struct.lua_TValue.17.692*, %struct.lua_TValue.17.692*, %struct.global_State.10.685*, %struct.CallInfo.11.686*, i32*, %struct.lua_TValue.17.692*, %struct.lua_TValue.17.692*, %struct.CallInfo.11.686*, %struct.CallInfo.11.686*, i32, i32, i16, i16, i8, i8, i32, i32, void (%struct.lua_State.14.689*, %struct.lua_Debug.12.687*)*, %struct.lua_TValue.17.692, %struct.lua_TValue.17.692, %union.GCObject.15.690*, %union.GCObject.15.690*, %struct.lua_longjmp.13.688*, i64 }
8 %struct.global_State.10.685 = type { %struct.stringtable.0.675, i8* (i8*, i8*, i64, i64)*, i8*, i8, i8, i32, %union.GCObject.15.690*, %union.GCObject.15.690**, %union.GCObject.15.690*, %union.GCObject.15.690*, %union.GCObject.15.690*, %union.GCObject.15.690*, %struct.Mbuffer.1.676, i64, i64, i64, i64, i32, i32, i32 (%struct.lua_State.14.689*)*, %struct.lua_TValue.17.692, %struct.lua_State.14.689*, %struct.UpVal.3.678, [9 x %struct.Table.7.682*], [17 x %union.TString.9.684*] }
9 %struct.stringtable.0.675 = type { %union.GCObject.15.690**, i32, i32 }
10 %struct.Mbuffer.1.676 = type { i8*, i64, i64 }
11 %struct.UpVal.3.678 = type { %union.GCObject.15.690*, i8, i8, %struct.lua_TValue.17.692*, %union.anon.2.677 }
12 %union.anon.2.677 = type { %struct.lua_TValue.17.692 }
13 %struct.Table.7.682 = type { %union.GCObject.15.690*, i8, i8, i8, i8, %struct.Table.7.682*, %struct.lua_TValue.17.692*, %struct.Node.6.681*, %struct.Node.6.681*, %union.GCObject.15.690*, i32 }
14 %struct.Node.6.681 = type { %struct.lua_TValue.17.692, %union.TKey.5.680 }
15 %union.TKey.5.680 = type { %struct.anon.0.4.679 }
16 %struct.anon.0.4.679 = type { %union.Value.16.691, i32, %struct.Node.6.681* }
17 %union.TString.9.684 = type { %struct.anon.1.8.683 }
18 %struct.anon.1.8.683 = type { %union.GCObject.15.690*, i8, i8, i8, i32, i64 }
19 %struct.CallInfo.11.686 = type { %struct.lua_TValue.17.692*, %struct.lua_TValue.17.692*, %struct.lua_TValue.17.692*, i32*, i32, i32 }
20 %struct.lua_Debug.12.687 = type { i32, i8*, i8*, i8*, i8*, i32, i32, i32, i32, [60 x i8], i32 }
21 %struct.lua_longjmp.13.688 = type opaque
22
23 define void @lua_xmove(i32 signext %n) #0 {
24 entry:
25 br i1 undef, label %for.end, label %if.end
26
27 if.end: ; preds = %entry
28 br i1 undef, label %for.body.lr.ph, label %for.end
29
30 for.body.lr.ph: ; preds = %if.end
31 br label %for.body
32
33 for.body: ; preds = %for.body.for.body_crit_edge, %for.body.lr.ph
34 %0 = phi %struct.lua_TValue.17.692* [ undef, %for.body.lr.ph ], [ %.pre, %for.body.for.body_crit_edge ]
35 %indvars.iv = phi i64 [ 0, %for.body.lr.ph ], [ %indvars.iv.next, %for.body.for.body_crit_edge ]
36 %tt = getelementptr inbounds %struct.lua_TValue.17.692* %0, i64 %indvars.iv, i32 1
37 %1 = load i32* %tt, align 4, !tbaa !0
38 store i32 %1, i32* undef, align 4, !tbaa !0
39 %indvars.iv.next = add i64 %indvars.iv, 1
40 %lftr.wideiv = trunc i64 %indvars.iv.next to i32
41 %exitcond = icmp eq i32 %lftr.wideiv, %n
42 br i1 %exitcond, label %for.end, label %for.body.for.body_crit_edge
43
44 for.body.for.body_crit_edge: ; preds = %for.body
45 %.pre = load %struct.lua_TValue.17.692** undef, align 8, !tbaa !3
46 br label %for.body
47
48 for.end: ; preds = %for.body, %if.end, %entry
49 ret void
50
51 ; CHECK: @lua_xmove
52 ; CHECK: bnelr
53 ; CHECK: bnelr
54 ; CHECK: bdzlr
55 }
56
57 attributes #0 = { nounwind }
58
59 !0 = metadata !{metadata !"int", metadata !1}
60 !1 = metadata !{metadata !"omnipotent char", metadata !2}
61 !2 = metadata !{metadata !"Simple C/C++ TBAA"}
62 !3 = metadata !{metadata !"any pointer", metadata !1}
0 ; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s
1 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
2 target triple = "powerpc64-unknown-linux-gnu"
3
4 define void @_Z8example3iPiS_() #0 {
5 entry:
6 br i1 undef, label %while.end, label %while.body.lr.ph
7
8 while.body.lr.ph: ; preds = %entry
9 br i1 undef, label %while.end, label %while.body
10
11 while.body: ; preds = %while.body, %while.body.lr.ph
12 br i1 false, label %while.end, label %while.body, !llvm.vectorizer.already_vectorized !0
13
14 while.end: ; preds = %while.body, %while.body.lr.ph, %entry
15 ret void
16
17 ; CHECK: @_Z8example3iPiS_
18 ; CHECK: bnelr
19 ; CHECK: bnelr
20 }
21
22 attributes #0 = { noinline nounwind }
23
24 !0 = metadata !{}
25