llvm.org GIT mirror llvm / 7e99a60
ARM: Define generic HINT instruction. The NOP, WFE, WFI, SEV and YIELD instructions are all hints w/ a different immediate value in bits [7,0]. Define a generic HINT instruction and refactor NOP, WFI, WFI, SEV and YIELD to be assembly aliases of that. rdar://11600518 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158674 91177308-0d34-0410-b5e6-96231b3b80d8 Jim Grosbach 8 years ago
6 changed file(s) with 82 addition(s) and 60 deletion(s). Raw diff Collapse all Expand all
3030 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
3131 void ARMInstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
3232 if (hasNOP()) {
33 NopInst.setOpcode(ARM::NOP);
33 NopInst.setOpcode(ARM::HINT);
34 NopInst.addOperand(MCOperand::CreateImm(0));
3435 NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
3536 NopInst.addOperand(MCOperand::CreateReg(0));
3637 } else {
15841584 NoItinerary, []>;
15851585 }
15861586
1587 def NOP : AI<(outs), (ins), MiscFrm, NoItinerary, "nop", "", []>,
1588 Requires<[IsARM, HasV6T2]> {
1589 let Inst{27-16} = 0b001100100000;
1590 let Inst{15-8} = 0b11110000;
1591 let Inst{7-0} = 0b00000000;
1592 }
1593
1594 def YIELD : AI<(outs), (ins), MiscFrm, NoItinerary, "yield", "", []>,
1595 Requires<[IsARM, HasV6T2]> {
1596 let Inst{27-16} = 0b001100100000;
1597 let Inst{15-8} = 0b11110000;
1598 let Inst{7-0} = 0b00000001;
1599 }
1600
1601 def WFE : AI<(outs), (ins), MiscFrm, NoItinerary, "wfe", "", []>,
1602 Requires<[IsARM, HasV6T2]> {
1603 let Inst{27-16} = 0b001100100000;
1604 let Inst{15-8} = 0b11110000;
1605 let Inst{7-0} = 0b00000010;
1606 }
1607
1608 def WFI : AI<(outs), (ins), MiscFrm, NoItinerary, "wfi", "", []>,
1609 Requires<[IsARM, HasV6T2]> {
1610 let Inst{27-16} = 0b001100100000;
1611 let Inst{15-8} = 0b11110000;
1612 let Inst{7-0} = 0b00000011;
1613 }
1587 def HINT : AI<(outs), (ins imm0_255:$imm), MiscFrm, NoItinerary,
1588 "hint", "\t$imm", []>, Requires<[IsARM, HasV6]> {
1589 bits<8> imm;
1590 let Inst{27-8} = 0b00110010000011110000;
1591 let Inst{7-0} = imm;
1592 }
1593
1594 def : InstAlias<"nop$p", (HINT 0, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1595 def : InstAlias<"yield$p", (HINT 1, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1596 def : InstAlias<"wfe$p", (HINT 2, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1597 def : InstAlias<"wfi$p", (HINT 3, pred:$p)>, Requires<[IsARM, HasV6T2]>;
1598 def : InstAlias<"sev$p", (HINT 4, pred:$p)>, Requires<[IsARM, HasV6T2]>;
16141599
16151600 def SEL : AI<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm, NoItinerary, "sel",
16161601 "\t$Rd, $Rn, $Rm", []>, Requires<[IsARM, HasV6]> {
16231608 let Inst{27-20} = 0b01101000;
16241609 let Inst{7-4} = 0b1011;
16251610 let Inst{11-8} = 0b1111;
1626
16271611 let Unpredictable{11-8} = 0b1111;
16281612 }
16291613
1630 def SEV : AI<(outs), (ins), MiscFrm, NoItinerary, "sev", "",
1631 []>, Requires<[IsARM, HasV6T2]> {
1632 let Inst{27-16} = 0b001100100000;
1633 let Inst{15-8} = 0b11110000;
1634 let Inst{7-0} = 0b00000100;
1635 }
1636
1637 // The i32imm operand $val can be used by a debugger to store more information
1614 // The 16-bit operand $val can be used by a debugger to store more information
16381615 // about the breakpoint.
16391616 def BKPT : AI<(outs), (ins imm0_65535:$val), MiscFrm, NoItinerary,
16401617 "bkpt", "\t$val", []>, Requires<[IsARM]> {
34563456
34573457 // A6.3.4 Branches and miscellaneous control
34583458 // Table A6-14 Change Processor State, and hint instructions
3459 class T2I_hint op7_0, string opc, string asm>
3460 : T2I<(outs), (ins), NoItinerary, opc, asm, []> {
3461 let Inst{31-20} = 0xf3a;
3462 let Inst{19-16} = 0b1111;
3463 let Inst{15-14} = 0b10;
3464 let Inst{12} = 0;
3465 let Inst{10-8} = 0b000;
3466 let Inst{7-0} = op7_0;
3467 }
3468
3469 def t2NOP : T2I_hint<0b00000000, "nop", ".w">;
3470 def t2YIELD : T2I_hint<0b00000001, "yield", ".w">;
3471 def t2WFE : T2I_hint<0b00000010, "wfe", ".w">;
3472 def t2WFI : T2I_hint<0b00000011, "wfi", ".w">;
3473 def t2SEV : T2I_hint<0b00000100, "sev", ".w">;
3459 def t2HINT : T2I<(outs), (ins imm0_255:$imm), NoItinerary, "hint", "\t$imm",[]>{
3460 bits<8> imm;
3461 let Inst{31-8} = 0b111100111010111110000000;
3462 let Inst{7-0} = imm;
3463 }
3464
3465 def : t2InstAlias<"hint$p.w $imm", (t2HINT imm0_255:$imm, pred:$p)>;
3466 def : t2InstAlias<"nop$p.w", (t2HINT 0, pred:$p)>;
3467 def : t2InstAlias<"yield$p.w", (t2HINT 1, pred:$p)>;
3468 def : t2InstAlias<"wfe$p.w", (t2HINT 2, pred:$p)>;
3469 def : t2InstAlias<"wfi$p.w", (t2HINT 3, pred:$p)>;
3470 def : t2InstAlias<"sev$p.w", (t2HINT 4, pred:$p)>;
34743471
34753472 def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt", []> {
34763473 bits<4> opt;
5050 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
5151 StringRef Annot) {
5252 unsigned Opcode = MI->getOpcode();
53
54 // Check for HINT instructions w/ canonical names.
55 if (Opcode == ARM::HINT || Opcode == ARM::t2HINT) {
56 switch (MI->getOperand(0).getImm()) {
57 case 0: O << "\tnop"; break;
58 case 1: O << "\tyield"; break;
59 case 2: O << "\twfe"; break;
60 case 3: O << "\twfi"; break;
61 case 4: O << "\tsev"; break;
62 default:
63 // Anything else should just print normally.
64 printInstruction(MI, O);
65 printAnnotation(O, Annot);
66 return;
67 }
68 printPredicateOperand(MI, 1, O);
69 if (Opcode == ARM::t2HINT)
70 O << ".w";
71 printAnnotation(O, Annot);
72 return;
73 }
5374
5475 // Check for MOVs and print canonical forms, instead.
5576 if (Opcode == ARM::MOVsr) {
27102710 wfilt
27112711 yield
27122712 yieldne
2713
2714 @ CHECK: wfe @ encoding: [0x02,0xf0,0x20,0xe3]
2715 @ CHECK: wfehi @ encoding: [0x02,0xf0,0x20,0x83]
2716 @ CHECK: wfi @ encoding: [0x03,0xf0,0x20,0xe3]
2717 @ CHECK: wfilt @ encoding: [0x03,0xf0,0x20,0xb3]
2718 @ CHECK: yield @ encoding: [0x01,0xf0,0x20,0xe3]
2719 @ CHECK: yieldne @ encoding: [0x01,0xf0,0x20,0x13]
2713 hint #5
2714 hint #4
2715 hint #3
2716 hint #2
2717 hint #1
2718 hint #0
2719
2720 @ CHECK: wfe @ encoding: [0x02,0xf0,0x20,0xe3]
2721 @ CHECK: wfehi @ encoding: [0x02,0xf0,0x20,0x83]
2722 @ CHECK: wfi @ encoding: [0x03,0xf0,0x20,0xe3]
2723 @ CHECK: wfilt @ encoding: [0x03,0xf0,0x20,0xb3]
2724 @ CHECK: yield @ encoding: [0x01,0xf0,0x20,0xe3]
2725 @ CHECK: yieldne @ encoding: [0x01,0xf0,0x20,0x13]
2726 @ CHECK: hint #5 @ encoding: [0x05,0xf0,0x20,0xe3]
2727 @ CHECK: sev @ encoding: [0x04,0xf0,0x20,0xe3]
2728 @ CHECK: wfi @ encoding: [0x03,0xf0,0x20,0xe3]
2729 @ CHECK: wfe @ encoding: [0x02,0xf0,0x20,0xe3]
2730 @ CHECK: yield @ encoding: [0x01,0xf0,0x20,0xe3]
2731 @ CHECK: nop @ encoding: [0x00,0xf0,0x20,0xe3]
33683368 @ CHECK: uxth.w r7, r8 @ encoding: [0x1f,0xfa,0x88,0xf7]
33693369
33703370 @------------------------------------------------------------------------------
3371 @ WFE/WFI/YIELD
3371 @ WFE/WFI/YIELD/HINT
33723372 @------------------------------------------------------------------------------
33733373 wfe
33743374 wfi
33773377 wfelt
33783378 wfige
33793379 yieldlt
3380 hint #5
3381 hint.w #5
3382 hint.w #4
3383 hint #3
3384 hint #2
3385 hint #1
3386 hint #0
33803387
33813388 @ CHECK: wfe @ encoding: [0x20,0xbf]
33823389 @ CHECK: wfi @ encoding: [0x30,0xbf]
33853392 @ CHECK: wfelt @ encoding: [0x20,0xbf]
33863393 @ CHECK: wfige @ encoding: [0x30,0xbf]
33873394 @ CHECK: yieldlt @ encoding: [0x10,0xbf]
3395 @ CHECK: hint #5 @ encoding: [0xaf,0xf3,0x05,0x80]
3396 @ CHECK: hint #5 @ encoding: [0xaf,0xf3,0x05,0x80]
3397 @ CHECK: sev.w @ encoding: [0xaf,0xf3,0x04,0x80]
3398 @ CHECK: wfi.w @ encoding: [0xaf,0xf3,0x03,0x80]
3399 @ CHECK: wfe.w @ encoding: [0xaf,0xf3,0x02,0x80]
3400 @ CHECK: yield.w @ encoding: [0xaf,0xf3,0x01,0x80]
3401 @ CHECK: nop.w @ encoding: [0xaf,0xf3,0x00,0x80]
33883402
33893403
33903404 @------------------------------------------------------------------------------