llvm.org GIT mirror llvm / 7e6b531
[globalisel][tablegen] Require that all registers between instructions of a match are virtual. Summary: Without this, it's possible to encounter multiple defs for a register. This is triggered by the current version of D32868 when applied to trunk. Reviewers: qcolombet, ab, t.p.northover, rovka, kristof.beyls Reviewed By: qcolombet Subscribers: llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D32869 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303253 91177308-0d34-0410-b5e6-96231b3b80d8 Daniel Sanders 3 years ago
2 changed file(s) with 6 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
136136 // CHECK-NEXT: if (MI0.getNumOperands() < 3)
137137 // CHECK-NEXT: return false;
138138 // CHECK-NEXT: if (!MI0.getOperand(1).isReg())
139 // CHECK-NEXT: return false;
140 // CHECK-NEXT: if (TRI.isPhysicalRegister(MI0.getOperand(1).getReg()))
139141 // CHECK-NEXT: return false;
140142 // CHECK-NEXT: MachineInstr &MI1 = *MRI.getVRegDef(MI0.getOperand(1).getReg());
141143 // CHECK-NEXT: if (MI1.getNumOperands() < 3)
179181 // CHECK-NEXT: return false;
180182 // CHECK-NEXT: if (!MI0.getOperand(2).isReg())
181183 // CHECK-NEXT: return false;
184 // CHECK-NEXT: if (TRI.isPhysicalRegister(MI0.getOperand(2).getReg()))
185 // CHECK-NEXT: return false;
182186 // CHECK-NEXT: MachineInstr &MI1 = *MRI.getVRegDef(MI0.getOperand(2).getReg());
183187 // CHECK-NEXT: if (MI1.getNumOperands() < 3)
184188 // CHECK-NEXT: return false;
774774 void emitCxxCaptureStmts(raw_ostream &OS, RuleMatcher &Rule,
775775 StringRef OperandExpr) const override {
776776 OS << "if (!" << OperandExpr + ".isReg())\n"
777 << " return false;\n"
778 << "if (TRI.isPhysicalRegister(" << OperandExpr + ".getReg()))\n"
777779 << " return false;\n";
778780 std::string InsnVarName = Rule.defineInsnVar(
779781 OS, *InsnMatcher,