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AMDGPU: Add instruction definitions for VGPR indexing VI added a second method of indexing into VGPRs besides using v_movrel* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284027 91177308-0d34-0410-b5e6-96231b3b80d8 Matt Arsenault 4 years ago
14 changed file(s) with 172 addition(s) and 12 deletion(s). Raw diff Collapse all Expand all
167167 "Has i16/f16 instructions"
168168 >;
169169
170 def FeatureMovrel : SubtargetFeature<"movrel",
171 "HasMovrel",
172 "true",
173 "Has v_movrel*_b32 instructions"
174 >;
175
176 def FeatureVGPRIndexMode : SubtargetFeature<"vgpr-index-mode",
177 "HasVGPRIndexMode",
178 "true",
179 "Has VGPR mode register indexing"
180 >;
181
170182 //===------------------------------------------------------------===//
171183 // Subtarget Features (options and debugging)
172184 //===------------------------------------------------------------===//
294306 def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
295307 [FeatureFP64, FeatureLocalMemorySize32768,
296308 FeatureWavefrontSize64, FeatureGCN, FeatureGCN1Encoding,
297 FeatureLDSBankCount32]
309 FeatureLDSBankCount32, FeatureMovrel]
298310 >;
299311
300312 def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
301313 [FeatureFP64, FeatureLocalMemorySize65536,
302314 FeatureWavefrontSize64, FeatureGCN, FeatureFlatAddressSpace,
303 FeatureGCN1Encoding, FeatureCIInsts]
315 FeatureGCN1Encoding, FeatureCIInsts, FeatureMovrel]
304316 >;
305317
306318 def FeatureVolcanicIslands : SubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
307319 [FeatureFP64, FeatureLocalMemorySize65536,
308320 FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
309321 FeatureGCN3Encoding, FeatureCIInsts, Feature16BitInsts,
310 FeatureSMemRealTime
322 FeatureSMemRealTime, FeatureVGPRIndexMode, FeatureMovrel
311323 ]
312324 >;
313325
106106 SGPRInitBug(false),
107107 HasSMemRealTime(false),
108108 Has16BitInsts(false),
109 HasMovrel(false),
110 HasVGPRIndexMode(false),
109111 FlatAddressSpace(false),
110112
111113 R600ALUInst(false),
9898 bool SGPRInitBug;
9999 bool HasSMemRealTime;
100100 bool Has16BitInsts;
101 bool HasMovrel;
102 bool HasVGPRIndexMode;
101103 bool FlatAddressSpace;
102104 bool R600ALUInst;
103105 bool CaymanISA;
500502 return Has16BitInsts;
501503 }
502504
505 bool hasMovrel() const {
506 return HasMovrel;
507 }
508
509 bool hasVGPRIndexMode() const {
510 return HasVGPRIndexMode;
511 }
512
503513 bool hasScalarCompareEq64() const {
504514 return getGeneration() >= VOLCANIC_ISLANDS;
505515 }
343343 bool isSMRDOffset() const;
344344 bool isSMRDLiteralOffset() const;
345345 bool isDPPCtrl() const;
346 bool isGPRIdxMode() const;
346347
347348 StringRef getExpressionAsToken() const {
348349 assert(isExpr());
27432744 return false;
27442745 }
27452746
2747 bool AMDGPUOperand::isGPRIdxMode() const {
2748 return isImm() && isUInt<4>(getImm());
2749 }
2750
27462751 AMDGPUAsmParser::OperandMatchResultTy
27472752 AMDGPUAsmParser::parseDPPCtrl(OperandVector &Operands) {
27482753 SMLoc S = Parser.getTok().getLoc();
3333 }
3434
3535 void AMDGPUInstPrinter::printU4ImmOperand(const MCInst *MI, unsigned OpNo,
36 const MCSubtargetInfo &STI,
3637 raw_ostream &O) {
3738 O << formatHex(MI->getOperand(OpNo).getImm() & 0xf);
3839 }
509510 const MCSubtargetInfo &STI,
510511 raw_ostream &O) {
511512 O << " row_mask:";
512 printU4ImmOperand(MI, OpNo, O);
513 printU4ImmOperand(MI, OpNo, STI, O);
513514 }
514515
515516 void AMDGPUInstPrinter::printBankMask(const MCInst *MI, unsigned OpNo,
516517 const MCSubtargetInfo &STI,
517518 raw_ostream &O) {
518519 O << " bank_mask:";
519 printU4ImmOperand(MI, OpNo, O);
520 printU4ImmOperand(MI, OpNo, STI, O);
520521 }
521522
522523 void AMDGPUInstPrinter::printBoundCtrl(const MCInst *MI, unsigned OpNo,
595596 } else {
596597 llvm_unreachable("Invalid interpolation parameter slot");
597598 }
599 }
600
601 void AMDGPUInstPrinter::printVGPRIndexMode(const MCInst *MI, unsigned OpNo,
602 const MCSubtargetInfo &STI,
603 raw_ostream &O) {
604 unsigned Val = MI->getOperand(OpNo).getImm();
605 if (Val == 0) {
606 O << " 0";
607 return;
608 }
609
610 if (Val & VGPRIndexMode::DST_ENABLE)
611 O << " dst";
612
613 if (Val & VGPRIndexMode::SRC0_ENABLE)
614 O << " src0";
615
616 if (Val & VGPRIndexMode::SRC1_ENABLE)
617 O << " src1";
618
619 if (Val & VGPRIndexMode::SRC2_ENABLE)
620 O << " src2";
598621 }
599622
600623 void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo,
3333 const MCRegisterInfo &MRI);
3434
3535 private:
36 void printU4ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
36 void printU4ImmOperand(const MCInst *MI, unsigned OpNo,
37 const MCSubtargetInfo &STI, raw_ostream &O);
3738 void printU8ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
3839 void printU16ImmOperand(const MCInst *MI, unsigned OpNo,
3940 const MCSubtargetInfo &STI, raw_ostream &O);
106107 const MCSubtargetInfo &STI, raw_ostream &O);
107108 void printInterpSlot(const MCInst *MI, unsigned OpNo,
108109 const MCSubtargetInfo &STI, raw_ostream &O);
110 void printVGPRIndexMode(const MCInst *MI, unsigned OpNo,
111 const MCSubtargetInfo &STI, raw_ostream &O);
109112 void printMemOperand(const MCInst *MI, unsigned OpNo,
110113 const MCSubtargetInfo &STI, raw_ostream &O);
111114 static void printIfSet(const MCInst *MI, unsigned OpNo, raw_ostream &O,
106106 MUL2 = 1,
107107 MUL4 = 2,
108108 DIV2 = 3
109 };
110 }
111
112 namespace VGPRIndexMode {
113 enum {
114 SRC0_ENABLE = 1 << 0,
115 SRC1_ENABLE = 1 << 1,
116 SRC2_ENABLE = 1 << 2,
117 DST_ENABLE = 1 << 3
109118 };
110119 }
111120
1919
2020 def has16BankLDS : Predicate<"Subtarget->getLDSBankCount() == 16">;
2121 def has32BankLDS : Predicate<"Subtarget->getLDSBankCount() == 32">;
22 def HasVGPRIndexMode : Predicate<"Subtarget->hasVGPRIndexMode()">,
23 AssemblerPredicate<"FeatureVGPRIndexMode">;
24 def HasMovrel : Predicate<"Subtarget->hasMovrel()">,
25 AssemblerPredicate<"FeatureMovrel">;
2226
2327 include "VOPInstructions.td"
2428 include "SOPInstructions.td"
55 // License. See LICENSE.TXT for details.
66 //
77 //===----------------------------------------------------------------------===//
8
9 def GPRIdxModeMatchClass : AsmOperandClass {
10 let Name = "GPRIdxMode";
11 let PredicateMethod = "isGPRIdxMode";
12 let RenderMethod = "addImmOperands";
13 }
14
15 def GPRIdxMode : Operand {
16 let PrintMethod = "printVGPRIndexMode";
17 let ParserMatchClass = GPRIdxModeMatchClass;
18 let OperandType = "OPERAND_IMMEDIATE";
19 }
820
921 //===----------------------------------------------------------------------===//
1022 // SOP1 Instructions
6274 "$sdst, $src0", pattern
6375 >;
6476
77 // 32-bit input, no output.
78 class SOP1_0_32 pattern = []> : SOP1_Pseudo <
79 opName, (outs), (ins SSrc_b32:$src0),
80 "$src0", pattern> {
81 let has_sdst = 0;
82 }
83
6584 class SOP1_64 pattern=[]> : SOP1_Pseudo <
6685 opName, (outs SReg_64:$sdst), (ins SSrc_b64:$src0),
6786 "$sdst, $src0", pattern
197216 } // End Defs = [SCC]
198217 def S_MOV_FED_B32 : SOP1_32 <"s_mov_fed_b32">;
199218
219 let SubtargetPredicate = HasVGPRIndexMode in {
220 def S_SET_GPR_IDX_IDX : SOP1_0_32<"s_set_gpr_idx_idx"> {
221 let Uses = [M0];
222 let Defs = [M0];
223 }
224 }
200225
201226 //===----------------------------------------------------------------------===//
202227 // SOP2 Instructions
596621 let Inst{31-23} = 0x17e;
597622 }
598623
599 class SOPC op, dag outs, dag ins, string asm, list pattern> :
624 class SOPC op, dag outs, dag ins, string asm,
625 list pattern = []> :
600626 InstSI, SOPCe {
601627 let mayLoad = 0;
602628 let mayStore = 0;
669695 def S_CMP_LG_U64 : SOPC_CMP_64 <0x13, "s_cmp_lg_u64", COND_NE>;
670696 }
671697
698 let SubtargetPredicate = HasVGPRIndexMode in {
699 def S_SET_GPR_IDX_ON : SOPC <0x11,
700 (outs),
701 (ins SSrc_b32:$src0, GPRIdxMode:$src1),
702 "s_set_gpr_idx_on $src0,$src1"> {
703 let Defs = [M0]; // No scc def
704 let Uses = [M0]; // Other bits of m0 unmodified.
705 let hasSideEffects = 1; // Sets mode.gpr_idx_en
706 }
707 }
708
672709 //===----------------------------------------------------------------------===//
673710 // SOPP Instructions
674711 //===----------------------------------------------------------------------===//
808845 def S_TTRACEDATA : SOPP <0x00000016, (ins), "s_ttracedata"> {
809846 let simm16 = 0;
810847 }
848
849 let SubtargetPredicate = HasVGPRIndexMode in {
850 def S_SET_GPR_IDX_OFF : SOPP<0x1c, (ins), "s_set_gpr_idx_off"> {
851 let simm16 = 0;
852 }
853 }
811854 } // End hasSideEffects
812855
856 let SubtargetPredicate = HasVGPRIndexMode in {
857 def S_SET_GPR_IDX_MODE : SOPP<0x1d, (ins GPRIdxMode:$simm16),
858 "s_set_gpr_idx_mode$simm16"> {
859 let Defs = [M0];
860 }
861 }
813862
814863 let Predicates = [isGCN] in {
815864
10701119 def S_MOV_REGRD_B32_vi : SOP1_Real_vi <0x2f, S_MOV_REGRD_B32>;
10711120 def S_ABS_I32_vi : SOP1_Real_vi <0x30, S_ABS_I32>;
10721121 def S_MOV_FED_B32_vi : SOP1_Real_vi <0x31, S_MOV_FED_B32>;
1122 def S_SET_GPR_IDX_IDX_vi : SOP1_Real_vi <0x32, S_SET_GPR_IDX_IDX>;
10731123
10741124 def S_ADD_U32_vi : SOP2_Real_vi <0x00, S_ADD_U32>;
10751125 def S_ADD_I32_vi : SOP2_Real_vi <0x02, S_ADD_I32>;
228228 let EmitDst = 1; // force vdst emission
229229 }
230230
231 let Uses = [M0, EXEC] in {
231 let SubtargetPredicate = HasMovrel, Uses = [M0, EXEC] in {
232232 // v_movreld_b32 is a special case because the destination output
233233 // register is really a source. It isn't actually read (but may be
234234 // written), and is only to provide the base register to start
None // RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck --check-prefix=GCN --check-prefix=SICI %s
1 // RUN: llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck --check-prefix=GCN --check-prefix=SICI %s
0 // RUN: not llvm-mc -arch=amdgcn -show-encoding %s | FileCheck --check-prefix=GCN --check-prefix=SICI %s
1 // RUN: not llvm-mc -arch=amdgcn -show-encoding %s 2>&1 | FileCheck --check-prefix=NOSICI %s
22 // RUN: not llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s 2>&1 | FileCheck --check-prefix=GCN --check-prefix=VI %s
33 // RUN: not llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s 2>&1 | FileCheck --check-prefix=NOVI %s
44
241241
242242 s_mov_fed_b32 s1, s2
243243 // SICI: s_mov_fed_b32 s1, s2 ; encoding: [0x02,0x35,0x81,0xbe]
244
245 s_set_gpr_idx_idx s0
246 // VI: s_set_gpr_idx_idx s0 ; encoding: [0x00,0x32,0x80,0xbe]
247 // NOSICI: error: instruction not supported on this GPU
0 // RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=VI %s
1
2 s_set_gpr_idx_on s0, s1
3 // GCN: error: invalid operand for instruction
4
5 s_set_gpr_idx_on s0, 16
6 // GCN: error: invalid operand for instruction
7
8 s_set_gpr_idx_on s0, -1
9 // GCN: error: invalid operand for instruction
6363 s_cmp_lg_u64 s[0:1], s[2:3]
6464 // VI: s_cmp_lg_u64 s[0:1], s[2:3] ; encoding: [0x00,0x02,0x13,0xbf]
6565 // NOSICI: error: instruction not supported on this GPU
66
67 s_set_gpr_idx_on s0, 0
68 // VI: s_set_gpr_idx_on s0, 0 ; encoding: [0x00,0x00,0x11,0xbf]
69 // NOSICI: error: instruction not supported on this GPU
70
71 s_set_gpr_idx_on s0, 1
72 // VI: s_set_gpr_idx_on s0, src0 ; encoding: [0x00,0x01,0x11,0xbf]
73 // NOSICI: error: instruction not supported on this GPU
74
75 s_set_gpr_idx_on s0, 3
76 // VI: s_set_gpr_idx_on s0, src0 src1 ; encoding: [0x00,0x03,0x11,0xbf]
77 // NOSICI: error: instruction not supported on this GPU
78
79 s_set_gpr_idx_on s0, 15
80 // VI: s_set_gpr_idx_on s0, dst src0 src1 src2 ; encoding: [0x00,0x0f,0x11,0xbf]
81 // NOSICI: error: instruction not supported on this GPU
None // RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck --check-prefix=GCN --check-prefix=SICI %s
1 // RUN: llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck --check-prefix=GCN --check-prefix=SICI %s
0 // RUN: not llvm-mc -arch=amdgcn -show-encoding %s | FileCheck --check-prefix=GCN --check-prefix=SICI %s
1 // RUN: not llvm-mc -arch=amdgcn -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSICI
22 // RUN: llvm-mc -arch=amdgcn -mcpu=fiji -show-encoding %s | FileCheck --check-prefix=GCN --check-prefix=VI %s
33
44 //===----------------------------------------------------------------------===//
175175
176176 s_ttracedata
177177 // GCN: s_ttracedata ; encoding: [0x00,0x00,0x96,0xbf]
178
179 s_set_gpr_idx_off
180 // VI: s_set_gpr_idx_off ; encoding: [0x00,0x00,0x9c,0xbf]
181 // NOSICI: error: instruction not supported on this GPU
182
183 s_set_gpr_idx_mode 0
184 // VI: s_set_gpr_idx_mode 0 ; encoding: [0x00,0x00,0x9d,0xbf]
185 // NOSICI: error: instruction not supported on this GPU
186
187 s_set_gpr_idx_mode 15
188 // VI: s_set_gpr_idx_mode dst src0 src1 src2 ; encoding: [0x0f,0x00,0x9d,0xbf]
189 // NOSICI: error: instruction not supported on this GPU