llvm.org GIT mirror llvm / 7e18b99
X86: Use enums for memory operand decoding instead of integer literals. Summary: X86BaseInfo.h defines an enum for the offset of each operand in a memory operand sequence. Some code uses it and some does not. This patch replaces (hopefully) all remaining locations where an integer literal was used instead of this enum. No functionality change intended. Reviewers: nadav CC: llvm-commits, t.p.northover Differential Revision: http://llvm-reviews.chandlerc.com/D3108 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204158 91177308-0d34-0410-b5e6-96231b3b80d8 Manuel Jacob 6 years ago
5 changed file(s) with 54 addition(s) and 53 deletion(s). Raw diff Collapse all Expand all
181181
182182 void X86ATTInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
183183 raw_ostream &O) {
184 const MCOperand &BaseReg = MI->getOperand(Op);
185 const MCOperand &IndexReg = MI->getOperand(Op+2);
186 const MCOperand &DispSpec = MI->getOperand(Op+3);
187 const MCOperand &SegReg = MI->getOperand(Op+4);
184 const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg);
185 const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg);
186 const MCOperand &DispSpec = MI->getOperand(Op+X86::AddrDisp);
187 const MCOperand &SegReg = MI->getOperand(Op+X86::AddrSegmentReg);
188188
189189 O << markup("
190190
191191 // If this has a segment register, print it.
192192 if (SegReg.getReg()) {
193 printOperand(MI, Op+4, O);
193 printOperand(MI, Op+X86::AddrSegmentReg, O);
194194 O << ':';
195195 }
196196
206206 if (IndexReg.getReg() || BaseReg.getReg()) {
207207 O << '(';
208208 if (BaseReg.getReg())
209 printOperand(MI, Op, O);
209 printOperand(MI, Op+X86::AddrBaseReg, O);
210210
211211 if (IndexReg.getReg()) {
212212 O << ',';
213 printOperand(MI, Op+2, O);
214 unsigned ScaleVal = MI->getOperand(Op+1).getImm();
213 printOperand(MI, Op+X86::AddrIndexReg, O);
214 unsigned ScaleVal = MI->getOperand(Op+X86::AddrScaleAmt).getImm();
215215 if (ScaleVal != 1) {
216216 O << ','
217217 << markup("
161161
162162 void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
163163 raw_ostream &O) {
164 const MCOperand &BaseReg = MI->getOperand(Op);
165 unsigned ScaleVal = MI->getOperand(Op+1).getImm();
166 const MCOperand &IndexReg = MI->getOperand(Op+2);
167 const MCOperand &DispSpec = MI->getOperand(Op+3);
168 const MCOperand &SegReg = MI->getOperand(Op+4);
164 const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg);
165 unsigned ScaleVal = MI->getOperand(Op+X86::AddrScaleAmt).getImm();
166 const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg);
167 const MCOperand &DispSpec = MI->getOperand(Op+X86::AddrDisp);
168 const MCOperand &SegReg = MI->getOperand(Op+X86::AddrSegmentReg);
169169
170170 // If this has a segment register, print it.
171171 if (SegReg.getReg()) {
172 printOperand(MI, Op+4, O);
172 printOperand(MI, Op+X86::AddrSegmentReg, O);
173173 O << ':';
174174 }
175175
177177
178178 bool NeedPlus = false;
179179 if (BaseReg.getReg()) {
180 printOperand(MI, Op, O);
180 printOperand(MI, Op+X86::AddrBaseReg, O);
181181 NeedPlus = true;
182182 }
183183
185185 if (NeedPlus) O << " + ";
186186 if (ScaleVal != 1)
187187 O << ScaleVal << '*';
188 printOperand(MI, Op+2, O);
188 printOperand(MI, Op+X86::AddrIndexReg, O);
189189 NeedPlus = true;
190190 }
191191
234234 static void printLeaMemReference(X86AsmPrinter &P, const MachineInstr *MI,
235235 unsigned Op, raw_ostream &O,
236236 const char *Modifier = NULL) {
237 const MachineOperand &BaseReg = MI->getOperand(Op);
238 const MachineOperand &IndexReg = MI->getOperand(Op+2);
239 const MachineOperand &DispSpec = MI->getOperand(Op+3);
237 const MachineOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg);
238 const MachineOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg);
239 const MachineOperand &DispSpec = MI->getOperand(Op+X86::AddrDisp);
240240
241241 // If we really don't want to print out (rip), don't.
242242 bool HasBaseReg = BaseReg.getReg() != 0;
258258 }
259259 case MachineOperand::MO_GlobalAddress:
260260 case MachineOperand::MO_ConstantPoolIndex:
261 printSymbolOperand(P, MI->getOperand(Op + 3), O);
261 printSymbolOperand(P, DispSpec, O);
262262 }
263263
264264 if (Modifier && strcmp(Modifier, "H") == 0)
270270
271271 O << '(';
272272 if (HasBaseReg)
273 printOperand(P, MI, Op, O, Modifier);
273 printOperand(P, MI, Op+X86::AddrBaseReg, O, Modifier);
274274
275275 if (IndexReg.getReg()) {
276276 O << ',';
277 printOperand(P, MI, Op+2, O, Modifier);
278 unsigned ScaleVal = MI->getOperand(Op+1).getImm();
277 printOperand(P, MI, Op+X86::AddrIndexReg, O, Modifier);
278 unsigned ScaleVal = MI->getOperand(Op+X86::AddrScaleAmt).getImm();
279279 if (ScaleVal != 1)
280280 O << ',' << ScaleVal;
281281 }
287287 unsigned Op, raw_ostream &O,
288288 const char *Modifier = NULL) {
289289 assert(isMem(MI, Op) && "Invalid memory reference!");
290 const MachineOperand &Segment = MI->getOperand(Op+4);
290 const MachineOperand &Segment = MI->getOperand(Op+X86::AddrSegmentReg);
291291 if (Segment.getReg()) {
292 printOperand(P, MI, Op+4, O, Modifier);
292 printOperand(P, MI, Op+X86::AddrSegmentReg, O, Modifier);
293293 O << ':';
294294 }
295295 printLeaMemReference(P, MI, Op, O, Modifier);
299299 unsigned Op, raw_ostream &O,
300300 const char *Modifier = NULL,
301301 unsigned AsmVariant = 1) {
302 const MachineOperand &BaseReg = MI->getOperand(Op);
303 unsigned ScaleVal = MI->getOperand(Op+1).getImm();
304 const MachineOperand &IndexReg = MI->getOperand(Op+2);
305 const MachineOperand &DispSpec = MI->getOperand(Op+3);
306 const MachineOperand &SegReg = MI->getOperand(Op+4);
302 const MachineOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg);
303 unsigned ScaleVal = MI->getOperand(Op+X86::AddrScaleAmt).getImm();
304 const MachineOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg);
305 const MachineOperand &DispSpec = MI->getOperand(Op+X86::AddrDisp);
306 const MachineOperand &SegReg = MI->getOperand(Op+X86::AddrSegmentReg);
307307
308308 // If this has a segment register, print it.
309309 if (SegReg.getReg()) {
310 printOperand(P, MI, Op+4, O, Modifier, AsmVariant);
310 printOperand(P, MI, Op+X86::AddrSegmentReg, O, Modifier, AsmVariant);
311311 O << ':';
312312 }
313313
315315
316316 bool NeedPlus = false;
317317 if (BaseReg.getReg()) {
318 printOperand(P, MI, Op, O, Modifier, AsmVariant);
318 printOperand(P, MI, Op+X86::AddrBaseReg, O, Modifier, AsmVariant);
319319 NeedPlus = true;
320320 }
321321
323323 if (NeedPlus) O << " + ";
324324 if (ScaleVal != 1)
325325 O << ScaleVal << '*';
326 printOperand(P, MI, Op+2, O, Modifier, AsmVariant);
326 printOperand(P, MI, Op+X86::AddrIndexReg, O, Modifier, AsmVariant);
327327 NeedPlus = true;
328328 }
329329
330330 if (!DispSpec.isImm()) {
331331 if (NeedPlus) O << " + ";
332 printOperand(P, MI, Op+3, O, Modifier, AsmVariant);
332 printOperand(P, MI, Op+X86::AddrDisp, O, Modifier, AsmVariant);
333333 } else {
334334 int64_t DispVal = DispSpec.getImm();
335335 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
110110
111111 inline static bool isLeaMem(const MachineInstr *MI, unsigned Op) {
112112 if (MI->getOperand(Op).isFI()) return true;
113 return Op+4 <= MI->getNumOperands() &&
114 MI->getOperand(Op ).isReg() && isScale(MI->getOperand(Op+1)) &&
115 MI->getOperand(Op+2).isReg() &&
116 (MI->getOperand(Op+3).isImm() ||
117 MI->getOperand(Op+3).isGlobal() ||
118 MI->getOperand(Op+3).isCPI() ||
119 MI->getOperand(Op+3).isJTI());
113 return Op+X86::AddrSegmentReg <= MI->getNumOperands() &&
114 MI->getOperand(Op+X86::AddrBaseReg).isReg() &&
115 isScale(MI->getOperand(Op+X86::AddrScaleAmt)) &&
116 MI->getOperand(Op+X86::AddrIndexReg).isReg() &&
117 (MI->getOperand(Op+X86::AddrDisp).isImm() ||
118 MI->getOperand(Op+X86::AddrDisp).isGlobal() ||
119 MI->getOperand(Op+X86::AddrDisp).isCPI() ||
120 MI->getOperand(Op+X86::AddrDisp).isJTI());
120121 }
121122
122123 inline static bool isMem(const MachineInstr *MI, unsigned Op) {
123124 if (MI->getOperand(Op).isFI()) return true;
124 return Op+5 <= MI->getNumOperands() &&
125 MI->getOperand(Op+4).isReg() &&
125 return Op+X86::AddrNumOperands <= MI->getNumOperands() &&
126 MI->getOperand(Op+X86::AddrSegmentReg).isReg() &&
126127 isLeaMem(MI, Op);
127128 }
128129
295295 unsigned RegOp = IsStore ? 0 : 5;
296296 unsigned AddrOp = AddrBase + 3;
297297 assert(Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() &&
298 Inst.getOperand(AddrBase + 0).isReg() && // base
299 Inst.getOperand(AddrBase + 1).isImm() && // scale
300 Inst.getOperand(AddrBase + 2).isReg() && // index register
301 (Inst.getOperand(AddrOp).isExpr() || // address
302 Inst.getOperand(AddrOp).isImm())&&
303 Inst.getOperand(AddrBase + 4).isReg() && // segment
298 Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() &&
299 Inst.getOperand(AddrBase + X86::AddrScaleAmt).isImm() &&
300 Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() &&
301 Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() &&
302 (Inst.getOperand(AddrOp).isExpr() ||
303 Inst.getOperand(AddrOp).isImm()) &&
304304 "Unexpected instruction!");
305305
306306 // Check whether the destination register can be fixed.
320320 }
321321
322322 if (Absolute &&
323 (Inst.getOperand(AddrBase + 0).getReg() != 0 ||
324 Inst.getOperand(AddrBase + 2).getReg() != 0 ||
325 Inst.getOperand(AddrBase + 1).getImm() != 1))
323 (Inst.getOperand(AddrBase + X86::AddrBaseReg).getReg() != 0 ||
324 Inst.getOperand(AddrBase + X86::AddrScaleAmt).getImm() != 1 ||
325 Inst.getOperand(AddrBase + X86::AddrIndexReg).getReg() != 0))
326326 return;
327327
328328 // If so, rewrite the instruction.
329329 MCOperand Saved = Inst.getOperand(AddrOp);
330 MCOperand Seg = Inst.getOperand(AddrBase + 4);
330 MCOperand Seg = Inst.getOperand(AddrBase + X86::AddrSegmentReg);
331331 Inst = MCInst();
332332 Inst.setOpcode(Opcode);
333333 Inst.addOperand(Saved);