llvm.org GIT mirror llvm / 7e11c73
Fix PR33028 - '-verify-mahcineinstrs' starts to complain allocatable live-in physical registers on non-entry or non-landing-pad basic blocks. - Refactor the XBEGIN translation to define EAX on a dedicated fallback code path due to XABORT. Add a pseudo instruction to define EAX explicitly to avoid add physical register live-in. Differential Revision: https://reviews.llvm.org/D33168 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303306 91177308-0d34-0410-b5e6-96231b3b80d8 Michael Liao 3 years ago
3 changed file(s) with 45 addition(s) and 17 deletion(s). Raw diff Collapse all Expand all
2470824708 // xbegin sinkMBB
2470924709 //
2471024710 // mainMBB:
24711 // eax = -1
24711 // s0 = -1
24712 //
24713 // fallBB:
24714 // eax = # XABORT_DEF
24715 // s1 = eax
2471224716 //
2471324717 // sinkMBB:
24714 // v = eax
24718 // v = phi(s0/mainBB, s1/fallBB)
2471524719
2471624720 MachineBasicBlock *thisMBB = MBB;
2471724721 MachineFunction *MF = MBB->getParent();
2471824722 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
24723 MachineBasicBlock *fallMBB = MF->CreateMachineBasicBlock(BB);
2471924724 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
2472024725 MF->insert(I, mainMBB);
24726 MF->insert(I, fallMBB);
2472124727 MF->insert(I, sinkMBB);
2472224728
2472324729 // Transfer the remainder of BB and its successor edges to sinkMBB.
2472524731 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
2472624732 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
2472724733
24734 MachineRegisterInfo &MRI = MF->getRegInfo();
24735 unsigned DstReg = MI.getOperand(0).getReg();
24736 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
24737 unsigned mainDstReg = MRI.createVirtualRegister(RC);
24738 unsigned fallDstReg = MRI.createVirtualRegister(RC);
24739
2472824740 // thisMBB:
24729 // xbegin sinkMBB
24741 // xbegin fallMBB
2473024742 // # fallthrough to mainMBB
24731 // # abortion to sinkMBB
24732 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(sinkMBB);
24743 // # abortion to fallMBB
24744 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(fallMBB);
2473324745 thisMBB->addSuccessor(mainMBB);
24734 thisMBB->addSuccessor(sinkMBB);
24746 thisMBB->addSuccessor(fallMBB);
2473524747
2473624748 // mainMBB:
24737 // EAX = -1
24738 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), X86::EAX).addImm(-1);
24749 // mainDstReg := -1
24750 BuildMI(mainMBB, DL, TII->get(X86::MOV32ri), mainDstReg).addImm(-1);
24751 BuildMI(mainMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
2473924752 mainMBB->addSuccessor(sinkMBB);
2474024753
24754 // fallMBB:
24755 // ; pseudo instruction to model hardware's definition from XABORT
24756 // EAX := XABORT_DEF
24757 // fallDstReg := EAX
24758 BuildMI(fallMBB, DL, TII->get(X86::XABORT_DEF));
24759 BuildMI(fallMBB, DL, TII->get(TargetOpcode::COPY), fallDstReg)
24760 .addReg(X86::EAX);
24761 fallMBB->addSuccessor(sinkMBB);
24762
2474124763 // sinkMBB:
24742 // EAX is live into the sinkMBB
24743 sinkMBB->addLiveIn(X86::EAX);
24744 BuildMI(*sinkMBB, sinkMBB->begin(), DL, TII->get(TargetOpcode::COPY),
24745 MI.getOperand(0).getReg())
24746 .addReg(X86::EAX);
24764 // DstReg := phi(mainDstReg/mainBB, fallDstReg/fallBB)
24765 BuildMI(*sinkMBB, sinkMBB->begin(), DL, TII->get(X86::PHI), DstReg)
24766 .addReg(mainDstReg).addMBB(mainMBB)
24767 .addReg(fallDstReg).addMBB(fallMBB);
2474724768
2474824769 MI.eraseFromParent();
2474924770 return sinkMBB;
2929 "xbegin\t$dst", []>, OpSize32;
3030 }
3131
32 // Psuedo instruction to fake the definition of EAX on the fallback code path.
33 let isPseudo = 1, Defs = [EAX] in {
34 def XABORT_DEF : I<0, Pseudo, (outs), (ins), "# XABORT DEF", []>;
35 }
36
3237 def XEND : I<0x01, MRM_D5, (outs), (ins),
3338 "xend", [(int_x86_xend)]>, TB, Requires<[HasRTM]>;
3439
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+rtm | FileCheck %s --check-prefix=X86
2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+rtm | FileCheck %s --check-prefix=X64
1 ; RUN: llc -verify-machineinstrs < %s -mtriple=i686-unknown-unknown -mattr=+rtm | FileCheck %s --check-prefix=X86
2 ; RUN: llc -verify-machineinstrs < %s -mtriple=x86_64-unknown-unknown -mattr=+rtm | FileCheck %s --check-prefix=X64
33
44 declare i32 @llvm.x86.xbegin() nounwind
55 declare void @llvm.x86.xend() nounwind
1212 ; X86-NEXT: xbegin .LBB0_2
1313 ; X86-NEXT: # BB#1: # %entry
1414 ; X86-NEXT: movl $-1, %eax
15 ; X86-NEXT: .LBB0_2: # %entry
15 ; X86: .LBB0_2: # %entry
16 ; X86-NEXT: # XABORT DEF
1617 ; X86-NEXT: retl
1718 ;
1819 ; X64-LABEL: test_xbegin:
2021 ; X64-NEXT: xbegin .LBB0_2
2122 ; X64-NEXT: # BB#1: # %entry
2223 ; X64-NEXT: movl $-1, %eax
23 ; X64-NEXT: .LBB0_2: # %entry
24 ; X64: .LBB0_2: # %entry
25 ; X64-NEXT: # XABORT DEF
2426 ; X64-NEXT: retq
2527 entry:
2628 %0 = tail call i32 @llvm.x86.xbegin() nounwind