llvm.org GIT mirror llvm / 7e07b30
new testcases for -enable-tail-merge default handling git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37287 91177308-0d34-0410-b5e6-96231b3b80d8 Dale Johannesen 12 years ago
2 changed file(s) with 136 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
0 ; RUN: llvm-as < %s | llc -march=arm | grep bl.*baz | wc -l | grep 1
1 ; RUN: llvm-as < %s | llc -march=arm | grep bl.*quux | wc -l | grep 1
2 ; RUN: llvm-as < %s | llc -march=arm -enable-tail-merge=0 | grep bl.*baz | wc -l | grep 2
3 ; RUN: llvm-as < %s | llc -march=arm -enable-tail-merge=0 | grep bl.*quux | wc -l | grep 2
4 ; Check that tail merging is the default on ARM, and that -enable-tail-merge=0 works.
5
6 ; ModuleID = 'tail.c'
7 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
8 target triple = "i686-apple-darwin8"
9
10 define i32 @f(i32 %i, i32 %q) {
11 entry:
12 %i_addr = alloca i32 ; [#uses=2]
13 %q_addr = alloca i32 ; [#uses=2]
14 %retval = alloca i32, align 4 ; [#uses=1]
15 "alloca point" = bitcast i32 0 to i32 ; [#uses=0]
16 store i32 %i, i32* %i_addr
17 store i32 %q, i32* %q_addr
18 %tmp = load i32* %i_addr ; [#uses=1]
19 %tmp1 = icmp ne i32 %tmp, 0 ; [#uses=1]
20 %tmp12 = zext i1 %tmp1 to i8 ; [#uses=1]
21 %toBool = icmp ne i8 %tmp12, 0 ; [#uses=1]
22 br i1 %toBool, label %cond_true, label %cond_false
23
24 cond_true: ; preds = %entry
25 %tmp3 = call i32 (...)* @bar( ) ; [#uses=0]
26 %tmp4 = call i32 (...)* @baz( i32 5, i32 6 ) ; [#uses=0]
27 %tmp7 = load i32* %q_addr ; [#uses=1]
28 %tmp8 = icmp ne i32 %tmp7, 0 ; [#uses=1]
29 %tmp89 = zext i1 %tmp8 to i8 ; [#uses=1]
30 %toBool10 = icmp ne i8 %tmp89, 0 ; [#uses=1]
31 br i1 %toBool10, label %cond_true11, label %cond_false15
32
33 cond_false: ; preds = %entry
34 %tmp5 = call i32 (...)* @foo( ) ; [#uses=0]
35 %tmp6 = call i32 (...)* @baz( i32 5, i32 6 ) ; [#uses=0]
36 %tmp27 = load i32* %q_addr ; [#uses=1]
37 %tmp28 = icmp ne i32 %tmp27, 0 ; [#uses=1]
38 %tmp289 = zext i1 %tmp28 to i8 ; [#uses=1]
39 %toBool210 = icmp ne i8 %tmp289, 0 ; [#uses=1]
40 br i1 %toBool210, label %cond_true11, label %cond_false15
41
42 cond_true11: ; preds = %cond_next
43 %tmp13 = call i32 (...)* @foo( ) ; [#uses=0]
44 %tmp14 = call i32 (...)* @quux( i32 3, i32 4 ) ; [#uses=0]
45 br label %cond_next18
46
47 cond_false15: ; preds = %cond_next
48 %tmp16 = call i32 (...)* @bar( ) ; [#uses=0]
49 %tmp17 = call i32 (...)* @quux( i32 3, i32 4 ) ; [#uses=0]
50 br label %cond_next18
51
52 cond_next18: ; preds = %cond_false15, %cond_true11
53 %tmp19 = call i32 (...)* @bar( ) ; [#uses=0]
54 br label %return
55
56 return: ; preds = %cond_next18
57 %retval20 = load i32* %retval ; [#uses=1]
58 ret i32 %retval20
59 }
60
61 declare i32 @bar(...)
62
63 declare i32 @baz(...)
64
65 declare i32 @foo(...)
66
67 declare i32 @quux(...)
0 ; RUN: llvm-as < %s | llc -march=ppc32 | grep bl.*baz | wc -l | grep 2
1 ; RUN: llvm-as < %s | llc -march=ppc32 | grep bl.*quux | wc -l | grep 2
2 ; RUN: llvm-as < %s | llc -march=ppc32 -enable-tail-merge | grep bl.*baz | wc -l | grep 1
3 ; RUN: llvm-as < %s | llc -march=ppc32 -enable-tail-merge=1 | grep bl.*quux | wc -l | grep 1
4 ; Check that tail merging is not the default on ppc, and that -enable-tail-merge works.
5
6 ; ModuleID = 'tail.c'
7 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
8 target triple = "i686-apple-darwin8"
9
10 define i32 @f(i32 %i, i32 %q) {
11 entry:
12 %i_addr = alloca i32 ; [#uses=2]
13 %q_addr = alloca i32 ; [#uses=2]
14 %retval = alloca i32, align 4 ; [#uses=1]
15 "alloca point" = bitcast i32 0 to i32 ; [#uses=0]
16 store i32 %i, i32* %i_addr
17 store i32 %q, i32* %q_addr
18 %tmp = load i32* %i_addr ; [#uses=1]
19 %tmp1 = icmp ne i32 %tmp, 0 ; [#uses=1]
20 %tmp12 = zext i1 %tmp1 to i8 ; [#uses=1]
21 %toBool = icmp ne i8 %tmp12, 0 ; [#uses=1]
22 br i1 %toBool, label %cond_true, label %cond_false
23
24 cond_true: ; preds = %entry
25 %tmp3 = call i32 (...)* @bar( ) ; [#uses=0]
26 %tmp4 = call i32 (...)* @baz( i32 5, i32 6 ) ; [#uses=0]
27 %tmp7 = load i32* %q_addr ; [#uses=1]
28 %tmp8 = icmp ne i32 %tmp7, 0 ; [#uses=1]
29 %tmp89 = zext i1 %tmp8 to i8 ; [#uses=1]
30 %toBool10 = icmp ne i8 %tmp89, 0 ; [#uses=1]
31 br i1 %toBool10, label %cond_true11, label %cond_false15
32
33 cond_false: ; preds = %entry
34 %tmp5 = call i32 (...)* @foo( ) ; [#uses=0]
35 %tmp6 = call i32 (...)* @baz( i32 5, i32 6 ) ; [#uses=0]
36 %tmp27 = load i32* %q_addr ; [#uses=1]
37 %tmp28 = icmp ne i32 %tmp27, 0 ; [#uses=1]
38 %tmp289 = zext i1 %tmp28 to i8 ; [#uses=1]
39 %toBool210 = icmp ne i8 %tmp289, 0 ; [#uses=1]
40 br i1 %toBool210, label %cond_true11, label %cond_false15
41
42 cond_true11: ; preds = %cond_next
43 %tmp13 = call i32 (...)* @foo( ) ; [#uses=0]
44 %tmp14 = call i32 (...)* @quux( i32 3, i32 4 ) ; [#uses=0]
45 br label %cond_next18
46
47 cond_false15: ; preds = %cond_next
48 %tmp16 = call i32 (...)* @bar( ) ; [#uses=0]
49 %tmp17 = call i32 (...)* @quux( i32 3, i32 4 ) ; [#uses=0]
50 br label %cond_next18
51
52 cond_next18: ; preds = %cond_false15, %cond_true11
53 %tmp19 = call i32 (...)* @bar( ) ; [#uses=0]
54 br label %return
55
56 return: ; preds = %cond_next18
57 %retval20 = load i32* %retval ; [#uses=1]
58 ret i32 %retval20
59 }
60
61 declare i32 @bar(...)
62
63 declare i32 @baz(...)
64
65 declare i32 @foo(...)
66
67 declare i32 @quux(...)