llvm.org GIT mirror llvm / 7def14f
Changed the format of DMBsy, DSBsy, and friends from Pseudo to MiscFrm. Added two test cases to arm-tests.txt. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110880 91177308-0d34-0410-b5e6-96231b3b80d8 Johnny Chen 10 years ago
4 changed file(s) with 12 addition(s) and 9 deletion(s). Raw diff Collapse all Expand all
23552355
23562356 // memory barriers protect the atomic sequences
23572357 let hasSideEffects = 1 in {
2358 def DMBsy : AInoP<(outs), (ins), Pseudo, NoItinerary, "dmb", "",
2358 def DMBsy : AInoP<(outs), (ins), MiscFrm, NoItinerary, "dmb", "",
23592359 [(ARMMemBarrier)]>, Requires<[IsARM, HasDB]> {
23602360 let Inst{31-4} = 0xf57ff05;
23612361 // FIXME: add support for options other than a full system DMB
23632363 let Inst{3-0} = 0b1111;
23642364 }
23652365
2366 def DSBsy : AInoP<(outs), (ins), Pseudo, NoItinerary, "dsb", "",
2366 def DSBsy : AInoP<(outs), (ins), MiscFrm, NoItinerary, "dsb", "",
23672367 [(ARMSyncBarrier)]>, Requires<[IsARM, HasDB]> {
23682368 let Inst{31-4} = 0xf57ff04;
23692369 // FIXME: add support for options other than a full system DSB
23712371 let Inst{3-0} = 0b1111;
23722372 }
23732373
2374 def DMB_MCR : AInoP<(outs), (ins GPR:$zero), Pseudo, NoItinerary,
2374 def DMB_MCR : AInoP<(outs), (ins GPR:$zero), MiscFrm, NoItinerary,
23752375 "mcr", "\tp15, 0, $zero, c7, c10, 5",
23762376 [(ARMMemBarrierMCR GPR:$zero)]>,
23772377 Requires<[IsARM, HasV6]> {
23792379 // FIXME: add encoding
23802380 }
23812381
2382 def DSB_MCR : AInoP<(outs), (ins GPR:$zero), Pseudo, NoItinerary,
2382 def DSB_MCR : AInoP<(outs), (ins GPR:$zero), MiscFrm, NoItinerary,
23832383 "mcr", "\tp15, 0, $zero, c7, c10, 4",
23842384 [(ARMSyncBarrierMCR GPR:$zero)]>,
23852385 Requires<[IsARM, HasV6]> {
492492 static bool DisassemblePseudo(MCInst &MI, unsigned Opcode, uint32_t insn,
493493 unsigned short NumOps, unsigned &NumOpsAdded, BO) {
494494
495 if (Opcode == ARM::DMBsy || Opcode == ARM::DSBsy)
496 return true;
497
498495 assert(0 && "Unexpected pseudo instruction!");
499496 return false;
500497 }
16281628 // A8.6.26
16291629 // t2BXJ -> Rn
16301630 //
1631 // Miscellaneous control: t2Int_MemBarrierV7 (and its t2DMB variants),
1632 // t2Int_SyncBarrierV7 (and its t2DSB varianst), t2ISBsy, t2CLREX
1631 // Miscellaneous control: t2DMBsy (and its t2DMB variants),
1632 // t2DSBsy (and its t2DSB varianst), t2ISBsy, t2CLREX
16331633 // -> no operand (except pred-imm pred-ccr for CLREX, memory barrier variants)
16341634 //
16351635 // Hint: t2NOP, t2YIELD, t2WFE, t2WFI, t2SEV
1111 # CHECK: cmn r0, #1
1212 0x01 0x00 0x70 0xe3
1313
14 # CHECK: dmb
15 0x5f 0xf0 0x7f 0xf5
16
1417 # CHECK: dmb nshst
1518 0x56 0xf0 0x7f 0xf5
19
20 # CHECK: dsb
21 0x4f 0xf0 0x7f 0xf5
1622
1723 # CHECK: ldclvc p5, cr15, [r8], #-0
1824 0x00 0xf5 0x78 0x7c