llvm.org GIT mirror llvm / 7de8fd2
[AMDGPU] Added checks for dpp_ctrl value - Report error for invalid dpp_ctrl values. - Changed the way it is reported, now the error will be emitted into asm and will work with release build as well. - Added dpp_ctrl value verifier for codegen. - Added symbolic constants for dpp_ctrl. Differential Revision: https://reviews.llvm.org/D46565 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@331775 91177308-0d34-0410-b5e6-96231b3b80d8 Stanislav Mekhanoshin 1 year, 9 months ago
4 changed file(s) with 99 addition(s) and 36 deletion(s). Raw diff Collapse all Expand all
47094709 //===----------------------------------------------------------------------===//
47104710
47114711 bool AMDGPUOperand::isDPPCtrl() const {
4712 using namespace AMDGPU::DPP;
4713
47124714 bool result = isImm() && getImmTy() == ImmTyDppCtrl && isUInt<9>(getImm());
47134715 if (result) {
47144716 int64_t Imm = getImm();
4715 return ((Imm >= 0x000) && (Imm <= 0x0ff)) ||
4716 ((Imm >= 0x101) && (Imm <= 0x10f)) ||
4717 ((Imm >= 0x111) && (Imm <= 0x11f)) ||
4718 ((Imm >= 0x121) && (Imm <= 0x12f)) ||
4719 (Imm == 0x130) ||
4720 (Imm == 0x134) ||
4721 (Imm == 0x138) ||
4722 (Imm == 0x13c) ||
4723 (Imm == 0x140) ||
4724 (Imm == 0x141) ||
4725 (Imm == 0x142) ||
4726 (Imm == 0x143);
4717 return (Imm >= DppCtrl::QUAD_PERM_FIRST && Imm <= DppCtrl::QUAD_PERM_LAST) ||
4718 (Imm >= DppCtrl::ROW_SHL_FIRST && Imm <= DppCtrl::ROW_SHL_LAST) ||
4719 (Imm >= DppCtrl::ROW_SHR_FIRST && Imm <= DppCtrl::ROW_SHR_LAST) ||
4720 (Imm >= DppCtrl::ROW_ROR_FIRST && Imm <= DppCtrl::ROW_ROR_LAST) ||
4721 (Imm == DppCtrl::WAVE_SHL1) ||
4722 (Imm == DppCtrl::WAVE_ROL1) ||
4723 (Imm == DppCtrl::WAVE_SHR1) ||
4724 (Imm == DppCtrl::WAVE_ROR1) ||
4725 (Imm == DppCtrl::ROW_MIRROR) ||
4726 (Imm == DppCtrl::ROW_HALF_MIRROR) ||
4727 (Imm == DppCtrl::BCAST15) ||
4728 (Imm == DppCtrl::BCAST31);
47274729 }
47284730 return false;
47294731 }
47424744
47434745 OperandMatchResultTy
47444746 AMDGPUAsmParser::parseDPPCtrl(OperandVector &Operands) {
4747 using namespace AMDGPU::DPP;
4748
47454749 SMLoc S = Parser.getTok().getLoc();
47464750 StringRef Prefix;
47474751 int64_t Int;
47534757 }
47544758
47554759 if (Prefix == "row_mirror") {
4756 Int = 0x140;
4760 Int = DppCtrl::ROW_MIRROR;
47574761 Parser.Lex();
47584762 } else if (Prefix == "row_half_mirror") {
4759 Int = 0x141;
4763 Int = DppCtrl::ROW_HALF_MIRROR;
47604764 Parser.Lex();
47614765 } else {
47624766 // Check to prevent parseDPPCtrlOps from eating invalid tokens
48084812 return MatchOperand_ParseFail;
48094813
48104814 if (Prefix == "row_shl" && 1 <= Int && Int <= 15) {
4811 Int |= 0x100;
4815 Int |= DppCtrl::ROW_SHL0;
48124816 } else if (Prefix == "row_shr" && 1 <= Int && Int <= 15) {
4813 Int |= 0x110;
4817 Int |= DppCtrl::ROW_SHR0;
48144818 } else if (Prefix == "row_ror" && 1 <= Int && Int <= 15) {
4815 Int |= 0x120;
4819 Int |= DppCtrl::ROW_ROR0;
48164820 } else if (Prefix == "wave_shl" && 1 == Int) {
4817 Int = 0x130;
4821 Int = DppCtrl::WAVE_SHL1;
48184822 } else if (Prefix == "wave_rol" && 1 == Int) {
4819 Int = 0x134;
4823 Int = DppCtrl::WAVE_ROL1;
48204824 } else if (Prefix == "wave_shr" && 1 == Int) {
4821 Int = 0x138;
4825 Int = DppCtrl::WAVE_SHR1;
48224826 } else if (Prefix == "wave_ror" && 1 == Int) {
4823 Int = 0x13C;
4827 Int = DppCtrl::WAVE_ROR1;
48244828 } else if (Prefix == "row_bcast") {
48254829 if (Int == 15) {
4826 Int = 0x142;
4830 Int = DppCtrl::BCAST15;
48274831 } else if (Int == 31) {
4828 Int = 0x143;
4832 Int = DppCtrl::BCAST31;
48294833 } else {
48304834 return MatchOperand_ParseFail;
48314835 }
630630 void AMDGPUInstPrinter::printDPPCtrl(const MCInst *MI, unsigned OpNo,
631631 const MCSubtargetInfo &STI,
632632 raw_ostream &O) {
633 using namespace AMDGPU::DPP;
634
633635 unsigned Imm = MI->getOperand(OpNo).getImm();
634 if (Imm <= 0x0ff) {
636 if (Imm <= DppCtrl::QUAD_PERM_LAST) {
635637 O << " quad_perm:[";
636638 O << formatDec(Imm & 0x3) << ',';
637639 O << formatDec((Imm & 0xc) >> 2) << ',';
638640 O << formatDec((Imm & 0x30) >> 4) << ',';
639641 O << formatDec((Imm & 0xc0) >> 6) << ']';
640 } else if ((Imm >= 0x101) && (Imm <= 0x10f)) {
642 } else if ((Imm >= DppCtrl::ROW_SHL_FIRST) &&
643 (Imm <= DppCtrl::ROW_SHL_LAST)) {
641644 O << " row_shl:";
642645 printU4ImmDecOperand(MI, OpNo, O);
643 } else if ((Imm >= 0x111) && (Imm <= 0x11f)) {
646 } else if ((Imm >= DppCtrl::ROW_SHR_FIRST) &&
647 (Imm <= DppCtrl::ROW_SHR_LAST)) {
644648 O << " row_shr:";
645649 printU4ImmDecOperand(MI, OpNo, O);
646 } else if ((Imm >= 0x121) && (Imm <= 0x12f)) {
650 } else if ((Imm >= DppCtrl::ROW_ROR_FIRST) &&
651 (Imm <= DppCtrl::ROW_ROR_LAST)) {
647652 O << " row_ror:";
648653 printU4ImmDecOperand(MI, OpNo, O);
649 } else if (Imm == 0x130) {
654 } else if (Imm == DppCtrl::WAVE_SHL1) {
650655 O << " wave_shl:1";
651 } else if (Imm == 0x134) {
656 } else if (Imm == DppCtrl::WAVE_ROL1) {
652657 O << " wave_rol:1";
653 } else if (Imm == 0x138) {
658 } else if (Imm == DppCtrl::WAVE_SHR1) {
654659 O << " wave_shr:1";
655 } else if (Imm == 0x13c) {
660 } else if (Imm == DppCtrl::WAVE_ROR1) {
656661 O << " wave_ror:1";
657 } else if (Imm == 0x140) {
662 } else if (Imm == DppCtrl::ROW_MIRROR) {
658663 O << " row_mirror";
659 } else if (Imm == 0x141) {
664 } else if (Imm == DppCtrl::ROW_HALF_MIRROR) {
660665 O << " row_half_mirror";
661 } else if (Imm == 0x142) {
666 } else if (Imm == DppCtrl::BCAST15) {
662667 O << " row_bcast:15";
663 } else if (Imm == 0x143) {
668 } else if (Imm == DppCtrl::BCAST31) {
664669 O << " row_bcast:31";
665670 } else {
666 llvm_unreachable("Invalid dpp_ctrl value");
671 O << " /* Invalid dpp_ctrl value */";
667672 }
668673 }
669674
384384 };
385385
386386 } // namespace SDWA
387
388 namespace DPP {
389
390 enum DppCtrl {
391 QUAD_PERM_FIRST = 0,
392 QUAD_PERM_LAST = 0xFF,
393 DPP_UNUSED1 = 0x100,
394 ROW_SHL0 = 0x100,
395 ROW_SHL_FIRST = 0x101,
396 ROW_SHL_LAST = 0x10F,
397 DPP_UNUSED2 = 0x110,
398 ROW_SHR0 = 0x110,
399 ROW_SHR_FIRST = 0x111,
400 ROW_SHR_LAST = 0x11F,
401 DPP_UNUSED3 = 0x120,
402 ROW_ROR0 = 0x120,
403 ROW_ROR_FIRST = 0x121,
404 ROW_ROR_LAST = 0x12F,
405 WAVE_SHL1 = 0x130,
406 DPP_UNUSED4_FIRST = 0x131,
407 DPP_UNUSED4_LAST = 0x133,
408 WAVE_ROL1 = 0x134,
409 DPP_UNUSED5_FIRST = 0x135,
410 DPP_UNUSED5_LAST = 0x137,
411 WAVE_SHR1 = 0x138,
412 DPP_UNUSED6_FIRST = 0x139,
413 DPP_UNUSED6_LAST = 0x13B,
414 WAVE_ROR1 = 0x13C,
415 DPP_UNUSED7_FIRST = 0x13D,
416 DPP_UNUSED7_LAST = 0x13F,
417 ROW_MIRROR = 0x140,
418 ROW_HALF_MIRROR = 0x141,
419 BCAST15 = 0x142,
420 BCAST31 = 0x143,
421 DPP_LAST = BCAST31
422 };
423
424 } // namespace DPP
387425 } // namespace AMDGPU
388426
389427 #define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028
28642864 const MachineOperand *Offset = getNamedOperand(MI, AMDGPU::OpName::offset);
28652865 if (Offset->getImm() != 0) {
28662866 ErrInfo = "subtarget does not support offsets in flat instructions";
2867 return false;
2868 }
2869 }
2870
2871 const MachineOperand *DppCt = getNamedOperand(MI, AMDGPU::OpName::dpp_ctrl);
2872 if (DppCt) {
2873 using namespace AMDGPU::DPP;
2874
2875 unsigned DC = DppCt->getImm();
2876 if (DC == DppCtrl::DPP_UNUSED1 || DC == DppCtrl::DPP_UNUSED2 ||
2877 DC == DppCtrl::DPP_UNUSED3 || DC > DppCtrl::DPP_LAST ||
2878 (DC >= DppCtrl::DPP_UNUSED4_FIRST && DC <= DppCtrl::DPP_UNUSED4_LAST) ||
2879 (DC >= DppCtrl::DPP_UNUSED5_FIRST && DC <= DppCtrl::DPP_UNUSED5_LAST) ||
2880 (DC >= DppCtrl::DPP_UNUSED6_FIRST && DC <= DppCtrl::DPP_UNUSED6_LAST) ||
2881 (DC >= DppCtrl::DPP_UNUSED7_FIRST && DC <= DppCtrl::DPP_UNUSED7_LAST)) {
2882 ErrInfo = "Invalid dpp_ctrl value";
28672883 return false;
28682884 }
28692885 }