llvm.org GIT mirror llvm / 7dc79e5
Support/ELF: Add AMDGPU relocation definitions to match documentation Reviewers: arsenm, kzhuravl, rafael Subscribers: llvm-commits, kzhuravl Differential Revision: http://reviews.llvm.org/D21443 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273066 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 4 years ago
5 changed file(s) with 91 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
614614 #include "ELFRelocs/WebAssembly.def"
615615 };
616616
617 // ELF Relocation types for AMDGPU
618 enum {
619 #include "ELFRelocs/AMDGPU.def"
620 };
621
617622 #undef ELF_RELOC
618623
619624 // Section header.
0 #ifndef ELF_RELOC
1 #error "ELF_RELOC must be defined"
2 #endif
3
4 ELF_RELOC(R_AMDGPU_NONE, 0)
5 ELF_RELOC(R_AMDGPU_ABS32_LO, 1)
6 ELF_RELOC(R_AMDGPU_ABS32_HI, 2)
7 ELF_RELOC(R_AMDGPU_ABS64, 3)
8 ELF_RELOC(R_AMDGPU_REL32, 4)
9 ELF_RELOC(R_AMDGPU_REL64, 5)
10 ELF_RELOC(R_AMDGPU_ABS32, 6)
104104 break;
105105 }
106106 break;
107 case ELF::EM_AMDGPU:
108 switch (Type) {
109 #include "llvm/Support/ELFRelocs/AMDGPU.def"
110 default:
111 break;
112 }
113 break;
107114 default:
108115 break;
109116 }
530530 case ELF::EM_LANAI:
531531 #include "llvm/Support/ELFRelocs/Lanai.def"
532532 break;
533 case ELF::EM_AMDGPU:
534 #include "llvm/Support/ELFRelocs/AMDGPU.def"
535 break;
533536 default:
534537 llvm_unreachable("Unsupported architecture");
535538 }
0 # RUN: yaml2obj -format=elf %s > %t
1 # RUN: llvm-readobj -r %t | FileCheck %s
2
3 # CHECK: Relocations [
4 # CHECK: Section (2) .rela.text {
5 # CHECK: 0x0 R_AMDGPU_NONE main 0x0
6 # CHECK: 0x8 R_AMDGPU_ABS32_LO - 0x0
7 # CHECK: 0x10 R_AMDGPU_ABS32_HI - 0x0
8 # CHECK: 0x18 R_AMDGPU_ABS64 - 0x0
9 # CHECK: 0x20 R_AMDGPU_REL32 - 0x0
10 # CHECK: 0x28 R_AMDGPU_REL64 - 0x0
11 # CHECK: 0x30 R_AMDGPU_ABS32 - 0x0
12 # CHECK: }
13 # CHECK: ]
14
15 FileHeader:
16 Class: ELFCLASS64
17 Data: ELFDATA2LSB
18 Type: ET_REL
19 Machine: EM_AMDGPU
20 Sections:
21 - Type: SHT_PROGBITS
22 Name: .text
23 Flags: [ SHF_ALLOC, SHF_EXECINSTR ]
24 AddressAlign: 0x08
25 Content: 0000000000000000
26 - Type: SHT_RELA
27 Name: .rela.text
28 Link: .symtab
29 Info: .text
30 AddressAlign: 0x08
31 Relocations:
32 - Offset: 0x0
33 Symbol: main
34 Type: R_AMDGPU_NONE
35 - Offset: 0x8
36 Symbol: a
37 Type: R_AMDGPU_ABS32_LO
38 - Offset: 0x10
39 Symbol: b
40 Type: R_AMDGPU_ABS32_HI
41 - Offset: 0x18
42 Symbol: c
43 Type: R_AMDGPU_ABS64
44 - Offset: 0x20
45 Symbol: d
46 Type: R_AMDGPU_REL32
47 - Offset: 0x28
48 Symbol: e
49 Type: R_AMDGPU_REL64
50 - Offset: 0x30
51 Symbol: f
52 Type: R_AMDGPU_ABS32
53
54 Symbols:
55 Local:
56 - Name: .text
57 Type: STT_SECTION
58 Section: .text
59
60 Global:
61 - Name: main
62 Type: STT_FUNC
63 Section: .text
64 Size: 0x08