llvm.org GIT mirror llvm / 7dc3d5f
[NFC] fix trivial typos in comments "the the" -> "the", "we we" -> "we", etc git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330006 91177308-0d34-0410-b5e6-96231b3b80d8 Hiroshi Inoue 2 years ago
9 changed file(s) with 9 addition(s) and 9 deletion(s). Raw diff Collapse all Expand all
5353
5454 /// Register cleanup handler, which is used when the recovery context is
5555 /// finished.
56 /// The recovery context owns the the handler.
56 /// The recovery context owns the handler.
5757 void registerCleanup(CrashRecoveryContextCleanup *cleanup);
5858
5959 void unregisterCleanup(CrashRecoveryContextCleanup *cleanup);
5959 /// * 1 for each of the remaining characters.
6060 int columnWidthUTF8(StringRef Text);
6161
62 /// Fold input unicode character according the the Simple unicode case folding
62 /// Fold input unicode character according the Simple unicode case folding
6363 /// rules.
6464 int foldCharSimple(int C);
6565
19901990 if (!NewSet.empty())
19911991 NodeSets.push_back(NewSet);
19921992
1993 // Create new nodes sets with the connected nodes any any remaining node that
1993 // Create new nodes sets with the connected nodes any remaining node that
19941994 // has no predecessor.
19951995 for (unsigned i = 0; i < SUnits.size(); ++i) {
19961996 SUnit *SU = &SUnits[i];
41874187
41884188 DAGCombinerInfo DCI(DAG, AfterLegalizeVectorOps, true, nullptr);
41894189
4190 // Make sure we we do any optimizations that will make it easier to fold
4190 // Make sure we do any optimizations that will make it easier to fold
41914191 // source modifiers before obscuring it with bit operations.
41924192
41934193 // XXX - Why doesn't this get called when vector_shuffle is expanded?
442442 // VCC, e.g. S_AND_B64 (vcc = V_CMP_...), (vcc = V_CMP_...)
443443 //
444444 // So, instead of forcing the instruction to write to VCC, we provide
445 // a hint to the register allocator to use VCC and then we we will run
445 // a hint to the register allocator to use VCC and then we will run
446446 // this pass again after RA and shrink it if it outputs to VCC.
447447 MRI.setRegAllocationHint(MI.getOperand(0).getReg(), 0, AMDGPU::VCC);
448448 continue;
521521 // operands, the following check on the kill flag would suffice.
522522 // if(!jmpInstr->getOperand(0).isKill()) break;
523523
524 // This predicate register is live out out of BB
524 // This predicate register is live out of BB
525525 // this would only work if we can actually use Live
526526 // variable analysis on phy regs - but LLVM does not
527527 // provide LV analysis on phys regs.
706706 void X86FlagsCopyLoweringPass::rewriteCopy(MachineInstr &MI,
707707 MachineOperand &FlagUse,
708708 MachineInstr &CopyDefI) {
709 // Just replace this copy with the the original copy def.
709 // Just replace this copy with the original copy def.
710710 MRI->replaceRegWith(MI.getOperand(0).getReg(),
711711 CopyDefI.getOperand(0).getReg());
712712 MI.eraseFromParent();
11
22
33 ; If computeKnownSignBits (in SelectionDAG) can do a simple
4 ; look-thru for extractelement then we we know that the add will yield a
4 ; look-thru for extractelement then we know that the add will yield a
55 ; non-negative result.
66 define i1 @test1(<4 x i16>* %in) {
77 ; CHECK-LABEL: ! %bb.0:
0 ; RUN: llc < %s -mtriple=i386-linux -mattr=+avx | FileCheck %s
11
2 ; In i386 there are only 8 XMMs (xmm0-xmm7), make sure we we are not creating illegal XMM
2 ; In i386 there are only 8 XMMs (xmm0-xmm7), make sure we are not creating illegal XMM
33 define float @only_xmm0_7(i32 %arg) {
44 top:
55 tail call void asm sideeffect "", "~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{dirflag},~{fpsr},~{flags}"()