llvm.org GIT mirror llvm / 7d88286
[CodeGen] Fix inconsistent declaration parameter name git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@337200 91177308-0d34-0410-b5e6-96231b3b80d8 Fangrui Song 1 year, 10 months ago
74 changed file(s) with 189 addition(s) and 189 deletion(s). Raw diff Collapse all Expand all
337337 /// global value is specified, and if that global has an explicit alignment
338338 /// requested, it will override the alignment request if required for
339339 /// correctness.
340 void EmitAlignment(unsigned NumBits, const GlobalObject *GO = nullptr) const;
340 void EmitAlignment(unsigned NumBits, const GlobalObject *GV = nullptr) const;
341341
342342 /// Lower the specified LLVM Constant to an MCExpr.
343343 virtual const MCExpr *lowerConstant(const Constant *CV);
645645 void EmitXXStructorList(const DataLayout &DL, const Constant *List,
646646 bool isCtor);
647647
648 GCMetadataPrinter *GetOrCreateGCPrinter(GCStrategy &C);
648 GCMetadataPrinter *GetOrCreateGCPrinter(GCStrategy &S);
649649 /// Emit GlobalAlias or GlobalIFunc.
650650 void emitGlobalIndirectSymbol(Module &M, const GlobalIndirectSymbol &GIS);
651651 void setupCodePaddingContext(const MachineBasicBlock &MBB,
5757 /// [...]
5858 ///
5959 /// Returns true if the containing function was modified.
60 bool expandAtomicRMWToCmpXchg(AtomicRMWInst *AI, CreateCmpXchgInstFun Factory);
60 bool expandAtomicRMWToCmpXchg(AtomicRMWInst *AI, CreateCmpXchgInstFun CreateCmpXchg);
6161
6262 } // end namespace llvm
6363
13781378 const TargetLoweringBase *getTLI() const { return TLI; }
13791379
13801380 public:
1381 explicit BasicTTIImpl(const TargetMachine *ST, const Function &F);
1381 explicit BasicTTIImpl(const TargetMachine *TM, const Function &F);
13821382 };
13831383
13841384 } // end namespace llvm
303303 /// CheckReturn - Analyze the return values of a function, returning
304304 /// true if the return can be performed without sret-demotion, and
305305 /// false otherwise.
306 bool CheckReturn(const SmallVectorImpl &ArgsFlags,
306 bool CheckReturn(const SmallVectorImpl &Outs,
307307 CCAssignFn Fn);
308308
309309 /// AnalyzeCallOperands - Analyze the outgoing arguments to a call,
189189 uint64_t getValue() const { return Integer; }
190190 void setValue(uint64_t Val) { Integer = Val; }
191191
192 void EmitValue(const AsmPrinter *AP, dwarf::Form Form) const;
192 void EmitValue(const AsmPrinter *Asm, dwarf::Form Form) const;
193193 unsigned SizeOf(const AsmPrinter *AP, dwarf::Form Form) const;
194194
195195 void print(raw_ostream &O) const;
867867 return dwarf::DW_FORM_block;
868868 }
869869
870 void EmitValue(const AsmPrinter *AP, dwarf::Form Form) const;
870 void EmitValue(const AsmPrinter *Asm, dwarf::Form Form) const;
871871 unsigned SizeOf(const AsmPrinter *AP, dwarf::Form Form) const;
872872
873873 void print(raw_ostream &O) const;
898898 return dwarf::DW_FORM_block;
899899 }
900900
901 void EmitValue(const AsmPrinter *AP, dwarf::Form Form) const;
901 void EmitValue(const AsmPrinter *Asm, dwarf::Form Form) const;
902902 unsigned SizeOf(const AsmPrinter *AP, dwarf::Form Form) const;
903903
904904 void print(raw_ostream &O) const;
279279
280280 /// This is a wrapper around getRegForValue that also takes care of
281281 /// truncating or sign-extending the given getelementptr index value.
282 std::pair getRegForGEPIndex(const Value *V);
282 std::pair getRegForGEPIndex(const Value *Idx);
283283
284284 /// We're checking to see if we can fold \p LI into \p FoldInst. Note
285285 /// that we could have a sequence where multiple LLVM IR instructions are
438438
439439 /// Emit a MachineInstr with a single immediate operand, and a result
440440 /// register in the given register class.
441 unsigned fastEmitInst_i(unsigned MachineInstrOpcode,
441 unsigned fastEmitInst_i(unsigned MachineInstOpcode,
442442 const TargetRegisterClass *RC, uint64_t Imm);
443443
444444 /// Emit a MachineInstr for an extract_subreg from a specified index of
452452
453453 /// Emit an unconditional branch to the given block, unless it is the
454454 /// immediate (fall-through) successor, and update the CFG.
455 void fastEmitBranch(MachineBasicBlock *MBB, const DebugLoc &DL);
455 void fastEmitBranch(MachineBasicBlock *MSucc, const DebugLoc &DbgLoc);
456456
457457 /// Emit an unconditional branch to \p FalseMBB, obtains the branch weight
458458 /// and adds TrueMBB and FalseMBB to the successor list.
507507 CmpInst::Predicate optimizeCmpPredicate(const CmpInst *CI) const;
508508
509509 bool lowerCallTo(const CallInst *CI, MCSymbol *Symbol, unsigned NumArgs);
510 bool lowerCallTo(const CallInst *CI, const char *SymbolName,
510 bool lowerCallTo(const CallInst *CI, const char *SymName,
511511 unsigned NumArgs);
512512 bool lowerCallTo(CallLoweringInfo &CLI);
513513
531531 bool selectGetElementPtr(const User *I);
532532 bool selectStackmap(const CallInst *I);
533533 bool selectPatchpoint(const CallInst *I);
534 bool selectCall(const User *Call);
534 bool selectCall(const User *I);
535535 bool selectIntrinsicCall(const IntrinsicInst *II);
536536 bool selectBitCast(const User *I);
537537 bool selectCast(const User *I, unsigned Opcode);
538 bool selectExtractValue(const User *I);
538 bool selectExtractValue(const User *U);
539539 bool selectInsertValue(const User *I);
540540 bool selectXRayCustomEvent(const CallInst *II);
541541 bool selectXRayTypedEvent(const CallInst *II);
122122 }
123123
124124 template
125 void setArgFlags(ArgInfo &Arg, unsigned OpNum, const DataLayout &DL,
125 void setArgFlags(ArgInfo &Arg, unsigned OpIdx, const DataLayout &DL,
126126 const FuncInfoTy &FuncInfo) const;
127127
128128 /// Invoke Handler::assignArg on each of the given \p Args and then use
130130 ///
131131 /// \return True if everything has succeeded, false otherwise.
132132 bool handleAssignments(MachineIRBuilder &MIRBuilder, ArrayRef Args,
133 ValueHandler &Callback) const;
133 ValueHandler &Handler) const;
134134
135135 public:
136136 CallLowering(const TargetLowering *TLI) : TLI(TLI) {}
209209
210210 /// Translate an LLVM string intrinsic (memcpy, memset, ...).
211211 bool translateMemfunc(const CallInst &CI, MachineIRBuilder &MIRBuilder,
212 unsigned Intrinsic);
212 unsigned ID);
213213
214214 void getStackGuard(unsigned DstReg, MachineIRBuilder &MIRBuilder);
215215
109109 /// the given Type (which implies the number of blocks needed). The generic
110110 /// registers created are appended to Ops, starting at bit 0 of Reg.
111111 void extractParts(unsigned Reg, LLT Ty, int NumParts,
112 SmallVectorImpl &Ops);
112 SmallVectorImpl &VRegs);
113113
114114 MachineRegisterInfo &MRI;
115115 const LegalizerInfo &LI;
9494 return MIB->getOperand(0).getReg();
9595 }
9696
97 void validateBinaryOp(unsigned Dst, unsigned Src0, unsigned Src1);
97 void validateBinaryOp(unsigned Res, unsigned Op0, unsigned Op1);
9898
9999 public:
100100 /// Some constructors for easy use.
423423 /// \pre setBasicBlock or setMI must have been called.
424424 ///
425425 /// \return a MachineInstrBuilder for the newly created instruction.
426 MachineInstrBuilder buildBr(MachineBasicBlock &BB);
426 MachineInstrBuilder buildBr(MachineBasicBlock &Dest);
427427
428428 /// Build and insert G_BRCOND \p Tst, \p Dest
429429 ///
437437 /// depend on bit 0 (for now).
438438 ///
439439 /// \return The newly created instruction.
440 MachineInstrBuilder buildBrCond(unsigned Tst, MachineBasicBlock &BB);
440 MachineInstrBuilder buildBrCond(unsigned Tst, MachineBasicBlock &Dest);
441441
442442 /// Build and insert G_BRINDIRECT \p Tgt
443443 ///
557557 template MachineInstrBuilder buildUndef(DstType &&Res) {
558558 return buildUndef(getDestFromArg(Res));
559559 }
560 MachineInstrBuilder buildUndef(unsigned Dst);
560 MachineInstrBuilder buildUndef(unsigned Res);
561561
562562 /// Build and insert instructions to put \p Ops together at the specified p
563563 /// Indices to form a larger register.
4141
4242 public:
4343 RegisterBank(unsigned ID, const char *Name, unsigned Size,
44 const uint32_t *ContainedRegClasses, unsigned NumRegClasses);
44 const uint32_t *CoveredClasses, unsigned NumRegClasses);
4545
4646 /// Get the identifier of this register bank.
4747 unsigned getID() const { return ID; }
2626 LatencyPriorityQueue *PQ;
2727 explicit latency_sort(LatencyPriorityQueue *pq) : PQ(pq) {}
2828
29 bool operator()(const SUnit* left, const SUnit* right) const;
29 bool operator()(const SUnit* LHS, const SUnit* RHS) const;
3030 };
3131
3232 class LatencyPriorityQueue : public SchedulingPriorityQueue {
9191 // successor nodes that have a single unscheduled predecessor. If so, that
9292 // single predecessor has a higher priority, since scheduling it will make
9393 // the node available.
94 void scheduledNode(SUnit *Node) override;
94 void scheduledNode(SUnit *SU) override;
9595
9696 private:
9797 void AdjustPriorityOfUnscheduledPreds(SUnit *SU);
325325 /// createDeadDef - Make sure the range has a value defined at Def.
326326 /// If one already exists, return it. Otherwise allocate a new value and
327327 /// add liveness for a dead def.
328 VNInfo *createDeadDef(SlotIndex Def, VNInfo::Allocator &VNInfoAllocator);
328 VNInfo *createDeadDef(SlotIndex Def, VNInfo::Allocator &VNIAlloc);
329329
330330 /// Create a def of value @p VNI. Return @p VNI. If there already exists
331331 /// a definition at VNI->def, the value defined there must be @p VNI.
453453 /// overlapsFrom - Return true if the intersection of the two live ranges
454454 /// is not empty. The specified iterator is a hint that we can begin
455455 /// scanning the Other range starting at I.
456 bool overlapsFrom(const LiveRange &Other, const_iterator I) const;
456 bool overlapsFrom(const LiveRange &Other, const_iterator StartPos) const;
457457
458458 /// Returns true if all segments of the @p Other live range are completely
459459 /// covered by this live range.
481481 /// @p Use, return {nullptr, false}. If there is an "undef" before @p Use,
482482 /// return {nullptr, true}.
483483 std::pair extendInBlock(ArrayRef Undefs,
484 SlotIndex StartIdx, SlotIndex Use);
484 SlotIndex StartIdx, SlotIndex Kill);
485485
486486 /// Simplified version of the above "extendInBlock", which assumes that
487487 /// no register lanes are undefined by operands.
790790 /// L00E0 and L0010 and the L000F lane into L0007 and L0008. The Mod
791791 /// function will be applied to the L0010 and L0008 subranges.
792792 void refineSubRanges(BumpPtrAllocator &Allocator, LaneBitmask LaneMask,
793 std::function Mod);
793 std::function Apply);
794794
795795 bool operator<(const LiveInterval& other) const {
796796 const SlotIndex &thisIndex = beginIndex();
153153 unsigned MaxInterferingRegs = std::numeric_limits::max());
154154
155155 // Was this virtual register visited during collectInterferingVRegs?
156 bool isSeenInterference(LiveInterval *VReg) const;
156 bool isSeenInterference(LiveInterval *VirtReg) const;
157157
158158 // Did collectInterferingVRegs collect all interferences?
159159 bool seenAllInterferences() const { return SeenAllInterferences; }
104104 /// Calculate the spill weight to assign to a single instruction.
105105 static float getSpillWeight(bool isDef, bool isUse,
106106 const MachineBlockFrequencyInfo *MBFI,
107 const MachineInstr &Instr);
107 const MachineInstr &MI);
108108
109109 /// Calculate the spill weight to assign to a single instruction.
110110 static float getSpillWeight(bool isDef, bool isUse,
3737 /// this funciton and the parser will use this function to construct a list if
3838 /// it is missing.
3939 void guessSuccessors(const MachineBasicBlock &MBB,
40 SmallVectorImpl &Successors,
40 SmallVectorImpl &Result,
4141 bool &IsFallthrough);
4242
4343 } // end namespace llvm
5757 public:
5858 void addNodeToList(MachineInstr *N);
5959 void removeNodeFromList(MachineInstr *N);
60 void transferNodesFromList(ilist_traits &OldList, instr_iterator First,
60 void transferNodesFromList(ilist_traits &FromList, instr_iterator First,
6161 instr_iterator Last);
6262 void deleteNode(MachineInstr *MI);
6363 };
8080 };
8181
8282 template <> struct ilist_callback_traits {
83 void addNodeToList(MachineBasicBlock* MBB);
84 void removeNodeFromList(MachineBasicBlock* MBB);
83 void addNodeToList(MachineBasicBlock* N);
84 void removeNodeFromList(MachineBasicBlock* N);
8585
8686 template
8787 void transferNodesFromList(ilist_callback_traits &OldList, Iterator, Iterator) {
365365 using VariableDbgInfoMapTy = SmallVector;
366366 VariableDbgInfoMapTy VariableDbgInfos;
367367
368 MachineFunction(const Function &F, const TargetMachine &TM,
368 MachineFunction(const Function &F, const TargetMachine &Target,
369369 const TargetSubtargetInfo &STI, unsigned FunctionNum,
370370 MachineModuleInfo &MMI);
371371 MachineFunction(const MachineFunction &) = delete;
808808 void addCleanup(MachineBasicBlock *LandingPad);
809809
810810 void addSEHCatchHandler(MachineBasicBlock *LandingPad, const Function *Filter,
811 const BlockAddress *RecoverLabel);
811 const BlockAddress *RecoverBA);
812812
813813 void addSEHCleanupHandler(MachineBasicBlock *LandingPad,
814814 const Function *Cleanup);
140140 /// This constructor create a MachineInstr and add the implicit operands.
141141 /// It reserves space for number of operands specified by
142142 /// MCInstrDesc. An explicit DebugLoc is supplied.
143 MachineInstr(MachineFunction &, const MCInstrDesc &MCID, DebugLoc dl,
143 MachineInstr(MachineFunction &, const MCInstrDesc &tid, DebugLoc dl,
144144 bool NoImp = false);
145145
146146 // MachineInstrs are pool-allocated and owned by MachineFunction.
13201320
13211321 /// Erase an operand from an instruction, leaving it with one
13221322 /// fewer operand than it started with.
1323 void RemoveOperand(unsigned i);
1323 void RemoveOperand(unsigned OpNo);
13241324
13251325 /// Add a MachineMemOperand to the machine instruction.
13261326 /// This function should be used only occasionally. The setMemRefs function
183183 /// atomic operations the atomic ordering requirements when store does not
184184 /// occur must also be specified.
185185 MachineMemOperand(MachinePointerInfo PtrInfo, Flags flags, uint64_t s,
186 uint64_t base_alignment,
186 uint64_t a,
187187 const AAMDNodes &AAInfo = AAMDNodes(),
188188 const MDNode *Ranges = nullptr,
189189 SyncScope::ID SSID = SyncScope::System,
5555 /// MachineSSAUpdater constructor. If InsertedPHIs is specified, it will be
5656 /// filled in with all PHI Nodes created by rewriting.
5757 explicit MachineSSAUpdater(MachineFunction &MF,
58 SmallVectorImpl *InsertedPHIs = nullptr);
58 SmallVectorImpl *NewPHI = nullptr);
5959 MachineSSAUpdater(const MachineSSAUpdater &) = delete;
6060 MachineSSAUpdater &operator=(const MachineSSAUpdater &) = delete;
6161 ~MachineSSAUpdater();
3939 splitCodeGen(std::unique_ptr M, ArrayRef OSs,
4040 ArrayRef BCOSs,
4141 const std::function()> &TMFactory,
42 TargetMachine::CodeGenFileType FT = TargetMachine::CGFT_ObjectFile,
42 TargetMachine::CodeGenFileType FileType = TargetMachine::CGFT_ObjectFile,
4343 bool PreserveLocals = false);
4444
4545 } // namespace llvm
126126
127127 /// Find an unused register of the specified register class.
128128 /// Return 0 if none is found.
129 unsigned FindUnusedReg(const TargetRegisterClass *RegClass) const;
129 unsigned FindUnusedReg(const TargetRegisterClass *RC) const;
130130
131131 /// Add a scavenging frame index.
132132 void addScavengingFrameIndex(int FI) {
157157 /// Returns the scavenged register.
158158 /// This is deprecated as it depends on the quality of the kill flags being
159159 /// present; Use scavengeRegisterBackwards() instead!
160 unsigned scavengeRegister(const TargetRegisterClass *RegClass,
160 unsigned scavengeRegister(const TargetRegisterClass *RC,
161161 MachineBasicBlock::iterator I, int SPAdj);
162162 unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj) {
163163 return scavengeRegister(RegClass, MBBI, SPAdj);
217217 /// Spill a register after position \p After and reload it before position
218218 /// \p UseMI.
219219 ScavengedInfo &spill(unsigned Reg, const TargetRegisterClass &RC, int SPAdj,
220 MachineBasicBlock::iterator After,
220 MachineBasicBlock::iterator Before,
221221 MachineBasicBlock::iterator &UseMI);
222222 };
223223
3131 ResourcePriorityQueue *PQ;
3232 explicit resource_sort(ResourcePriorityQueue *pq) : PQ(pq) {}
3333
34 bool operator()(const SUnit* left, const SUnit* right) const;
34 bool operator()(const SUnit* LHS, const SUnit* RHS) const;
3535 };
3636
3737 class ResourcePriorityQueue : public SchedulingPriorityQueue {
120120 void remove(SUnit *SU) override;
121121
122122 /// scheduledNode - Main resource tracking point.
123 void scheduledNode(SUnit *Node) override;
123 void scheduledNode(SUnit *SU) override;
124124 bool isResourceAvailable(SUnit *SU);
125125 void reserveResources(SUnit *SU);
126126
461461 void dump(const ScheduleDAG *G) const;
462462 void dumpAll(const ScheduleDAG *G) const;
463463 raw_ostream &print(raw_ostream &O,
464 const SUnit *N = nullptr,
465 const SUnit *X = nullptr) const;
464 const SUnit *Entry = nullptr,
465 const SUnit *Exit = nullptr) const;
466466 raw_ostream &print(raw_ostream &O, const ScheduleDAG *G) const;
467467
468468 private:
105105 Scoreboard RequiredScoreboard;
106106
107107 public:
108 ScoreboardHazardRecognizer(const InstrItineraryData *ItinData,
108 ScoreboardHazardRecognizer(const InstrItineraryData *II,
109109 const ScheduleDAG *DAG,
110110 const char *ParentDebugType = "");
111111
381381 /// Prepare this SelectionDAG to process code in the given MachineFunction.
382382 void init(MachineFunction &NewMF, OptimizationRemarkEmitter &NewORE,
383383 Pass *PassPtr, const TargetLibraryInfo *LibraryInfo,
384 DivergenceAnalysis * DA);
384 DivergenceAnalysis * Divergence);
385385
386386 void setFunctionLoweringInfo(FunctionLoweringInfo * FuncInfo) {
387387 FLI = FuncInfo;
597597 bool isTarget = false);
598598 SDValue getConstantFP(const APFloat &Val, const SDLoc &DL, EVT VT,
599599 bool isTarget = false);
600 SDValue getConstantFP(const ConstantFP &CF, const SDLoc &DL, EVT VT,
600 SDValue getConstantFP(const ConstantFP &V, const SDLoc &DL, EVT VT,
601601 bool isTarget = false);
602602 SDValue getTargetConstantFP(double Val, const SDLoc &DL, EVT VT) {
603603 return getConstantFP(Val, DL, VT, true);
781781
782782 /// Return the expression required to zero extend the Op
783783 /// value assuming it was the smaller SrcTy value.
784 SDValue getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT SrcTy);
784 SDValue getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT);
785785
786786 /// Return an operation which will any-extend the low lanes of the operand
787787 /// into the specified vector type. For example,
878878 ArrayRef Ops, const SDNodeFlags Flags = SDNodeFlags());
879879 SDValue getNode(unsigned Opcode, const SDLoc &DL, ArrayRef ResultTys,
880880 ArrayRef Ops);
881 SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTs,
881 SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList,
882882 ArrayRef Ops);
883883
884884 // Specialize based on number of operands.
885885 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT);
886 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N,
886 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue Operand,
887887 const SDNodeFlags Flags = SDNodeFlags());
888888 SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, SDValue N1,
889889 SDValue N2, const SDNodeFlags Flags = SDNodeFlags());
897897
898898 // Specialize again based on number of operands for nodes with a VTList
899899 // rather than a single VT.
900 SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTs);
901 SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTs, SDValue N);
902 SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTs, SDValue N1,
900 SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList);
901 SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue N);
902 SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue N1,
903903 SDValue N2);
904 SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTs, SDValue N1,
904 SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue N1,
905905 SDValue N2, SDValue N3);
906 SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTs, SDValue N1,
906 SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue N1,
907907 SDValue N2, SDValue N3, SDValue N4);
908 SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTs, SDValue N1,
908 SDValue getNode(unsigned Opcode, const SDLoc &DL, SDVTList VTList, SDValue N1,
909909 SDValue N2, SDValue N3, SDValue N4, SDValue N5);
910910
911911 /// Compute a TokenFactor to force all the incoming stack arguments to be
10841084 MachineMemOperand *MMO);
10851085 SDValue
10861086 getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr,
1087 MachinePointerInfo PtrInfo, EVT TVT, unsigned Alignment = 0,
1087 MachinePointerInfo PtrInfo, EVT SVT, unsigned Alignment = 0,
10881088 MachineMemOperand::Flags MMOFlags = MachineMemOperand::MONone,
10891089 const AAMDNodes &AAInfo = AAMDNodes());
10901090 SDValue getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val,
1091 SDValue Ptr, EVT TVT, MachineMemOperand *MMO);
1092 SDValue getIndexedStore(SDValue OrigStoe, const SDLoc &dl, SDValue Base,
1091 SDValue Ptr, EVT SVT, MachineMemOperand *MMO);
1092 SDValue getIndexedStore(SDValue OrigStore, const SDLoc &dl, SDValue Base,
10931093 SDValue Offset, ISD::MemIndexedMode AM);
10941094
10951095 /// Returns sum of the base pointer and offset.
11621162 /// specified node to have the specified return type, Target opcode, and
11631163 /// operands. Note that target opcodes are stored as
11641164 /// ~TargetOpcode in the node opcode field. The resultant node is returned.
1165 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT);
1166 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT, SDValue Op1);
1167 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT,
1165 SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT);
1166 SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT, SDValue Op1);
1167 SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT,
11681168 SDValue Op1, SDValue Op2);
1169 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT,
1169 SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT,
11701170 SDValue Op1, SDValue Op2, SDValue Op3);
1171 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT,
1171 SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT,
11721172 ArrayRef Ops);
1173 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT1, EVT VT2);
1174 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT1,
1173 SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2);
1174 SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1,
11751175 EVT VT2, ArrayRef Ops);
1176 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT1,
1176 SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1,
11771177 EVT VT2, EVT VT3, ArrayRef Ops);
11781178 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT1,
11791179 EVT VT2, SDValue Op1);
1180 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, EVT VT1,
1180 SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1,
11811181 EVT VT2, SDValue Op1, SDValue Op2);
1182 SDNode *SelectNodeTo(SDNode *N, unsigned TargetOpc, SDVTList VTs,
1182 SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, SDVTList VTs,
11831183 ArrayRef Ops);
11841184
11851185 /// This *mutates* the specified node to have the specified
12341234 SDValue Operand, SDValue Subreg);
12351235
12361236 /// Get the specified node if it's already available, or else return NULL.
1237 SDNode *getNodeIfExists(unsigned Opcode, SDVTList VTs, ArrayRef Ops,
1237 SDNode *getNodeIfExists(unsigned Opcode, SDVTList VTList, ArrayRef Ops,
12381238 const SDNodeFlags Flags = SDNodeFlags());
12391239
12401240 /// Creates a SDDbgValue node.
12901290 /// to be given new uses. These new uses of From are left in place, and
12911291 /// not automatically transferred to To.
12921292 ///
1293 void ReplaceAllUsesWith(SDValue From, SDValue Op);
1293 void ReplaceAllUsesWith(SDValue From, SDValue To);
12941294 void ReplaceAllUsesWith(SDNode *From, SDNode *To);
12951295 void ReplaceAllUsesWith(SDNode *From, const SDValue *To);
12961296
291291
292292 // Calls to these functions are generated by tblgen.
293293 void Select_INLINEASM(SDNode *N);
294 void Select_READ_REGISTER(SDNode *N);
295 void Select_WRITE_REGISTER(SDNode *N);
294 void Select_READ_REGISTER(SDNode *Op);
295 void Select_WRITE_REGISTER(SDNode *Op);
296296 void Select_UNDEF(SDNode *N);
297297 void CannotYetSelect(SDNode *N);
298298
299299 private:
300300 void DoInstructionSelection();
301 SDNode *MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTs,
301 SDNode *MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
302302 ArrayRef Ops, unsigned EmitNodeInfo);
303303
304304 SDNode *MutateStrictFPToFP(SDNode *Node, unsigned NewOpc);
12451245
12461246 public:
12471247 MemSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTs,
1248 EVT MemoryVT, MachineMemOperand *MMO);
1248 EVT memvt, MachineMemOperand *MMO);
12491249
12501250 bool readMem() const { return MMO->isLoad(); }
12511251 bool writeMem() const { return MMO->isStore(); }
15931593 bool isBitwiseNot(SDValue V);
15941594
15951595 /// Returns the SDNode if it is a constant splat BuildVector or constant int.
1596 ConstantSDNode *isConstOrConstSplat(SDValue V);
1596 ConstantSDNode *isConstOrConstSplat(SDValue N);
15971597
15981598 /// Returns the SDNode if it is a constant splat BuildVector or constant float.
1599 ConstantFPSDNode *isConstOrConstSplatFP(SDValue V);
1599 ConstantFPSDNode *isConstOrConstSplatFP(SDValue N);
16001600
16011601 class GlobalAddressSDNode : public SDNode {
16021602 friend class SelectionDAG;
16071607
16081608 GlobalAddressSDNode(unsigned Opc, unsigned Order, const DebugLoc &DL,
16091609 const GlobalValue *GA, EVT VT, int64_t o,
1610 unsigned char TargetFlags);
1610 unsigned char TF);
16111611
16121612 public:
16131613 const GlobalValue *getGlobal() const { return TheGlobal; }
8080
8181 /// Given a machine instruction descriptor, returns the register
8282 /// class constraint for OpNum, or NULL.
83 const TargetRegisterClass *getRegClass(const MCInstrDesc &TID, unsigned OpNum,
83 const TargetRegisterClass *getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
8484 const TargetRegisterInfo *TRI,
8585 const MachineFunction &MF) const;
8686
908908 /// The new instruction is inserted before MI, and the client is responsible
909909 /// for removing the old instruction.
910910 MachineInstr *foldMemoryOperand(MachineInstr &MI, ArrayRef Ops,
911 int FrameIndex,
911 int FI,
912912 LiveIntervals *LIS = nullptr) const;
913913
914914 /// Same as the previous version except it allows folding of any load and
966966 MachineInstr &Root, MachineCombinerPattern Pattern,
967967 SmallVectorImpl &InsInstrs,
968968 SmallVectorImpl &DelInstrs,
969 DenseMap &InstrIdxForVirtReg) const;
969 DenseMap &InstIdxForVirtReg) const;
970970
971971 /// Attempt to reassociate \P Root and \P Prev according to \P Pattern to
972972 /// reduce critical path length.
28192819 /// results of this function, because simply replacing replacing TLO.Old
28202820 /// with TLO.New will be incorrect when this parameter is true and TLO.Old
28212821 /// has multiple uses.
2822 bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts,
2822 bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedEltMask,
28232823 APInt &KnownUndef, APInt &KnownZero,
28242824 TargetLoweringOpt &TLO, unsigned Depth = 0,
28252825 bool AssumeSingleUse = false) const;
29022902 bool isConstFalseVal(const SDNode *N) const;
29032903
29042904 /// Return if \p N is a True value when extended to \p VT.
2905 bool isExtendedTrueVal(const ConstantSDNode *N, EVT VT, bool Signed) const;
2905 bool isExtendedTrueVal(const ConstantSDNode *N, EVT VT, bool SExt) const;
29062906
29072907 /// Try to simplify a setcc built with the specified operands and cc. If it is
29082908 /// unable to simplify it, return a null SDValue.
36233623 /// bounds the returned pointer is unspecified, but will be within the vector
36243624 /// bounds.
36253625 SDValue getVectorElementPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT,
3626 SDValue Idx) const;
3626 SDValue Index) const;
36273627
36283628 //===--------------------------------------------------------------------===//
36293629 // Instruction Emitting Hooks
4646 /// Emit Obj-C garbage collection and linker options.
4747 void emitModuleMetadata(MCStreamer &Streamer, Module &M) const override;
4848
49 void emitPersonalityValue(MCStreamer &Streamer, const DataLayout &TM,
49 void emitPersonalityValue(MCStreamer &Streamer, const DataLayout &DL,
5050 const MCSymbol *Sym) const override;
5151
5252 /// Given a constant with the SectionKind, return a section that it should be
237237
238238 protected:
239239 TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
240 regclass_iterator RegClassBegin,
241 regclass_iterator RegClassEnd,
240 regclass_iterator RCB,
241 regclass_iterator RCE,
242242 const char *const *SRINames,
243243 const LaneBitmask *SRILaneMasks,
244244 LaneBitmask CoveringLanes,
245 const RegClassInfo *const RSI,
245 const RegClassInfo *const RCIs,
246246 unsigned Mode = 0);
247247 virtual ~TargetRegisterInfo();
248248
11661166 ///
11671167 /// Usage: OS << printReg(Reg, TRI, SubRegIdx) << '\n';
11681168 Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI = nullptr,
1169 unsigned SubRegIdx = 0,
1169 unsigned SubIdx = 0,
11701170 const MachineRegisterInfo *MRI = nullptr);
11711171
11721172 /// Create Printable object to print register units on a \ref raw_ostream.
184184 /// if converter after moving it to TargetSchedModel).
185185 unsigned computeInstrLatency(const MachineInstr *MI,
186186 bool UseDefaultDefLatency = true) const;
187 unsigned computeInstrLatency(const MCInst &MI) const;
187 unsigned computeInstrLatency(const MCInst &Inst) const;
188188 unsigned computeInstrLatency(unsigned Opcode) const;
189189
190190
191191 /// Output dependency latency of a pair of defs of the same register.
192192 ///
193193 /// This is typically one cycle.
194 unsigned computeOutputLatency(const MachineInstr *DefMI, unsigned DefIdx,
194 unsigned computeOutputLatency(const MachineInstr *DefMI, unsigned DefOperIdx,
195195 const MachineInstr *DepMI) const;
196196
197197 /// Compute the reciprocal throughput of the given instruction.
171171
172172 /// create a mapping for the specified virtual register to
173173 /// the specified stack slot
174 void assignVirt2StackSlot(unsigned virtReg, int frameIndex);
174 void assignVirt2StackSlot(unsigned virtReg, int SS);
175175
176176 void print(raw_ostream &OS, const Module* M = nullptr) const override;
177177 void dump() const;
7272 };
7373
7474 // Analyze the IR in the given function to build WasmEHFuncInfo.
75 void calculateWasmEHInfo(const Function *F, WasmEHFuncInfo &FuncInfo);
75 void calculateWasmEHInfo(const Function *F, WasmEHFuncInfo &EHInfo);
7676
7777 } // namespace llvm
7878
304304 class LLVMTargetMachine : public TargetMachine {
305305 protected: // Can only create subclasses.
306306 LLVMTargetMachine(const Target &T, StringRef DataLayoutString,
307 const Triple &TargetTriple, StringRef CPU, StringRef FS,
307 const Triple &TT, StringRef CPU, StringRef FS,
308308 const TargetOptions &Options, Reloc::Model RM,
309309 CodeModel::Model CM, CodeGenOpt::Level OL);
310310
335335 /// fills the MCContext Ctx pointer which can be used to build custom
336336 /// MCStreamer.
337337 bool addPassesToEmitMC(PassManagerBase &PM, MCContext *&Ctx,
338 raw_pwrite_stream &OS,
338 raw_pwrite_stream &Out,
339339 bool DisableVerify = true) override;
340340
341341 /// Returns true if the target is expected to pass all machine verifier
232232 void emitBuckets() const;
233233 void emitStringOffsets() const;
234234 void emitAbbrevs() const;
235 void emitEntry(const DataT &Data) const;
235 void emitEntry(const DataT &Entry) const;
236236 void emitData() const;
237237
238238 public:
224224 using FileToFilepathMapTy = std::map;
225225 FileToFilepathMapTy FileToFilepathMap;
226226
227 StringRef getFullFilepath(const DIFile *S);
227 StringRef getFullFilepath(const DIFile *File);
228228
229229 unsigned maybeRecordFile(const DIFile *F);
230230
385385 void endFunctionImpl(const MachineFunction *) override;
386386
387387 public:
388 CodeViewDebug(AsmPrinter *Asm);
388 CodeViewDebug(AsmPrinter *AP);
389389
390390 void setSymbolSize(const MCSymbol *, uint64_t) override {}
391391
4343 // Helper routines to process parts of a DIE.
4444 private:
4545 /// Adds the parent context of \param Die to the hash.
46 void addParentContext(const DIE &Die);
46 void addParentContext(const DIE &Parent);
4747
4848 /// Adds the attributes of \param Die to the hash.
4949 void addAttributes(const DIE &Die);
216216 DbgVariable *getExistingAbstractVariable(InlinedVariable IV,
217217 const DILocalVariable *&Cleansed);
218218 DbgVariable *getExistingAbstractVariable(InlinedVariable IV);
219 void createAbstractVariable(const DILocalVariable *DV, LexicalScope *Scope);
219 void createAbstractVariable(const DILocalVariable *Var, LexicalScope *Scope);
220220
221221 /// Set the skeleton unit associated with this unit.
222222 void setSkeleton(DwarfCompileUnit &Skel) { Skeleton = &Skel; }
330330
331331 using InlinedVariable = DbgValueHistoryMap::InlinedVariable;
332332
333 void ensureAbstractVariableIsCreated(DwarfCompileUnit &CU, InlinedVariable Var,
333 void ensureAbstractVariableIsCreated(DwarfCompileUnit &CU, InlinedVariable IV,
334334 const MDNode *Scope);
335 void ensureAbstractVariableIsCreatedIfScoped(DwarfCompileUnit &CU, InlinedVariable Var,
335 void ensureAbstractVariableIsCreatedIfScoped(DwarfCompileUnit &CU, InlinedVariable IV,
336336 const MDNode *Scope);
337337
338338 DbgVariable *createConcreteVariable(DwarfCompileUnit &TheCU,
9797 /// corresponds to the MDNode mapped with the subprogram DIE.
9898 DenseMap ContainingTypeMap;
9999
100 DwarfUnit(dwarf::Tag, const DICompileUnit *CU, AsmPrinter *A, DwarfDebug *DW,
100 DwarfUnit(dwarf::Tag, const DICompileUnit *Node, AsmPrinter *A, DwarfDebug *DW,
101101 DwarfFile *DWU);
102102
103103 bool applySubprogramDefinitionAttributes(const DISubprogram *SP, DIE &SPDie);
186186
187187 /// Add a dwarf op address data and value using the form given and an
188188 /// op of either DW_FORM_addr or DW_FORM_GNU_addr_index.
189 void addOpAddress(DIELoc &Die, const MCSymbol *Label);
189 void addOpAddress(DIELoc &Die, const MCSymbol *Sym);
190190
191191 /// Add a label delta attribute data and value.
192192 void addLabelDelta(DIE &Die, dwarf::Attribute Attribute, const MCSymbol *Hi,
202202 void addDIETypeSignature(DIE &Die, uint64_t Signature);
203203
204204 /// Add block data.
205 void addBlock(DIE &Die, dwarf::Attribute Attribute, DIELoc *Block);
205 void addBlock(DIE &Die, dwarf::Attribute Attribute, DIELoc *Loc);
206206
207207 /// Add block data.
208208 void addBlock(DIE &Die, dwarf::Attribute Attribute, DIEBlock *Block);
259259 bool SkipSPAttributes = false);
260260
261261 /// Find existing DIE or create new DIE for the given type.
262 DIE *getOrCreateTypeDIE(const MDNode *N);
262 DIE *getOrCreateTypeDIE(const MDNode *TyNode);
263263
264264 /// Get context owner's DIE.
265265 DIE *getOrCreateContextDIE(const DIScope *Context);
341341 private:
342342 void constructTypeDIE(DIE &Buffer, const DIBasicType *BTy);
343343 void constructTypeDIE(DIE &Buffer, const DIDerivedType *DTy);
344 void constructTypeDIE(DIE &Buffer, const DISubroutineType *DTy);
344 void constructTypeDIE(DIE &Buffer, const DISubroutineType *CTy);
345345 void constructSubrangeDIE(DIE &Buffer, const DISubrange *SR, DIE *IndexTy);
346346 void constructArrayTypeDIE(DIE &Buffer, const DICompositeType *CTy);
347347 void constructEnumTypeDIE(DIE &Buffer, const DICompositeType *CTy);
7171
7272 /// Compute the actions table and gather the first action index for each
7373 /// landing pad site.
74 void computeActionsTable(const SmallVectorImpl &LPs,
74 void computeActionsTable(const SmallVectorImpl &LandingPads,
7575 SmallVectorImpl &Actions,
7676 SmallVectorImpl &FirstActions);
7777
8585 /// no entry and must not be contained in the try-range of any entry - they
8686 /// form gaps in the table. Entries must be ordered by try-range address.
8787 void computeCallSiteTable(SmallVectorImpl &CallSites,
88 const SmallVectorImpl &LPs,
88 const SmallVectorImpl &LandingPads,
8989 const SmallVectorImpl &FirstActions);
9090
9191 /// Emit landing pads and actions.
9797 CreateCmpXchgInstFun CreateCmpXchg);
9898
9999 bool expandAtomicCmpXchg(AtomicCmpXchgInst *CI);
100 bool isIdempotentRMW(AtomicRMWInst *AI);
101 bool simplifyIdempotentRMW(AtomicRMWInst *AI);
100 bool isIdempotentRMW(AtomicRMWInst *RMWI);
101 bool simplifyIdempotentRMW(AtomicRMWInst *RMWI);
102102
103103 bool expandAtomicOpToLibcall(Instruction *I, unsigned Size, unsigned Align,
104104 Value *PointerOperand, Value *ValueOperand,
3737
3838 explicit BranchFolder(bool defaultEnableTailMerge,
3939 bool CommonHoist,
40 MBFIWrapper &MBFI,
41 const MachineBranchProbabilityInfo &MBPI,
40 MBFIWrapper &FreqInfo,
41 const MachineBranchProbabilityInfo &ProbInfo,
4242 // Min tail length to merge. Defaults to commandline
4343 // flag. Ignored for optsize.
44 unsigned MinCommonTailLength = 0);
44 unsigned MinTailLength = 0);
4545
4646 /// Perhaps branch folding, tail merging and other CFG optimizations on the
4747 /// given function. Block placement changes the layout and may create new
9595
9696 MachineBasicBlock *splitBlockBeforeInstr(MachineInstr &MI,
9797 MachineBasicBlock *DestBB);
98 void adjustBlockOffsets(MachineBasicBlock &MBB);
98 void adjustBlockOffsets(MachineBasicBlock &Start);
9999 bool isBlockInRange(const MachineInstr &MI, const MachineBasicBlock &BB) const;
100100
101101 bool fixupConditionalBranch(MachineInstr &MI);
320320 bool isPreheader);
321321 bool optimizeBlock(BasicBlock &BB, bool &ModifiedDT);
322322 bool optimizeInst(Instruction *I, bool &ModifiedDT);
323 bool optimizeMemoryInst(Instruction *I, Value *Addr,
324 Type *AccessTy, unsigned AS);
323 bool optimizeMemoryInst(Instruction *MemoryInst, Value *Addr,
324 Type *AccessTy, unsigned AddrSpace);
325325 bool optimizeInlineAsmInst(CallInst *CS);
326326 bool optimizeCallInst(CallInst *CI, bool &ModifiedDT);
327327 bool optimizeExt(Instruction *&I);
328328 bool optimizeExtUses(Instruction *I);
329 bool optimizeLoadExt(LoadInst *I);
329 bool optimizeLoadExt(LoadInst *Load);
330330 bool optimizeSelectInst(SelectInst *SI);
331 bool optimizeShuffleVectorInst(ShuffleVectorInst *SI);
332 bool optimizeSwitchInst(SwitchInst *CI);
331 bool optimizeShuffleVectorInst(ShuffleVectorInst *SVI);
332 bool optimizeSwitchInst(SwitchInst *SI);
333333 bool optimizeExtractElementInst(Instruction *Inst);
334334 bool dupRetToEnableTailCallOpts(BasicBlock *BB);
335335 bool placeDbgValues(Function &F);
26112611
26122612 private:
26132613 bool matchScaledValue(Value *ScaleReg, int64_t Scale, unsigned Depth);
2614 bool matchAddr(Value *V, unsigned Depth);
2615 bool matchOperationAddr(User *Operation, unsigned Opcode, unsigned Depth,
2614 bool matchAddr(Value *Addr, unsigned Depth);
2615 bool matchOperationAddr(User *AddrInst, unsigned Opcode, unsigned Depth,
26162616 bool *MovedAway = nullptr);
26172617 bool isProfitableToFoldIntoAddressingMode(Instruction *I,
26182618 ExtAddrMode &AMBefore,
101101 MemCmpExpansion(CallInst *CI, uint64_t Size,
102102 const TargetTransformInfo::MemCmpExpansionOptions &Options,
103103 unsigned MaxNumLoads, const bool IsUsedForZeroCmp,
104 unsigned NumLoadsPerBlockForZeroCmp, const DataLayout &DL);
104 unsigned MaxLoadsPerBlockForZeroCmp, const DataLayout &TheDataLayout);
105105
106106 unsigned getNumBlocks();
107107 uint64_t getNumLoads() const { return LoadSequence.size(); }
3737 /// directed by the GCStrategy. It also performs automatic root initialization
3838 /// and custom intrinsic lowering.
3939 class LowerIntrinsics : public FunctionPass {
40 bool PerformDefaultLowering(Function &F, GCStrategy &Coll);
40 bool PerformDefaultLowering(Function &F, GCStrategy &S);
4141
4242 public:
4343 static char ID;
6060 const TargetInstrInfo *TII;
6161
6262 void FindSafePoints(MachineFunction &MF);
63 void VisitCallPoint(MachineBasicBlock::iterator MI);
63 void VisitCallPoint(MachineBasicBlock::iterator CI);
6464 MCSymbol *InsertLabel(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
6565 const DebugLoc &DL) const;
6666
251251 BBInfo &TrueBBI, BBInfo &FalseBBI) const;
252252 void AnalyzeBlock(MachineBasicBlock &MBB,
253253 std::vector> &Tokens);
254 bool FeasibilityAnalysis(BBInfo &BBI, SmallVectorImpl &Cond,
254 bool FeasibilityAnalysis(BBInfo &BBI, SmallVectorImpl &Pred,
255255 bool isTriangle = false, bool RevBranch = false,
256256 bool hasCommonTail = false);
257257 void AnalyzeBlocks(MachineFunction &MF,
114114 /// \c canHandle should return true for all instructions in \p
115115 /// Insts.
116116 DependenceResult computeDependence(const MachineInstr *MI,
117 ArrayRef Insts);
117 ArrayRef Block);
118118
119119 /// Represents one null check that can be made implicit.
120120 class NullCheck {
306306
307307 /// splitRegister - Replace OldReg ranges with NewRegs ranges where NewRegs is
308308 /// live. Returns true if any changes were made.
309 bool splitRegister(unsigned OldLocNo, ArrayRef NewRegs,
309 bool splitRegister(unsigned OldReg, ArrayRef NewRegs,
310310 LiveIntervals &LIS);
311311
312312 /// rewriteLocations - Rewrite virtual register locations according to the
146146 ///
147147 /// PhysReg, when set, is used to verify live-in lists on basic blocks.
148148 bool findReachingDefs(LiveRange &LR, MachineBasicBlock &UseMBB,
149 SlotIndex Kill, unsigned PhysReg,
149 SlotIndex Use, unsigned PhysReg,
150150 ArrayRef Undefs);
151151
152152 /// updateSSA - Compute the values that will be live in to all requested
202202 bool parseRegisterOperand(MachineOperand &Dest,
203203 Optional &TiedDefIdx, bool IsDef = false);
204204 bool parseImmediateOperand(MachineOperand &Dest);
205 bool parseIRConstant(StringRef::iterator Loc, StringRef Source,
205 bool parseIRConstant(StringRef::iterator Loc, StringRef StringValue,
206206 const Constant *&C);
207207 bool parseIRConstant(StringRef::iterator Loc, const Constant *&C);
208208 bool parseLowLevelType(StringRef::iterator Loc, LLT &Ty);
221221 bool parseJumpTableIndexOperand(MachineOperand &Dest);
222222 bool parseExternalSymbolOperand(MachineOperand &Dest);
223223 bool parseMDNode(MDNode *&Node);
224 bool parseDIExpression(MDNode *&Node);
224 bool parseDIExpression(MDNode *&Expr);
225225 bool parseMetadataOperand(MachineOperand &Dest);
226226 bool parseCFIOffset(int &Offset);
227227 bool parseCFIRegister(unsigned &Reg);
6666 const Name2RegClassMap &Names2RegClasses,
6767 const Name2RegBankMap &Names2RegBanks);
6868
69 VRegInfo &getVRegInfo(unsigned VReg);
69 VRegInfo &getVRegInfo(unsigned Num);
7070 VRegInfo &getVRegInfoNamed(StringRef RegName);
7171 };
7272
424424 MachineBasicBlock *BB, MachineBasicBlock *LPred,
425425 BlockChain &Chain, BlockFilterSet *BlockFilter,
426426 MachineFunction::iterator &PrevUnplacedBlockIt,
427 bool &DuplicatedToPred);
427 bool &DuplicatedToLPred);
428428 bool hasBetterLayoutPredecessor(
429429 const MachineBasicBlock *BB, const MachineBasicBlock *Succ,
430430 const BlockChain &SuccChain, BranchProbability SuccProb,
473473 /// fallthroughs.
474474 bool isProfitableToTailDup(
475475 const MachineBasicBlock *BB, const MachineBasicBlock *Succ,
476 BranchProbability AdjustedSumProb,
476 BranchProbability QProb,
477477 const BlockChain &Chain, const BlockFilterSet *BlockFilter);
478478
479479 /// Check for a trellis layout.
215215 DenseMap &OpenChildren,
216216 DenseMap &ParentMap);
217217
218 void HoistOutOfLoop(MachineDomTreeNode *LoopHeaderNode);
218 void HoistOutOfLoop(MachineDomTreeNode *HeaderN);
219219
220220 void HoistRegion(MachineDomTreeNode *N, bool IsHeader);
221221
433433 unsigned InstStageNum,
434434 SMSchedule &Schedule);
435435 void updateInstruction(MachineInstr *NewMI, bool LastDef,
436 unsigned CurStageNum, unsigned InstStageNum,
436 unsigned CurStageNum, unsigned InstrStageNum,
437437 SMSchedule &Schedule, ValueMapTy *VRMap);
438438 MachineInstr *findDefInLoop(unsigned Reg);
439439 unsigned getPrevMapVal(unsigned StageNum, unsigned PhiStage, unsigned LoopVal,
709709 void orderDependence(SwingSchedulerDAG *SSD, SUnit *SU,
710710 std::deque &Insts);
711711 bool isLoopCarried(SwingSchedulerDAG *SSD, MachineInstr &Phi);
712 bool isLoopCarriedDefOfUse(SwingSchedulerDAG *SSD, MachineInstr *Inst,
712 bool isLoopCarriedDefOfUse(SwingSchedulerDAG *SSD, MachineInstr *Def,
713713 MachineOperand &MO);
714714 void print(raw_ostream &os) const;
715715 void dump() const;
250250 void report_context_liverange(const LiveRange &LR) const;
251251 void report_context_lanemask(LaneBitmask LaneMask) const;
252252 void report_context_vreg(unsigned VReg) const;
253 void report_context_vreg_regunit(unsigned VRegOrRegUnit) const;
253 void report_context_vreg_regunit(unsigned VRegOrUnit) const;
254254
255255 void verifyInlineAsm(const MachineInstr *MI);
256256
257257 void checkLiveness(const MachineOperand *MO, unsigned MONum);
258258 void checkLivenessAtUse(const MachineOperand *MO, unsigned MONum,
259 SlotIndex UseIdx, const LiveRange &LR, unsigned Reg,
259 SlotIndex UseIdx, const LiveRange &LR, unsigned VRegOrUnit,
260260 LaneBitmask LaneMask = LaneBitmask::getNone());
261261 void checkLivenessAtDef(const MachineOperand *MO, unsigned MONum,
262 SlotIndex DefIdx, const LiveRange &LR, unsigned Reg,
262 SlotIndex DefIdx, const LiveRange &LR, unsigned VRegOrUnit,
263263 LaneBitmask LaneMask = LaneBitmask::getNone());
264264
265265 void markReachable(const MachineBasicBlock *MBB);
4444 initializeOptimizePHIsPass(*PassRegistry::getPassRegistry());
4545 }
4646
47 bool runOnMachineFunction(MachineFunction &MF) override;
47 bool runOnMachineFunction(MachineFunction &Fn) override;
4848
4949 void getAnalysisUsage(AnalysisUsage &AU) const override {
5050 AU.setPreservesCFG();
7474 initializePHIEliminationPass(*PassRegistry::getPassRegistry());
7575 }
7676
77 bool runOnMachineFunction(MachineFunction &Fn) override;
77 bool runOnMachineFunction(MachineFunction &MF) override;
7878 void getAnalysisUsage(AnalysisUsage &AU) const override;
7979
8080 private:
9090 /// register which is used in a PHI node. We map that to the BB the
9191 /// vreg is coming from. This is used later to determine when the vreg
9292 /// is killed in the BB.
93 void analyzePHINodes(const MachineFunction& Fn);
93 void analyzePHINodes(const MachineFunction& MF);
9494
9595 /// Split critical edges where necessary for good coalescer performance.
9696 bool SplitPHIEdges(MachineFunction &MF, MachineBasicBlock &MBB,
4343
4444 void getAnalysisUsage(AnalysisUsage &au) const override;
4545
46 bool runOnMachineFunction(MachineFunction &fn) override;
46 bool runOnMachineFunction(MachineFunction &MF) override;
4747 };
4848 } // end anonymous namespace
4949
178178 }
179179
180180 private:
181 bool runOnMachineFunction(MachineFunction &Fn) override;
181 bool runOnMachineFunction(MachineFunction &MF) override;
182182 void allocateBasicBlock(MachineBasicBlock &MBB);
183183 void handleThroughOperands(MachineInstr &MI,
184184 SmallVectorImpl &VirtDead);
205205 return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg));
206206 }
207207
208 LiveRegMap::iterator assignVirtToPhysReg(unsigned VReg, MCPhysReg PhysReg);
208 LiveRegMap::iterator assignVirtToPhysReg(unsigned VirtReg, MCPhysReg PhysReg);
209209 LiveRegMap::iterator allocVirtReg(MachineInstr &MI, LiveRegMap::iterator,
210210 unsigned Hint);
211211 LiveRegMap::iterator defineVirtReg(MachineInstr &MI, unsigned OpNum,
461461 bool calcCompactRegion(GlobalSplitCandidate&);
462462 void splitAroundRegion(LiveRangeEdit&, ArrayRef);
463463 void calcGapWeights(unsigned, SmallVectorImpl&);
464 unsigned canReassign(LiveInterval &VirtReg, unsigned PhysReg);
464 unsigned canReassign(LiveInterval &VirtReg, unsigned PrevReg);
465465 bool shouldEvict(LiveInterval &A, bool, LiveInterval &B, bool);
466466 bool canEvictInterference(LiveInterval&, unsigned, bool, EvictionCost&);
467467 bool canEvictInterferenceInRange(LiveInterval &VirtReg, unsigned PhysReg,
161161 /// was successfully coalesced away. If it is not currently possible to
162162 /// coalesce this interval, but it may be possible if other things get
163163 /// coalesced, then it returns true by reference in 'Again'.
164 bool joinCopy(MachineInstr *TheCopy, bool &Again);
164 bool joinCopy(MachineInstr *CopyMI, bool &Again);
165165
166166 /// Attempt to join these two intervals. On failure, this
167167 /// returns false. The output "SrcInt" will not have been modified, so we
21252125 /// Find the ultimate value that VNI was copied from.
21262126 std::pair followCopyChain(const VNInfo *VNI) const;
21272127
2128 bool valuesIdentical(VNInfo *Val0, VNInfo *Val1, const JoinVals &Other) const;
2128 bool valuesIdentical(VNInfo *Value0, VNInfo *Value1, const JoinVals &Other) const;
21292129
21302130 /// Analyze ValNo in this live range, and set all fields of Vals[ValNo].
21312131 /// Return a conflict resolution when possible, but leave the hard cases as
6060 }
6161
6262
63 std::string getNodeLabel(const SUnit *Node, const ScheduleDAG *Graph);
63 std::string getNodeLabel(const SUnit *SU, const ScheduleDAG *Graph);
6464 static std::string getNodeAttributes(const SUnit *N,
6565 const ScheduleDAG *Graph) {
6666 return "shape=Mrecord";
309309 SDValue visitUMULO(SDNode *N);
310310 SDValue visitIMINMAX(SDNode *N);
311311 SDValue visitAND(SDNode *N);
312 SDValue visitANDLike(SDValue N0, SDValue N1, SDNode *LocReference);
312 SDValue visitANDLike(SDValue N0, SDValue N1, SDNode *N);
313313 SDValue visitOR(SDNode *N);
314 SDValue visitORLike(SDValue N0, SDValue N1, SDNode *LocReference);
314 SDValue visitORLike(SDValue N0, SDValue N1, SDNode *N);
315315 SDValue visitXOR(SDNode *N);
316316 SDValue SimplifyVBinOp(SDNode *N);
317317 SDValue visitSHL(SDNode *N);
391391 SDValue visitFMULForFMADistributiveCombine(SDNode *N);
392392
393393 SDValue XformToShuffleWithZero(SDNode *N);
394 SDValue ReassociateOps(unsigned Opc, const SDLoc &DL, SDValue LHS,
395 SDValue RHS);
394 SDValue ReassociateOps(unsigned Opc, const SDLoc &DL, SDValue N0,
395 SDValue N1);
396396
397397 SDValue visitShiftByConstant(SDNode *N, ConstantSDNode *Amt);
398398
430430 SDValue BuildSDIV(SDNode *N);
431431 SDValue BuildSDIVPow2(SDNode *N);
432432 SDValue BuildUDIV(SDNode *N);
433 SDValue BuildLogBase2(SDValue Op, const SDLoc &DL);
433 SDValue BuildLogBase2(SDValue V, const SDLoc &DL);
434434 SDValue BuildReciprocalEstimate(SDValue Op, SDNodeFlags Flags);
435435 SDValue buildRsqrtEstimate(SDValue Op, SDNodeFlags Flags);
436436 SDValue buildSqrtEstimate(SDValue Op, SDNodeFlags Flags);
437437 SDValue buildSqrtEstimateImpl(SDValue Op, SDNodeFlags Flags, bool Recip);
438 SDValue buildSqrtNROneConst(SDValue Op, SDValue Est, unsigned Iterations,
438 SDValue buildSqrtNROneConst(SDValue Arg, SDValue Est, unsigned Iterations,
439439 SDNodeFlags Flags, bool Reciprocal);
440 SDValue buildSqrtNRTwoConst(SDValue Op, SDValue Est, unsigned Iterations,
440 SDValue buildSqrtNRTwoConst(SDValue Arg, SDValue Est, unsigned Iterations,
441441 SDNodeFlags Flags, bool Reciprocal);
442442 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
443443 bool DemandHighBits = true);
459459 SDValue createBuildVecShuffle(const SDLoc &DL, SDNode *N,
460460 ArrayRef VectorMask, SDValue VecIn1,
461461 SDValue VecIn2, unsigned LeftIdx);
462 SDValue matchVSelectOpSizesWithSetCC(SDNode *N);
462 SDValue matchVSelectOpSizesWithSetCC(SDNode *Cast);
463463
464464 /// Walk up chain skipping non-aliasing memory nodes,
465465 /// looking for aliasing nodes and adding them to the Aliases vector.
518518
519519 /// Used by BackwardsPropagateMask to find suitable loads.
520520 bool SearchForAndLoads(SDNode *N, SmallPtrSetImpl &Loads,
521 SmallPtrSetImpl &NodeWithConsts,
522 ConstantSDNode *Mask, SDNode *&UncombinedNode);
521 SmallPtrSetImpl &NodesWithConsts,
522 ConstantSDNode *Mask, SDNode *&NodeToMask);
523523 /// Attempt to propagate a given AND node back to load leaves so that they
524524 /// can be combined into narrow loads.
525525 bool BackwardsPropagateMask(SDNode *N, SelectionDAG &DAG);
560560 /// This optimization uses wide integers or vectors when possible.
561561 /// \return number of stores that were merged into a merged store (the
562562 /// affected nodes are stored as a prefix in \p StoreNodes).
563 bool MergeConsecutiveStores(StoreSDNode *N);
563 bool MergeConsecutiveStores(StoreSDNode *St);
564564
565565 /// Try to transform a truncation where C is a constant:
566566 /// (trunc (and X, C)) -> (and (trunc X), (trunc C))
166166 SDValue NewIntValue) const;
167167 SDValue ExpandFCOPYSIGN(SDNode *Node) const;
168168 SDValue ExpandFABS(SDNode *Node) const;
169 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
169 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue Op0, EVT DestVT,
170170 const SDLoc &dl);
171171 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
172172 const SDLoc &dl);
208208 SDNode *AnalyzeNewNode(SDNode *N);
209209 void AnalyzeNewValue(SDValue &Val);
210210 void PerformExpensiveChecks();
211 void RemapId(TableId &N);
211 void RemapId(TableId &Id);
212212 void RemapValue(SDValue &V);
213213
214214 // Common routines.
331331 SDValue PromoteIntRes_XMULO(SDNode *N, unsigned ResNo);
332332
333333 // Integer Operand Promotion.
334 bool PromoteIntegerOperand(SDNode *N, unsigned OperandNo);
334 bool PromoteIntegerOperand(SDNode *N, unsigned OpNo);
335335 SDValue PromoteIntOp_ANY_EXTEND(SDNode *N);
336336 SDValue PromoteIntOp_ATOMIC_STORE(AtomicSDNode *N);
337337 SDValue PromoteIntOp_BITCAST(SDNode *N);
422422 bool ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi);
423423
424424 // Integer Operand Expansion.
425 bool ExpandIntegerOperand(SDNode *N, unsigned OperandNo);
425 bool ExpandIntegerOperand(SDNode *N, unsigned OpNo);
426426 SDValue ExpandIntOp_BR_CC(SDNode *N);
427427 SDValue ExpandIntOp_SELECT_CC(SDNode *N);
428428 SDValue ExpandIntOp_SETCC(SDNode *N);
578578 void ExpandFloatRes_XINT_TO_FP(SDNode *N, SDValue &Lo, SDValue &Hi);
579579
580580 // Float Operand Expansion.
581 bool ExpandFloatOperand(SDNode *N, unsigned OperandNo);
581 bool ExpandFloatOperand(SDNode *N, unsigned OpNo);
582582 SDValue ExpandFloatOp_BR_CC(SDNode *N);
583583 SDValue ExpandFloatOp_FCOPYSIGN(SDNode *N);
584584 SDValue ExpandFloatOp_FP_ROUND(SDNode *N);
619619 SDValue PromoteFloatRes_UNDEF(SDNode *N);
620620 SDValue PromoteFloatRes_XINT_TO_FP(SDNode *N);
621621
622 bool PromoteFloatOperand(SDNode *N, unsigned ResNo);
622 bool PromoteFloatOperand(SDNode *N, unsigned OpNo);
623623 SDValue PromoteFloatOp_BITCAST(SDNode *N, unsigned OpNo);
624624 SDValue PromoteFloatOp_FCOPYSIGN(SDNode *N, unsigned OpNo);
625625 SDValue PromoteFloatOp_FP_EXTEND(SDNode *N, unsigned OpNo);
644644 void SetScalarizedVector(SDValue Op, SDValue Result);
645645
646646 // Vector Result Scalarization: <1 x ty> -> ty.
647 void ScalarizeVectorResult(SDNode *N, unsigned OpNo);
647 void ScalarizeVectorResult(SDNode *N, unsigned ResNo);
648648 SDValue ScalarizeVecRes_MERGE_VALUES(SDNode *N, unsigned ResNo);
649649 SDValue ScalarizeVecRes_BinOp(SDNode *N);
650650 SDValue ScalarizeVecRes_TernaryOp(SDNode *N);
693693 void SetSplitVector(SDValue Op, SDValue Lo, SDValue Hi);
694694
695695 // Vector Result Splitting: <128 x ty> -> 2 x <64 x ty>.
696 void SplitVectorResult(SDNode *N, unsigned OpNo);
696 void SplitVectorResult(SDNode *N, unsigned ResNo);
697697 void SplitVecRes_BinOp(SDNode *N, SDValue &Lo, SDValue &Hi);
698698 void SplitVecRes_TernaryOp(SDNode *N, SDValue &Lo, SDValue &Hi);
699699 void SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo, SDValue &Hi);
709709 void SplitVecRes_FPOWI(SDNode *N, SDValue &Lo, SDValue &Hi);
710710 void SplitVecRes_FCOPYSIGN(SDNode *N, SDValue &Lo, SDValue &Hi);
711711 void SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo, SDValue &Hi);
712 void SplitVecRes_LOAD(LoadSDNode *N, SDValue &Lo, SDValue &Hi);
713 void SplitVecRes_MLOAD(MaskedLoadSDNode *N, SDValue &Lo, SDValue &Hi);
714 void SplitVecRes_MGATHER(MaskedGatherSDNode *N, SDValue &Lo, SDValue &Hi);
712 void SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo, SDValue &Hi);
713 void SplitVecRes_MLOAD(MaskedLoadSDNode *MLD, SDValue &Lo, SDValue &Hi);
714 void SplitVecRes_MGATHER(MaskedGatherSDNode *MGT, SDValue &Lo, SDValue &Hi);
715715 void SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo, SDValue &Hi);
716716 void SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi);
717717 void SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N, SDValue &Lo,
731731 SDValue SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo);
732732 SDValue SplitVecOp_MSTORE(MaskedStoreSDNode *N, unsigned OpNo);
733733 SDValue SplitVecOp_MSCATTER(MaskedScatterSDNode *N, unsigned OpNo);
734 SDValue SplitVecOp_MGATHER(MaskedGatherSDNode *N, unsigned OpNo);
734 SDValue SplitVecOp_MGATHER(MaskedGatherSDNode *MGT, unsigned OpNo);
735735 SDValue SplitVecOp_CONCAT_VECTORS(SDNode *N);
736736 SDValue SplitVecOp_VSETCC(SDNode *N);
737737 SDValue SplitVecOp_FP_ROUND(SDNode *N);
8787 /// Clone - Creates a clone of the specified SUnit. It does not copy the
8888 /// predecessors / successors info nor the temporary scheduling states.
8989 ///
90 SUnit *Clone(SUnit *N);
90 SUnit *Clone(SUnit *Old);
9191
9292 /// BuildSchedGraph - Build the SUnit graph from the selection dag that we
9393 /// are input. This SUnit graph is similar to the SelectionDAG, but
711711 void FindMergedConditions(const Value *Cond, MachineBasicBlock *TBB,
712712 MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
713713 MachineBasicBlock *SwitchBB,
714 Instruction::BinaryOps Opc, BranchProbability TW,
715 BranchProbability FW, bool InvertCond);
714 Instruction::BinaryOps Opc, BranchProbability TProb,
715 BranchProbability FProb, bool InvertCond);
716716 void EmitBranchForMergedCondition(const Value *Cond, MachineBasicBlock *TBB,
717717 MachineBasicBlock *FBB,
718718 MachineBasicBlock *CurBB,
719719 MachineBasicBlock *SwitchBB,
720 BranchProbability TW, BranchProbability FW,
720 BranchProbability TProb, BranchProbability FProb,
721721 bool InvertCond);
722722 bool ShouldEmitAsBranches(const std::vector &Cases);
723723 bool isExportableFromCurrentBlock(const Value *V, const BasicBlock *FromBB);
789789 };
790790
791791 /// Lower \p SLI into a STATEPOINT instruction.
792 SDValue LowerAsSTATEPOINT(StatepointLoweringInfo &SLI);
792 SDValue LowerAsSTATEPOINT(StatepointLoweringInfo &SI);
793793
794794 // This function is responsible for the whole statepoint lowering process.
795795 // It uniformly handles invoke and call statepoints.
796 void LowerStatepoint(ImmutableStatepoint Statepoint,
796 void LowerStatepoint(ImmutableStatepoint ISP,
797797 const BasicBlock *EHPadBB = nullptr);
798798
799799 void LowerCallSiteWithDeoptBundle(ImmutableCallSite CS, SDValue Callee,
896896
897897 void visitExtractValue(const User &I);
898898 void visitInsertValue(const User &I);
899 void visitLandingPad(const LandingPadInst &I);
899 void visitLandingPad(const LandingPadInst &LP);
900900
901901 void visitGetElementPtr(const User &I);
902902 void visitSelect(const User &I);
941941 const BasicBlock *EHPadBB = nullptr);
942942
943943 // These two are implemented in StatepointLowering.cpp
944 void visitGCRelocate(const GCRelocateInst &I);
944 void visitGCRelocate(const GCRelocateInst &Relocate);
945945 void visitGCResult(const GCResultInst &I);
946946
947947 void visitVectorReduce(const CallInst &I, unsigned Intrinsic);
10511051 /// Add this value to the specified inlineasm node operand list. This adds the
10521052 /// code marker, matching input operand index (if applicable), and includes
10531053 /// the number of values added into it.
1054 void AddInlineAsmOperands(unsigned Kind, bool HasMatching,
1054 void AddInlineAsmOperands(unsigned Code, bool HasMatching,
10551055 unsigned MatchingIdx, const SDLoc &dl,
10561056 SelectionDAG &DAG, std::vector &Ops) const;
10571057
420420
421421 SlotIndex buildSingleSubRegCopy(unsigned FromReg, unsigned ToReg,
422422 MachineBasicBlock &MB, MachineBasicBlock::iterator InsertBefore,
423 unsigned SubIdx, LiveInterval &DestLI, bool Late, SlotIndex PrevCopy);
423 unsigned SubIdx, LiveInterval &DestLI, bool Late, SlotIndex Def);
424424
425425 public:
426426 /// Create a new SplitEditor for editing the LiveInterval analyzed by SA.
444444 }
445445
446446 void getAnalysisUsage(AnalysisUsage &AU) const override;
447 bool runOnMachineFunction(MachineFunction &MF) override;
447 bool runOnMachineFunction(MachineFunction &Func) override;
448448
449449 private:
450450 /// Used in collectMarkers