llvm.org GIT mirror llvm / 7d7d996
Replace PROLOG_LABEL with a new CFI_INSTRUCTION. The old system was fairly convoluted: * A temporary label was created. * A single PROLOG_LABEL was created with it. * A few MCCFIInstructions were created with the same label. The semantics were that the cfi instructions were mapped to the PROLOG_LABEL via the temporary label. The output position was that of the PROLOG_LABEL. The temporary label itself was used only for doing the mapping. The new CFI_INSTRUCTION has a 1:1 mapping to MCCFIInstructions and points to one by holding an index into the CFI instructions of this function. I did consider removing MMI.getFrameInstructions completelly and having CFI_INSTRUCTION own a MCCFIInstruction, but MCCFIInstructions have non trivial constructors and destructors and are somewhat big, so the this setup is probably better. The net result is that we don't create temporary labels that are never used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203204 91177308-0d34-0410-b5e6-96231b3b80d8 Rafael Espindola 5 years ago
45 changed file(s) with 342 addition(s) and 339 deletion(s). Raw diff Collapse all Expand all
207207 /// function.
208208 void EmitFunctionBody();
209209
210 void emitPrologLabel(const MachineInstr &MI);
210 void emitCFIInstruction(const MachineInstr &MI);
211211
212212 enum CFIMoveType {
213213 CFI_M_None,
636636 /// bundle remain bundled.
637637 void eraseFromBundle();
638638
639 /// isLabel - Returns true if the MachineInstr represents a label.
640 ///
641 bool isLabel() const {
642 return getOpcode() == TargetOpcode::PROLOG_LABEL ||
643 getOpcode() == TargetOpcode::EH_LABEL ||
644 getOpcode() == TargetOpcode::GC_LABEL;
645 }
646
647 bool isPrologLabel() const {
648 return getOpcode() == TargetOpcode::PROLOG_LABEL;
649 }
650639 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
651640 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
641
642 /// isLabel - Returns true if the MachineInstr represents a label.
643 ///
644 bool isLabel() const { return isEHLabel() || isGCLabel(); }
645 bool isCFIInstruction() const {
646 return getOpcode() == TargetOpcode::CFI_INSTRUCTION;
647 }
648
649 // True if the instruction represents a position in the function.
650 bool isPosition() const { return isLabel() || isCFIInstruction(); }
651
652652 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
653653 /// A DBG_VALUE is indirect iff the first operand is a register and
654654 /// the second operand is an immediate.
714714 // Pseudo-instructions that don't produce any real output.
715715 case TargetOpcode::IMPLICIT_DEF:
716716 case TargetOpcode::KILL:
717 case TargetOpcode::PROLOG_LABEL:
717 case TargetOpcode::CFI_INSTRUCTION:
718718 case TargetOpcode::EH_LABEL:
719719 case TargetOpcode::GC_LABEL:
720720 case TargetOpcode::DBG_VALUE:
171171 MI->addOperand(*MF, MachineOperand::CreateMetadata(MD));
172172 return *this;
173173 }
174
174
175 const MachineInstrBuilder &addCFIIndex(unsigned CFIIndex) const {
176 MI->addOperand(*MF, MachineOperand::CreateCFIIndex(CFIIndex));
177 return *this;
178 }
179
175180 const MachineInstrBuilder &addSym(MCSymbol *Sym) const {
176181 MI->addOperand(*MF, MachineOperand::CreateMCSymbol(Sym));
177182 return *this;
237237 return FrameInstructions;
238238 }
239239
240 void addFrameInst(const MCCFIInstruction &Inst) {
240 unsigned LLVM_ATTRIBUTE_UNUSED_RESULT
241 addFrameInst(const MCCFIInstruction &Inst) {
241242 FrameInstructions.push_back(Inst);
243 return FrameInstructions.size() - 1;
242244 }
243245
244246 /// getCompactUnwindEncoding - Returns the compact unwind encoding for a
5757 MO_RegisterMask, ///< Mask of preserved registers.
5858 MO_RegisterLiveOut, ///< Mask of live-out registers.
5959 MO_Metadata, ///< Metadata reference (for debug info)
60 MO_MCSymbol ///< MCSymbol reference (for debug/eh info)
60 MO_MCSymbol, ///< MCSymbol reference (for debug/eh info)
61 MO_CFIIndex ///< MCCFIInstruction index.
6162 };
6263
6364 private:
155156 int64_t ImmVal; // For MO_Immediate.
156157 const uint32_t *RegMask; // For MO_RegisterMask and MO_RegisterLiveOut.
157158 const MDNode *MD; // For MO_Metadata.
158 MCSymbol *Sym; // For MO_MCSymbol
159 MCSymbol *Sym; // For MO_MCSymbol.
160 unsigned CFIIndex; // For MO_CFI.
159161
160162 struct { // For MO_Register.
161163 // Register number is in SmallContents.RegNo.
251253 /// isMetadata - Tests if this is a MO_Metadata operand.
252254 bool isMetadata() const { return OpKind == MO_Metadata; }
253255 bool isMCSymbol() const { return OpKind == MO_MCSymbol; }
254
256 bool isCFIIndex() const { return OpKind == MO_CFIIndex; }
255257
256258 //===--------------------------------------------------------------------===//
257259 // Accessors for Register Operands
440442 MCSymbol *getMCSymbol() const {
441443 assert(isMCSymbol() && "Wrong MachineOperand accessor");
442444 return Contents.Sym;
445 }
446
447 unsigned getCFIIndex() const {
448 assert(isCFIIndex() && "Wrong MachineOperand accessor");
449 return Contents.CFIIndex;
443450 }
444451
445452 /// getOffset - Return the offset from the symbol in this operand. This always
685692 return Op;
686693 }
687694
695 static MachineOperand CreateCFIIndex(unsigned CFIIndex) {
696 MachineOperand Op(MachineOperand::MO_CFIIndex);
697 Op.Contents.CFIIndex = CFIIndex;
698 return Op;
699 }
700
688701 friend class MachineInstr;
689702 friend class MachineRegisterInfo;
690703 private:
713713 let AsmString = "";
714714 let neverHasSideEffects = 1; // Note side effect is encoded in an operand.
715715 }
716 def PROLOG_LABEL : Instruction {
716 def CFI_INSTRUCTION : Instruction {
717717 let OutOperandList = (outs);
718718 let InOperandList = (ins i32imm:$id);
719719 let AsmString = "";
2424 enum {
2525 PHI = 0,
2626 INLINEASM = 1,
27 PROLOG_LABEL = 2,
27 CFI_INSTRUCTION = 2,
2828 EH_LABEL = 3,
2929 GC_LABEL = 4,
3030
698698 MF->getFunction()->needsUnwindTableEntry();
699699 }
700700
701 void AsmPrinter::emitPrologLabel(const MachineInstr &MI) {
702 const MCSymbol *Label = MI.getOperand(0).getMCSymbol();
703
701 void AsmPrinter::emitCFIInstruction(const MachineInstr &MI) {
704702 ExceptionHandling::ExceptionsType ExceptionHandlingType =
705703 MAI->getExceptionHandlingType();
706704 if (ExceptionHandlingType != ExceptionHandling::DwarfCFI &&
715713
716714 const MachineModuleInfo &MMI = MF->getMMI();
717715 const std::vector &Instrs = MMI.getFrameInstructions();
718 bool FoundOne = false;
719 (void)FoundOne;
720 for (std::vector::const_iterator I = Instrs.begin(),
721 E = Instrs.end(); I != E; ++I) {
722 if (I->getLabel() == Label) {
723 emitCFIInstruction(*I);
724 FoundOne = true;
725 }
726 }
727 assert(FoundOne);
716 unsigned CFIIndex = MI.getOperand(0).getCFIIndex();
717 const MCCFIInstruction &CFI = Instrs[CFIIndex];
718 emitCFIInstruction(CFI);
728719 }
729720
730721 /// EmitFunctionBody - This method emits the body and trailer for a
747738 LastMI = II;
748739
749740 // Print the assembly for the instruction.
750 if (!II->isLabel() && !II->isImplicitDef() && !II->isKill() &&
741 if (!II->isPosition() && !II->isImplicitDef() && !II->isKill() &&
751742 !II->isDebugValue()) {
752743 HasAnyRealCode = true;
753744 ++EmittedInsts;
766757 emitComments(*II, OutStreamer.GetCommentOS());
767758
768759 switch (II->getOpcode()) {
769 case TargetOpcode::PROLOG_LABEL:
770 emitPrologLabel(*II);
760 case TargetOpcode::CFI_INSTRUCTION:
761 emitCFIInstruction(*II);
771762 break;
772763
773764 case TargetOpcode::EH_LABEL:
810801 // label equaling the end of function label and an invalid "row" in the
811802 // FDE. We need to emit a noop in this situation so that the FDE's rows are
812803 // valid.
813 bool RequiresNoop = LastMI && LastMI->isPrologLabel();
804 bool RequiresNoop = LastMI && LastMI->isCFIInstruction();
814805
815806 // If the function is empty and the object file uses .subsections_via_symbols,
816807 // then we need to emit *something* to the function body to prevent the
16091609 History.push_back(MI);
16101610 } else {
16111611 // Not a DBG_VALUE instruction.
1612 if (!MI->isLabel())
1612 if (!MI->isPosition())
16131613 AtBlockEntry = false;
16141614
16151615 // First known non-DBG_VALUE and non-frame setup location marks
159159 MachineBasicBlock::iterator
160160 MachineBasicBlock::SkipPHIsAndLabels(MachineBasicBlock::iterator I) {
161161 iterator E = end();
162 while (I != E && (I->isPHI() || I->isLabel() || I->isDebugValue()))
162 while (I != E && (I->isPHI() || I->isPosition() || I->isDebugValue()))
163163 ++I;
164164 // FIXME: This needs to change if we wish to bundle labels / dbg_values
165165 // inside the bundle.
324324 }
325325
326326 bool MachineCSE::isCSECandidate(MachineInstr *MI) {
327 if (MI->isLabel() || MI->isPHI() || MI->isImplicitDef() ||
328 MI->isKill() || MI->isInlineAsm() || MI->isDebugValue())
327 if (MI->isPosition() || MI->isPHI() || MI->isImplicitDef() || MI->isKill() ||
328 MI->isInlineAsm() || MI->isDebugValue())
329329 return false;
330330
331331 // Ignore copies.
202202 return getRegMask() == Other.getRegMask();
203203 case MachineOperand::MO_MCSymbol:
204204 return getMCSymbol() == Other.getMCSymbol();
205 case MachineOperand::MO_CFIIndex:
206 return getCFIIndex() == Other.getCFIIndex();
205207 case MachineOperand::MO_Metadata:
206208 return getMetadata() == Other.getMetadata();
207209 }
246248 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
247249 case MachineOperand::MO_MCSymbol:
248250 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
251 case MachineOperand::MO_CFIIndex:
252 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex());
249253 }
250254 llvm_unreachable("Invalid machine operand type");
251255 }
379383 case MachineOperand::MO_MCSymbol:
380384 OS << "';
381385 break;
386 case MachineOperand::MO_CFIIndex:
387 OS << "";
388 break;
382389 }
383390
384391 if (unsigned TF = getTargetFlags())
12941301 return false;
12951302 }
12961303
1297 if (isLabel() || isDebugValue() ||
1298 isTerminator() || hasUnmodeledSideEffects())
1304 if (isPosition() || isDebugValue() || isTerminator() ||
1305 hasUnmodeledSideEffects())
12991306 return false;
13001307
13011308 // See if this instruction does a load. If so, we have to guarantee that the
595595
596596 // If there exists an instruction which belongs to the following
597597 // categories, we will discard the load candidate.
598 if (MI->isLabel() || MI->isPHI() || MI->isImplicitDef() ||
598 if (MI->isPosition() || MI->isPHI() || MI->isImplicitDef() ||
599599 MI->isKill() || MI->isInlineAsm() || MI->isDebugValue() ||
600600 MI->hasUnmodeledSideEffects()) {
601601 FoldAsLoadDefReg = 0;
803803 "RPTracker can't find MI");
804804 }
805805
806 assert((CanHandleTerminators || (!MI->isTerminator() && !MI->isLabel())) &&
807 "Cannot schedule terminators or labels!");
806 assert(
807 (CanHandleTerminators || (!MI->isTerminator() && !MI->isPosition())) &&
808 "Cannot schedule terminators or labels!");
808809
809810 // Add register-based dependencies (data, anti, and output).
810811 bool HasVRegDef = false;
644644 const MachineBasicBlock *MBB,
645645 const MachineFunction &MF) const {
646646 // Terminators and labels can't be scheduled around.
647 if (MI->isTerminator() || MI->isLabel())
647 if (MI->isTerminator() || MI->isPosition())
648648 return true;
649649
650650 // Don't attempt to schedule around any instruction that defines
9191 if (NeedsFrameMoves && NumInitialBytes) {
9292 // We emit this update even if the CFA is set from a frame pointer later so
9393 // that the CFA is valid in the interim.
94 MCSymbol *SPLabel = MMI.getContext().CreateTempSymbol();
95 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::PROLOG_LABEL))
96 .addSym(SPLabel);
97
9894 MachineLocation Dst(MachineLocation::VirtualFP);
9995 unsigned Reg = MRI->getDwarfRegNum(AArch64::XSP, true);
100 MMI.addFrameInst(
101 MCCFIInstruction::createDefCfa(SPLabel, Reg, -NumInitialBytes));
96 unsigned CFIIndex = MMI.addFrameInst(
97 MCCFIInstruction::createDefCfa(nullptr, Reg, -NumInitialBytes));
98 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
99 .addCFIIndex(CFIIndex);
102100 }
103101
104102 // Otherwise we need to set the frame pointer and/or add a second stack
128126 - MFI->getStackSize());
129127
130128 if (NeedsFrameMoves) {
131 MCSymbol *FPLabel = MMI.getContext().CreateTempSymbol();
132 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::PROLOG_LABEL))
133 .addSym(FPLabel);
134129 unsigned Reg = MRI->getDwarfRegNum(AArch64::X29, true);
135130 unsigned Offset = MFI->getObjectOffset(X29FrameIdx);
136 MMI.addFrameInst(MCCFIInstruction::createDefCfa(FPLabel, Reg, Offset));
131 unsigned CFIIndex = MMI.addFrameInst(
132 MCCFIInstruction::createDefCfa(nullptr, Reg, Offset));
133 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
134 .addCFIIndex(CFIIndex);
137135 }
138136
139137 FPNeedsSetting = false;
154152 if (!NeedsFrameMoves)
155153 return;
156154
157 // Reuse the label if appropriate, so create it in this outer scope.
158 MCSymbol *CSLabel = 0;
159
160155 // The rest of the stack adjustment
161156 if (!hasFP(MF) && NumResidualBytes) {
162 CSLabel = MMI.getContext().CreateTempSymbol();
163 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::PROLOG_LABEL))
164 .addSym(CSLabel);
165
166157 MachineLocation Dst(MachineLocation::VirtualFP);
167158 unsigned Reg = MRI->getDwarfRegNum(AArch64::XSP, true);
168159 unsigned Offset = NumResidualBytes + NumInitialBytes;
169 MMI.addFrameInst(MCCFIInstruction::createDefCfa(CSLabel, Reg, -Offset));
160 unsigned CFIIndex =
161 MMI.addFrameInst(MCCFIInstruction::createDefCfa(nullptr, Reg, -Offset));
162 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
163 .addCFIIndex(CFIIndex);
170164 }
171165
172166 // And any callee-saved registers (it's fine to leave them to the end here,
173167 // because the old values are still valid at this point.
174168 const std::vector &CSI = MFI->getCalleeSavedInfo();
175169 if (CSI.size()) {
176 if (!CSLabel) {
177 CSLabel = MMI.getContext().CreateTempSymbol();
178 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::PROLOG_LABEL))
179 .addSym(CSLabel);
180 }
181
182170 for (std::vector::const_iterator I = CSI.begin(),
183171 E = CSI.end(); I != E; ++I) {
184172 unsigned Offset = MFI->getObjectOffset(I->getFrameIdx());
185173 unsigned Reg = MRI->getDwarfRegNum(I->getReg(), true);
186 MMI.addFrameInst(MCCFIInstruction::createOffset(CSLabel, Reg, Offset));
174 unsigned CFIIndex = MMI.addFrameInst(
175 MCCFIInstruction::createOffset(nullptr, Reg, Offset));
176 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
177 .addCFIIndex(CFIIndex);
187178 }
188179 }
189180 }
734734 return getInstBundleLength(MI);
735735 case TargetOpcode::IMPLICIT_DEF:
736736 case TargetOpcode::KILL:
737 case TargetOpcode::PROLOG_LABEL:
737 case TargetOpcode::CFI_INSTRUCTION:
738738 case TargetOpcode::EH_LABEL:
739739 case TargetOpcode::GC_LABEL:
740740 case TargetOpcode::DBG_VALUE:
15421542 return false;
15431543
15441544 // Terminators and labels can't be scheduled around.
1545 if (MI->isTerminator() || MI->isLabel())
1545 if (MI->isTerminator() || MI->isPosition())
15461546 return true;
15471547
15481548 // Treat the start of the IT block as a scheduling boundary, but schedule
865865 }
866866 break;
867867 }
868 case TargetOpcode::PROLOG_LABEL:
868 case TargetOpcode::CFI_INSTRUCTION:
869 break;
869870 case TargetOpcode::EH_LABEL:
870871 MCE.emitLabel(MI.getOperand(0).getMCSymbol());
871872 break;
178178 if (ArgRegsSaveSize) {
179179 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -ArgRegsSaveSize,
180180 MachineInstr::FrameSetup);
181 MCSymbol *SPLabel = Context.CreateTempSymbol();
182 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::PROLOG_LABEL))
183 .addSym(SPLabel);
184181 CFAOffset -= ArgRegsSaveSize;
185 MMI.addFrameInst(
186 MCCFIInstruction::createDefCfaOffset(SPLabel, CFAOffset));
182 unsigned CFIIndex = MMI.addFrameInst(
183 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
184 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
185 .addCFIIndex(CFIIndex);
187186 }
188187
189188 if (!AFI->hasStackFrame()) {
190189 if (NumBytes - ArgRegsSaveSize != 0) {
191190 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -(NumBytes - ArgRegsSaveSize),
192191 MachineInstr::FrameSetup);
193 MCSymbol *SPLabel = Context.CreateTempSymbol();
194 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::PROLOG_LABEL))
195 .addSym(SPLabel);
196192 CFAOffset -= NumBytes - ArgRegsSaveSize;
197 MMI.addFrameInst(MCCFIInstruction::createDefCfaOffset(SPLabel,
198 CFAOffset));
193 unsigned CFIIndex = MMI.addFrameInst(
194 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
195 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
196 .addCFIIndex(CFIIndex);
199197 }
200198 return;
201199 }
310308 }
311309
312310 if (adjustedGPRCS1Size > 0) {
313 MCSymbol *SPLabel = Context.CreateTempSymbol();
314 BuildMI(MBB, ++GPRCS1Push, dl, TII.get(TargetOpcode::PROLOG_LABEL))
315 .addSym(SPLabel);
316311 CFAOffset -= adjustedGPRCS1Size;
317 MMI.addFrameInst(
318 MCCFIInstruction::createDefCfaOffset(SPLabel, CFAOffset));
312 unsigned CFIIndex = MMI.addFrameInst(
313 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
314 MachineBasicBlock::iterator Pos = ++GPRCS1Push;
315 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
316 .addCFIIndex(CFIIndex);
319317 for (std::vector::const_iterator I = CSI.begin(),
320318 E = CSI.end(); I != E; ++I) {
321319 unsigned Reg = I->getReg();
338336 case ARM::R6:
339337 case ARM::R7:
340338 case ARM::LR:
341 MMI.addFrameInst(MCCFIInstruction::createOffset(SPLabel,
342 MRI->getDwarfRegNum(Reg, true),
343 MFI->getObjectOffset(FI)));
339 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
340 nullptr, MRI->getDwarfRegNum(Reg, true), MFI->getObjectOffset(FI)));
341 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
342 .addCFIIndex(CFIIndex);
344343 break;
345344 }
346345 }
356355 emitRegPlusImmediate(!AFI->isThumbFunction(), MBB, GPRCS1Push, dl, TII,
357356 FramePtr, ARM::SP, FramePtrOffsetInPush,
358357 MachineInstr::FrameSetup);
359 MCSymbol *SPLabel = Context.CreateTempSymbol();
360 BuildMI(MBB, GPRCS1Push, dl, TII.get(TargetOpcode::PROLOG_LABEL))
361 .addSym(SPLabel);
362358 if (FramePtrOffsetInPush) {
363359 CFAOffset += FramePtrOffsetInPush;
364 MMI.addFrameInst(
365 MCCFIInstruction::createDefCfa(SPLabel,
366 MRI->getDwarfRegNum(FramePtr, true), CFAOffset));
367 } else
368 MMI.addFrameInst(
369 MCCFIInstruction::createDefCfaRegister(SPLabel,
370 MRI->getDwarfRegNum(FramePtr, true)));
360 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createDefCfa(
361 nullptr, MRI->getDwarfRegNum(FramePtr, true), CFAOffset));
362 BuildMI(MBB, GPRCS1Push, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
363 .addCFIIndex(CFIIndex);
364
365 } else {
366 unsigned CFIIndex =
367 MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(
368 nullptr, MRI->getDwarfRegNum(FramePtr, true)));
369 BuildMI(MBB, GPRCS1Push, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
370 .addCFIIndex(CFIIndex);
371 }
371372 }
372373
373374 if (GPRCS2Size > 0) {
374 MCSymbol *SPLabel = Context.CreateTempSymbol();
375 BuildMI(MBB, ++GPRCS2Push, dl, TII.get(TargetOpcode::PROLOG_LABEL))
376 .addSym(SPLabel);
375 MachineBasicBlock::iterator Pos = ++GPRCS2Push;
377376 if (!HasFP) {
378377 CFAOffset -= GPRCS2Size;
379 MMI.addFrameInst(
380 MCCFIInstruction::createDefCfaOffset(SPLabel, CFAOffset));
378 unsigned CFIIndex = MMI.addFrameInst(
379 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
380 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
381 .addCFIIndex(CFIIndex);
381382 }
382383 for (std::vector::const_iterator I = CSI.begin(),
383384 E = CSI.end(); I != E; ++I) {
392393 if (STI.isTargetMachO()) {
393394 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
394395 unsigned Offset = MFI->getObjectOffset(FI);
395 MMI.addFrameInst(
396 MCCFIInstruction::createOffset(SPLabel, DwarfReg, Offset));
396 unsigned CFIIndex = MMI.addFrameInst(
397 MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
398 BuildMI(MBB, Pos, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
399 .addCFIIndex(CFIIndex);
397400 }
398401 break;
399402 }
403406 if (DPRCSSize > 0) {
404407 // Since vpush register list cannot have gaps, there may be multiple vpush
405408 // instructions in the prologue.
406 MCSymbol *SPLabel = NULL;
407409 do {
408410 MachineBasicBlock::iterator Push = DPRCSPush++;
409411 if (!HasFP) {
410 SPLabel = Context.CreateTempSymbol();
411 BuildMI(MBB, DPRCSPush, dl, TII.get(TargetOpcode::PROLOG_LABEL))
412 .addSym(SPLabel);
413412 CFAOffset -= sizeOfSPAdjustment(Push);;
414 MMI.addFrameInst(
415 MCCFIInstruction::createDefCfaOffset(SPLabel, CFAOffset));
413 unsigned CFIIndex = MMI.addFrameInst(
414 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
415 BuildMI(MBB, DPRCSPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
416 .addCFIIndex(CFIIndex);
416417 }
417418 } while (DPRCSPush->getOpcode() == ARM::VSTMDDB_UPD);
418419
419 if (!SPLabel) {
420 SPLabel = Context.CreateTempSymbol();
421 BuildMI(MBB, DPRCSPush, dl, TII.get(TargetOpcode::PROLOG_LABEL))
422 .addSym(SPLabel);
423 }
424420 for (std::vector::const_iterator I = CSI.begin(),
425421 E = CSI.end(); I != E; ++I) {
426422 unsigned Reg = I->getReg();
429425 (Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs())) {
430426 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
431427 unsigned Offset = MFI->getObjectOffset(FI);
432 MMI.addFrameInst(MCCFIInstruction::createOffset(SPLabel, DwarfReg,
433 Offset));
428 unsigned CFIIndex = MMI.addFrameInst(
429 MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
430 BuildMI(MBB, DPRCSPush, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
431 .addCFIIndex(CFIIndex);
434432 }
435433 }
436434 }
437435
438436 if (NumBytes) {
439437 if (!HasFP) {
440 MCSymbol *SPLabel = Context.CreateTempSymbol();
441 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::PROLOG_LABEL))
442 .addSym(SPLabel);
443438 CFAOffset -= NumBytes;
444 MMI.addFrameInst(
445 MCCFIInstruction::createDefCfaOffset(SPLabel, CFAOffset));
439 unsigned CFIIndex = MMI.addFrameInst(
440 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
441 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
442 .addCFIIndex(CFIIndex);
446443 }
447444 }
448445
334334 while (MII != E) {
335335 MachineInstr *MI = &*MII;
336336
337 if (MI->isLabel() || MI->isImplicitDef() || MI->isCopy()) {
337 if (MI->isPosition() || MI->isImplicitDef() || MI->isCopy()) {
338338 ++MII;
339339 continue;
340340 }
113113 if (ArgRegsSaveSize) {
114114 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize,
115115 MachineInstr::FrameSetup);
116 MCSymbol *SPLabel = MMI.getContext().CreateTempSymbol();
117 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::PROLOG_LABEL))
118 .addSym(SPLabel);
119116 CFAOffset -= ArgRegsSaveSize;
120 MMI.addFrameInst(
121 MCCFIInstruction::createDefCfaOffset(SPLabel, CFAOffset));
117 unsigned CFIIndex = MMI.addFrameInst(
118 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
119 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
120 .addCFIIndex(CFIIndex);
122121 }
123122
124123 if (!AFI->hasStackFrame()) {
125124 if (NumBytes - ArgRegsSaveSize != 0) {
126125 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -(NumBytes - ArgRegsSaveSize),
127126 MachineInstr::FrameSetup);
128 MCSymbol *SPLabel = MMI.getContext().CreateTempSymbol();
129 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::PROLOG_LABEL))
130 .addSym(SPLabel);
131127 CFAOffset -= NumBytes - ArgRegsSaveSize;
132 MMI.addFrameInst(
133 MCCFIInstruction::createDefCfaOffset(SPLabel, CFAOffset));
128 unsigned CFIIndex = MMI.addFrameInst(
129 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
130 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
131 .addCFIIndex(CFIIndex);
134132 }
135133 return;
136134 }
189187 NumBytes = 0;
190188 }
191189
192 MCSymbol *SPLabel = MMI.getContext().CreateTempSymbol();
193 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::PROLOG_LABEL)).addSym(SPLabel);
194190 if (adjustedGPRCS1Size) {
195191 CFAOffset -= adjustedGPRCS1Size;
196 MMI.addFrameInst(
197 MCCFIInstruction::createDefCfaOffset(SPLabel, CFAOffset));
192 unsigned CFIIndex = MMI.addFrameInst(
193 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
194 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
195 .addCFIIndex(CFIIndex);
198196 }
199197 for (std::vector::const_iterator I = CSI.begin(),
200198 E = CSI.end(); I != E; ++I) {
218216 case ARM::R6:
219217 case ARM::R7:
220218 case ARM::LR:
221 MMI.addFrameInst(MCCFIInstruction::createOffset(SPLabel,
222 MRI->getDwarfRegNum(Reg, true),
223 MFI->getObjectOffset(FI)));
219 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
220 nullptr, MRI->getDwarfRegNum(Reg, true), MFI->getObjectOffset(FI)));
221 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
222 .addCFIIndex(CFIIndex);
224223 break;
225224 }
226225 }
233232 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
234233 .addReg(ARM::SP).addImm(FramePtrOffsetInBlock / 4)
235234 .setMIFlags(MachineInstr::FrameSetup));
236 MCSymbol *SPLabel = MMI.getContext().CreateTempSymbol();
237 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::PROLOG_LABEL))
238 .addSym(SPLabel);
239235 if(FramePtrOffsetInBlock) {
240236 CFAOffset += FramePtrOffsetInBlock;
241 MMI.addFrameInst(
242 MCCFIInstruction::createDefCfa(SPLabel,
243 MRI->getDwarfRegNum(FramePtr, true), CFAOffset));
244 } else
245 MMI.addFrameInst(
246 MCCFIInstruction::createDefCfaRegister(SPLabel,
247 MRI->getDwarfRegNum(FramePtr, true)));
237 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createDefCfa(
238 nullptr, MRI->getDwarfRegNum(FramePtr, true), CFAOffset));
239 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
240 .addCFIIndex(CFIIndex);
241 } else {
242 unsigned CFIIndex =
243 MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(
244 nullptr, MRI->getDwarfRegNum(FramePtr, true)));
245 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
246 .addCFIIndex(CFIIndex);
247 }
248248 if (NumBytes > 508)
249249 // If offset is > 508 then sp cannot be adjusted in a single instruction,
250250 // try restoring from fp instead.
256256 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes,
257257 MachineInstr::FrameSetup);
258258 if (!HasFP) {
259 MCSymbol *SPLabel = MMI.getContext().CreateTempSymbol();
260 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::PROLOG_LABEL))
261 .addSym(SPLabel);
262259 CFAOffset -= NumBytes;
263 MMI.addFrameInst(
264 MCCFIInstruction::createDefCfaOffset(SPLabel, CFAOffset));
260 unsigned CFIIndex = MMI.addFrameInst(
261 MCCFIInstruction::createDefCfaOffset(nullptr, CFAOffset));
262 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
263 .addCFIIndex(CFIIndex);
265264 }
266265 }
267266
16531653 return false;
16541654
16551655 // Terminators and labels can't be scheduled around.
1656 if (MI->getDesc().isTerminator() || MI->isLabel() || MI->isInlineAsm())
1656 if (MI->getDesc().isTerminator() || MI->isPosition() || MI->isInlineAsm())
16571657 return true;
16581658
16591659 return false;
107107 case TargetOpcode::REG_SEQUENCE:
108108 case TargetOpcode::IMPLICIT_DEF:
109109 case TargetOpcode::KILL:
110 case TargetOpcode::PROLOG_LABEL:
110 case TargetOpcode::CFI_INSTRUCTION:
111111 case TargetOpcode::EH_LABEL:
112112 case TargetOpcode::COPY:
113113 case TargetOpcode::INLINEASM:
298298 default:
299299 switch (Desc.getOpcode()) {
300300 default: llvm_unreachable("Unknown instruction size!");
301 case TargetOpcode::PROLOG_LABEL:
301 case TargetOpcode::CFI_INSTRUCTION:
302302 case TargetOpcode::EH_LABEL:
303303 case TargetOpcode::IMPLICIT_DEF:
304304 case TargetOpcode::KILL:
4747 TII.makeFrame(Mips::SP, StackSize, MBB, MBBI);
4848
4949 // emit ".cfi_def_cfa_offset StackSize"
50 MCSymbol *AdjustSPLabel = MMI.getContext().CreateTempSymbol();
51 BuildMI(MBB, MBBI, dl,
52 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(AdjustSPLabel);
53 MMI.addFrameInst(
54 MCCFIInstruction::createDefCfaOffset(AdjustSPLabel, -StackSize));
50 unsigned CFIIndex = MMI.addFrameInst(
51 MCCFIInstruction::createDefCfaOffset(nullptr, -StackSize));
52 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
53 .addCFIIndex(CFIIndex);
5554
5655 const std::vector &CSI = MFI->getCalleeSavedInfo();
5756
5857 if (CSI.size()) {
59 MCSymbol *CSLabel = MMI.getContext().CreateTempSymbol();
60 BuildMI(MBB, MBBI, dl,
61 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(CSLabel);
62
63
6458 const std::vector &CSI = MFI->getCalleeSavedInfo();
6559
6660 for (std::vector::const_iterator I = CSI.begin(),
6862 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
6963 unsigned Reg = I->getReg();
7064 unsigned DReg = MRI->getDwarfRegNum(Reg, true);
71 MMI.addFrameInst(MCCFIInstruction::createOffset(CSLabel, DReg, Offset));
65 unsigned CFIIndex = MMI.addFrameInst(
66 MCCFIInstruction::createOffset(nullptr, DReg, Offset));
67 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
68 .addCFIIndex(CFIIndex);
7269 }
7370 }
7471 if (hasFP(MF))
703703
704704 bool Filler::terminateSearch(const MachineInstr &Candidate) const {
705705 return (Candidate.isTerminator() || Candidate.isCall() ||
706 Candidate.isLabel() || Candidate.isInlineAsm() ||
706 Candidate.isPosition() || Candidate.isInlineAsm() ||
707707 Candidate.hasUnmodeledSideEffects());
708708 }
298298 TII.adjustStackPtr(SP, -StackSize, MBB, MBBI);
299299
300300 // emit ".cfi_def_cfa_offset StackSize"
301 MCSymbol *AdjustSPLabel = MMI.getContext().CreateTempSymbol();
302 BuildMI(MBB, MBBI, dl,
303 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(AdjustSPLabel);
304 MMI.addFrameInst(
305 MCCFIInstruction::createDefCfaOffset(AdjustSPLabel, -StackSize));
301 unsigned CFIIndex = MMI.addFrameInst(
302 MCCFIInstruction::createDefCfaOffset(nullptr, -StackSize));
303 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
304 .addCFIIndex(CFIIndex);
306305
307306 const std::vector &CSI = MFI->getCalleeSavedInfo();
308307
314313
315314 // Iterate over list of callee-saved registers and emit .cfi_offset
316315 // directives.
317 MCSymbol *CSLabel = MMI.getContext().CreateTempSymbol();
318 BuildMI(MBB, MBBI, dl,
319 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(CSLabel);
320
321316 for (std::vector::const_iterator I = CSI.begin(),
322317 E = CSI.end(); I != E; ++I) {
323318 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
334329 if (!STI.isLittle())
335330 std::swap(Reg0, Reg1);
336331
337 MMI.addFrameInst(
338 MCCFIInstruction::createOffset(CSLabel, Reg0, Offset));
339 MMI.addFrameInst(
340 MCCFIInstruction::createOffset(CSLabel, Reg1, Offset + 4));
332 unsigned CFIIndex = MMI.addFrameInst(
333 MCCFIInstruction::createOffset(nullptr, Reg0, Offset));
334 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
335 .addCFIIndex(CFIIndex);
336
337 CFIIndex = MMI.addFrameInst(
338 MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4));
339 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
340 .addCFIIndex(CFIIndex);
341341 } else {
342342 // Reg is either in GPR32 or FGR32.
343 MMI.addFrameInst(MCCFIInstruction::createOffset(
344 CSLabel, MRI->getDwarfRegNum(Reg, 1), Offset));
343 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
344 nullptr, MRI->getDwarfRegNum(Reg, 1), Offset));
345 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
346 .addCFIIndex(CFIIndex);
345347 }
346348 }
347349 }
359361 }
360362
361363 // Emit .cfi_offset directives for eh data registers.
362 MCSymbol *CSLabel2 = MMI.getContext().CreateTempSymbol();
363 BuildMI(MBB, MBBI, dl,
364 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(CSLabel2);
365364 for (int I = 0; I < 4; ++I) {
366365 int64_t Offset = MFI->getObjectOffset(MipsFI->getEhDataRegFI(I));
367366 unsigned Reg = MRI->getDwarfRegNum(ehDataReg(I), true);
368 MMI.addFrameInst(MCCFIInstruction::createOffset(CSLabel2, Reg, Offset));
367 unsigned CFIIndex = MMI.addFrameInst(
368 MCCFIInstruction::createOffset(nullptr, Reg, Offset));
369 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
370 .addCFIIndex(CFIIndex);
369371 }
370372 }
371373
375377 BuildMI(MBB, MBBI, dl, TII.get(ADDu), FP).addReg(SP).addReg(ZERO);
376378
377379 // emit ".cfi_def_cfa_register $fp"
378 MCSymbol *SetFPLabel = MMI.getContext().CreateTempSymbol();
379 BuildMI(MBB, MBBI, dl,
380 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(SetFPLabel);
381 MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(
382 SetFPLabel, MRI->getDwarfRegNum(FP, true)));
380 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(
381 nullptr, MRI->getDwarfRegNum(FP, true)));
382 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
383 .addCFIIndex(CFIIndex);
383384 }
384385 }
385386
120120 default:
121121 MCE.emitWordBE(getBinaryCodeForInstr(MI));
122122 break;
123 case TargetOpcode::PROLOG_LABEL:
123 case TargetOpcode::CFI_INSTRUCTION:
124 break;
124125 case TargetOpcode::EH_LABEL:
125126 MCE.emitLabel(MI.getOperand(0).getMCSymbol());
126127 break;
352352 assert((isDarwinABI || isSVR4ABI) &&
353353 "Currently only Darwin and SVR4 ABIs are supported for PowerPC.");
354354
355 // Prepare for frame info.
356 MCSymbol *FrameLabel = 0;
357
358355 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
359356 // process it.
360357 if (!isSVR4ABI)
560557 // Add the "machine moves" for the instructions we generated above, but in
561558 // reverse order.
562559 if (needsFrameMoves) {
563 // Mark effective beginning of when frame pointer becomes valid.
564 FrameLabel = MMI.getContext().CreateTempSymbol();
565 BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(FrameLabel);
566
567560 // Show update of SP.
568561 assert(NegFrameSize);
569 MMI.addFrameInst(
570 MCCFIInstruction::createDefCfaOffset(FrameLabel, NegFrameSize));
562 unsigned CFIIndex = MMI.addFrameInst(
563 MCCFIInstruction::createDefCfaOffset(nullptr, NegFrameSize));
564 BuildMI(MBB, MBBI, dl, TII.get(PPC::CFI_INSTRUCTION)).addCFIIndex(CFIIndex);
571565
572566 if (HasFP) {
573567 unsigned Reg = MRI->getDwarfRegNum(FPReg, true);
574 MMI.addFrameInst(
575 MCCFIInstruction::createOffset(FrameLabel, Reg, FPOffset));
568 CFIIndex = MMI.addFrameInst(
569 MCCFIInstruction::createOffset(nullptr, Reg, FPOffset));
570 BuildMI(MBB, MBBI, dl, TII.get(PPC::CFI_INSTRUCTION))
571 .addCFIIndex(CFIIndex);
576572 }
577573
578574 if (HasBP) {
579575 unsigned Reg = MRI->getDwarfRegNum(BPReg, true);
580 MMI.addFrameInst(
581 MCCFIInstruction::createOffset(FrameLabel, Reg, BPOffset));
576 CFIIndex = MMI.addFrameInst(
577 MCCFIInstruction::createOffset(nullptr, Reg, BPOffset));
578 BuildMI(MBB, MBBI, dl, TII.get(PPC::CFI_INSTRUCTION))
579 .addCFIIndex(CFIIndex);
582580 }
583581
584582 if (MustSaveLR) {
585583 unsigned Reg = MRI->getDwarfRegNum(LRReg, true);
586 MMI.addFrameInst(
587 MCCFIInstruction::createOffset(FrameLabel, Reg, LROffset));
588 }
589 }
590
591 MCSymbol *ReadyLabel = 0;
584 CFIIndex = MMI.addFrameInst(
585 MCCFIInstruction::createOffset(nullptr, Reg, LROffset));
586 BuildMI(MBB, MBBI, dl, TII.get(PPC::CFI_INSTRUCTION))
587 .addCFIIndex(CFIIndex);
588 }
589 }
592590
593591 // If there is a frame pointer, copy R1 into R31
594592 if (HasFP) {
597595 .addReg(SPReg);
598596
599597 if (needsFrameMoves) {
600 ReadyLabel = MMI.getContext().CreateTempSymbol();
601
602598 // Mark effective beginning of when frame pointer is ready.
603 BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(ReadyLabel);
604
605599 unsigned Reg = MRI->getDwarfRegNum(FPReg, true);
606 MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(ReadyLabel, Reg));
600 unsigned CFIIndex = MMI.addFrameInst(
601 MCCFIInstruction::createDefCfaRegister(nullptr, Reg));
602
603 BuildMI(MBB, MBBI, dl, TII.get(PPC::CFI_INSTRUCTION))
604 .addCFIIndex(CFIIndex);
607605 }
608606 }
609607
610608 if (needsFrameMoves) {
611 MCSymbol *Label = HasFP ? ReadyLabel : FrameLabel;
612
613609 // Add callee saved registers to move list.
614610 const std::vector &CSI = MFI->getCalleeSavedInfo();
615611 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
630626 // For 64-bit SVR4 when we have spilled CRs, the spill location
631627 // is SP+8, not a frame-relative slot.
632628 if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
633 MMI.addFrameInst(MCCFIInstruction::createOffset(
634 Label, MRI->getDwarfRegNum(PPC::CR2, true), 8));
629 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
630 nullptr, MRI->getDwarfRegNum(PPC::CR2, true), 8));
631 BuildMI(MBB, MBBI, dl, TII.get(PPC::CFI_INSTRUCTION))
632 .addCFIIndex(CFIIndex);
635633 continue;
636634 }
637635
638636 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
639 MMI.addFrameInst(MCCFIInstruction::createOffset(
640 Label, MRI->getDwarfRegNum(Reg, true), Offset));
637 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
638 nullptr, MRI->getDwarfRegNum(Reg, true), Offset));
639 BuildMI(MBB, MBBI, dl, TII.get(PPC::CFI_INSTRUCTION))
640 .addCFIIndex(CFIIndex);
641641 }
642642 }
643643 }
210210 if (I->isDebugValue())
211211 continue;
212212
213
214 if (I->hasUnmodeledSideEffects()
215 || I->isInlineAsm()
216 || I->isLabel()
217 || I->hasDelaySlot()
218 || I->isBundledWithSucc())
213 if (I->hasUnmodeledSideEffects() || I->isInlineAsm() || I->isPosition() ||
214 I->hasDelaySlot() || I->isBundledWithSucc())
219215 break;
220216
221217 if (delayHasHazard(I, sawLoad, sawStore, RegDefs, RegUses)) {
144144 }
145145 break;
146146 }
147 case TargetOpcode::PROLOG_LABEL:
147 case TargetOpcode::CFI_INSTRUCTION:
148 break;
148149 case TargetOpcode::EH_LABEL: {
149150 MCE.emitLabel(MI->getOperand(0).getMCSymbol());
150151 break;
103103
104104 MachineModuleInfo &MMI = MF.getMMI();
105105 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
106 MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol();
107 BuildMI(MBB, MBBI, dl, TII.get(SP::PROLOG_LABEL)).addSym(FrameLabel);
108
109106 unsigned regFP = MRI->getDwarfRegNum(SP::I6, true);
110107
111108 // Emit ".cfi_def_cfa_register 30".
112 MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(FrameLabel,
113 regFP));
109 unsigned CFIIndex =
110 MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister(nullptr, regFP));
111 BuildMI(MBB, MBBI, dl, TII.get(SP::CFI_INSTRUCTION)).addCFIIndex(CFIIndex);
112
114113 // Emit ".cfi_window_save".
115 MMI.addFrameInst(MCCFIInstruction::createWindowSave(FrameLabel));
114 CFIIndex = MMI.addFrameInst(MCCFIInstruction::createWindowSave(nullptr));
115 BuildMI(MBB, MBBI, dl, TII.get(SP::CFI_INSTRUCTION)).addCFIIndex(CFIIndex);
116116
117117 unsigned regInRA = MRI->getDwarfRegNum(SP::I7, true);
118118 unsigned regOutRA = MRI->getDwarfRegNum(SP::O7, true);
119119 // Emit ".cfi_register 15, 31".
120 MMI.addFrameInst(MCCFIInstruction::createRegister(FrameLabel,
121 regOutRA,
122 regInRA));
120 CFIIndex = MMI.addFrameInst(
121 MCCFIInstruction::createRegister(nullptr, regOutRA, regInRA));
122 BuildMI(MBB, MBBI, dl, TII.get(SP::CFI_INSTRUCTION)).addCFIIndex(CFIIndex);
123123 }
124124
125125 void SparcFrameLowering::
332332 llvm_unreachable("Couldn't skip over GPR saves");
333333
334334 // Add CFI for the GPR saves.
335 MCSymbol *GPRSaveLabel = MMI.getContext().CreateTempSymbol();
336 BuildMI(MBB, MBBI, DL,
337 ZII->get(TargetOpcode::PROLOG_LABEL)).addSym(GPRSaveLabel);
338335 for (auto &Save : CSI) {
339336 unsigned Reg = Save.getReg();
340337 if (SystemZ::GR64BitRegClass.contains(Reg)) {
341338 int64_t Offset = SPOffsetFromCFA + RegSpillOffsets[Reg];
342 MMI.addFrameInst(MCCFIInstruction::createOffset(
343 GPRSaveLabel, MRI->getDwarfRegNum(Reg, true), Offset));
339 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
340 nullptr, MRI->getDwarfRegNum(Reg, true), Offset));
341 BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
342 .addCFIIndex(CFIIndex);
344343 }
345344 }
346345 }
352351 emitIncrement(MBB, MBBI, DL, SystemZ::R15D, Delta, ZII);
353352
354353 // Add CFI for the allocation.
355 MCSymbol *AdjustSPLabel = MMI.getContext().CreateTempSymbol();
356 BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::PROLOG_LABEL))
357 .addSym(AdjustSPLabel);
358 MMI.addFrameInst(MCCFIInstruction::createDefCfaOffset(
359 AdjustSPLabel, SPOffsetFromCFA + Delta));
354 unsigned CFIIndex = MMI.addFrameInst(
355 MCCFIInstruction::createDefCfaOffset(nullptr, SPOffsetFromCFA + Delta));
356 BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
357 .addCFIIndex(CFIIndex);
360358 SPOffsetFromCFA += Delta;
361359 }
362360
366364 .addReg(SystemZ::R15D);
367365
368366 // Add CFI for the new frame location.
369 MCSymbol *SetFPLabel = MMI.getContext().CreateTempSymbol();
370 BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::PROLOG_LABEL))
371 .addSym(SetFPLabel);
372367 unsigned HardFP = MRI->getDwarfRegNum(SystemZ::R11D, true);
373 MMI.addFrameInst(
374 MCCFIInstruction::createDefCfaRegister(SetFPLabel, HardFP));
368 unsigned CFIIndex = MMI.addFrameInst(
369 MCCFIInstruction::createDefCfaRegister(nullptr, HardFP));
370 BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
371 .addCFIIndex(CFIIndex);
375372
376373 // Mark the FramePtr as live at the beginning of every block except
377374 // the entry block. (We'll have marked R11 as live on entry when
381378 }
382379
383380 // Skip over the FPR saves.
384 MCSymbol *FPRSaveLabel = 0;
381 SmallVector CFIIndexes;
385382 for (auto &Save : CSI) {
386383 unsigned Reg = Save.getReg();
387384 if (SystemZ::FP64BitRegClass.contains(Reg)) {
393390 llvm_unreachable("Couldn't skip over FPR save");
394391
395392 // Add CFI for the this save.
396 if (!FPRSaveLabel)
397 FPRSaveLabel = MMI.getContext().CreateTempSymbol();
398393 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
399394 int64_t Offset = getFrameIndexOffset(MF, Save.getFrameIdx());
400 MMI.addFrameInst(MCCFIInstruction::createOffset(
401 FPRSaveLabel, DwarfReg, SPOffsetFromCFA + Offset));
395 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
396 nullptr, DwarfReg, SPOffsetFromCFA + Offset));
397 CFIIndexes.push_back(CFIIndex);
402398 }
403399 }
404400 // Complete the CFI for the FPR saves, modelling them as taking effect
405401 // after the last save.
406 if (FPRSaveLabel)
407 BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::PROLOG_LABEL))
408 .addSym(FPRSaveLabel);
402 for (auto CFIIndex : CFIIndexes) {
403 BuildMI(MBB, MBBI, DL, ZII->get(TargetOpcode::CFI_INSTRUCTION))
404 .addCFIIndex(CFIIndex);
405 }
409406 }
410407
411408 void SystemZFrameLowering::emitEpilogue(MachineFunction &MF,
11141114 if (MI.getOperand(0).getSymbolName()[0])
11151115 report_fatal_error("JIT does not support inline asm!");
11161116 break;
1117 case TargetOpcode::PROLOG_LABEL:
1117 case TargetOpcode::CFI_INSTRUCTION:
1118 break;
11181119 case TargetOpcode::GC_LABEL:
11191120 case TargetOpcode::EH_LABEL:
11201121 MCE.emitLabel(MI.getOperand(0).getMCSymbol());
303303 return false;
304304 }
305305
306 void X86FrameLowering::emitCalleeSavedFrameMoves(MachineFunction &MF,
307 MCSymbol *Label,
308 unsigned FramePtr) const {
306 void X86FrameLowering::emitCalleeSavedFrameMoves(
307 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc DL,
308 unsigned FramePtr) const {
309 MachineFunction &MF = *MBB.getParent();
309310 MachineFrameInfo *MFI = MF.getFrameInfo();
310311 MachineModuleInfo &MMI = MF.getMMI();
311312 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
313 const X86InstrInfo &TII = *TM.getInstrInfo();
312314
313315 // Add callee saved registers to move list.
314316 const std::vector &CSI = MFI->getCalleeSavedInfo();
362364 continue;
363365
364366 unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
365 MMI.addFrameInst(MCCFIInstruction::createOffset(Label, DwarfReg, Offset));
367 unsigned CFIIndex =
368 MMI.addFrameInst(MCCFIInstruction::createOffset(0, DwarfReg, Offset));
369 BuildMI(MBB, MBBI, DL, TII.get(X86::CFI_INSTRUCTION)).addCFIIndex(CFIIndex);
366370 }
367371 }
368372
502506
503507 if (needsFrameMoves) {
504508 // Mark the place where EBP/RBP was saved.
505 MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol();
506 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL))
507 .addSym(FrameLabel);
508
509509 // Define the current CFA rule to use the provided offset.
510510 assert(StackSize);
511 MMI.addFrameInst(
512 MCCFIInstruction::createDefCfaOffset(FrameLabel, 2 * stackGrowth));
511 unsigned CFIIndex = MMI.addFrameInst(
512 MCCFIInstruction::createDefCfaOffset(0, 2 * stackGrowth));
513 BuildMI(MBB, MBBI, DL, TII.get(X86::CFI_INSTRUCTION))
514 .addCFIIndex(CFIIndex);
513515
514516 // Change the rule for the FramePtr to be an "offset" rule.
515517 unsigned DwarfFramePtr = RegInfo->getDwarfRegNum(FramePtr, true);
516 MMI.addFrameInst(MCCFIInstruction::createOffset(FrameLabel, DwarfFramePtr,
517 2 * stackGrowth));
518 CFIIndex = MMI.addFrameInst(
519 MCCFIInstruction::createOffset(0, DwarfFramePtr, 2 * stackGrowth));
520 BuildMI(MBB, MBBI, DL, TII.get(X86::CFI_INSTRUCTION))
521 .addCFIIndex(CFIIndex);
518522 }
519523
520524 // Update EBP with the new base value.
525529
526530 if (needsFrameMoves) {
527531 // Mark effective beginning of when frame pointer becomes valid.
528 MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol();
529 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL))
530 .addSym(FrameLabel);
531
532532 // Define the current CFA to use the EBP/RBP register.
533533 unsigned DwarfFramePtr = RegInfo->getDwarfRegNum(FramePtr, true);
534 MMI.addFrameInst(
535 MCCFIInstruction::createDefCfaRegister(FrameLabel, DwarfFramePtr));
534 unsigned CFIIndex = MMI.addFrameInst(
535 MCCFIInstruction::createDefCfaRegister(0, DwarfFramePtr));
536 BuildMI(MBB, MBBI, DL, TII.get(X86::CFI_INSTRUCTION))
537 .addCFIIndex(CFIIndex);
536538 }
537539
538540 // Mark the FramePtr as live-in in every block except the entry.
556558
557559 if (!HasFP && needsFrameMoves) {
558560 // Mark callee-saved push instruction.
559 MCSymbol *Label = MMI.getContext().CreateTempSymbol();
560 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)).addSym(Label);
561
562561 // Define the current CFA rule to use the provided offset.
563562 assert(StackSize);
564 MMI.addFrameInst(
565 MCCFIInstruction::createDefCfaOffset(Label, StackOffset));
563 unsigned CFIIndex = MMI.addFrameInst(
564 MCCFIInstruction::createDefCfaOffset(nullptr, StackOffset));
565 BuildMI(MBB, MBBI, DL, TII.get(X86::CFI_INSTRUCTION))
566 .addCFIIndex(CFIIndex);
566567 StackOffset += stackGrowth;
567568 }
568569 }
691692
692693 if (( (!HasFP && NumBytes) || PushedRegs) && needsFrameMoves) {
693694 // Mark end of stack pointer adjustment.
694 MCSymbol *Label = MMI.getContext().CreateTempSymbol();
695 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL))
696 .addSym(Label);
697
698695 if (!HasFP && NumBytes) {
699696 // Define the current CFA rule to use the provided offset.
700697 assert(StackSize);
701 MMI.addFrameInst(MCCFIInstruction::createDefCfaOffset(
702 Label, -StackSize + stackGrowth));
698 unsigned CFIIndex = MMI.addFrameInst(
699 MCCFIInstruction::createDefCfaOffset(0, -StackSize + stackGrowth));
700
701 BuildMI(MBB, MBBI, DL, TII.get(X86::CFI_INSTRUCTION))
702 .addCFIIndex(CFIIndex);
703703 }
704704
705705 // Emit DWARF info specifying the offsets of the callee-saved registers.
706706 if (PushedRegs)
707 emitCalleeSavedFrameMoves(MF, Label, HasFP ? FramePtr : StackPtr);
707 emitCalleeSavedFrameMoves(MBB, MBBI, DL, HasFP ? FramePtr : StackPtr);
708708 }
709709 }
710710
3333 TM(tm), STI(sti) {
3434 }
3535
36 void emitCalleeSavedFrameMoves(MachineFunction &MF, MCSymbol *Label,
36 void emitCalleeSavedFrameMoves(MachineBasicBlock &MBB,
37 MachineBasicBlock::iterator MBBI, DebugLoc DL,
3738 unsigned FramePtr) const;
3839
3940 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
6161 MachineBasicBlock::iterator MBBI, DebugLoc dl,
6262 const TargetInstrInfo &TII,
6363 MachineModuleInfo *MMI, unsigned DRegNum) {
64 MCSymbol *Label = MMI->getContext().CreateTempSymbol();
65 BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(Label);
66 MMI->addFrameInst(MCCFIInstruction::createDefCfaRegister(Label, DRegNum));
64 unsigned CFIIndex = MMI->addFrameInst(
65 MCCFIInstruction::createDefCfaRegister(nullptr, DRegNum));
66 BuildMI(MBB, MBBI, dl, TII.get(XCore::CFI_INSTRUCTION)).addCFIIndex(CFIIndex);
6767 }
6868
6969 static void EmitDefCfaOffset(MachineBasicBlock &MBB,
7070 MachineBasicBlock::iterator MBBI, DebugLoc dl,
7171 const TargetInstrInfo &TII,
7272 MachineModuleInfo *MMI, int Offset) {
73 MCSymbol *Label = MMI->getContext().CreateTempSymbol();
74 BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(Label);
75 MMI->addFrameInst(MCCFIInstruction::createDefCfaOffset(Label, -Offset));
73 unsigned CFIIndex =
74 MMI->addFrameInst(MCCFIInstruction::createDefCfaOffset(nullptr, -Offset));
75 BuildMI(MBB, MBBI, dl, TII.get(XCore::CFI_INSTRUCTION)).addCFIIndex(CFIIndex);
7676 }
7777
7878 static void EmitCfiOffset(MachineBasicBlock &MBB,
7979 MachineBasicBlock::iterator MBBI, DebugLoc dl,
8080 const TargetInstrInfo &TII, MachineModuleInfo *MMI,
81 unsigned DRegNum, int Offset, MCSymbol *Label) {
82 if (!Label) {
83 Label = MMI->getContext().CreateTempSymbol();
84 BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(Label);
85 }
86 MMI->addFrameInst(MCCFIInstruction::createOffset(Label, DRegNum, Offset));
81 unsigned DRegNum, int Offset) {
82 unsigned CFIIndex = MMI->addFrameInst(
83 MCCFIInstruction::createOffset(nullptr, DRegNum, Offset));
84 BuildMI(MBB, MBBI, dl, TII.get(XCore::CFI_INSTRUCTION)).addCFIIndex(CFIIndex);
8785 }
8886
8987 /// The SP register is moved in steps of 'MaxImmU16' towards the bottom of the
261259 if (emitFrameMoves) {
262260 EmitDefCfaOffset(MBB, MBBI, dl, TII, MMI, Adjusted*4);
263261 unsigned DRegNum = MRI->getDwarfRegNum(XCore::LR, true);
264 EmitCfiOffset(MBB, MBBI, dl, TII, MMI, DRegNum, 0, NULL);
262 EmitCfiOffset(MBB, MBBI, dl, TII, MMI, DRegNum, 0);
265263 }
266264 }
267265
286284 MachineMemOperand::MOStore));
287285 if (emitFrameMoves) {
288286 unsigned DRegNum = MRI->getDwarfRegNum(SpillList[i].Reg, true);
289 EmitCfiOffset(MBB,MBBI,dl,TII,MMI, DRegNum, SpillList[i].Offset, NULL);
287 EmitCfiOffset(MBB, MBBI, dl, TII, MMI, DRegNum, SpillList[i].Offset);
290288 }
291289 }
292290
305303
306304 if (emitFrameMoves) {
307305 // Frame moves for callee saved.
308 std::vector >&SpillLabels =
309 XFI->getSpillLabels();
306 auto SpillLabels = XFI->getSpillLabels();
310307 for (unsigned I = 0, E = SpillLabels.size(); I != E; ++I) {
311 MCSymbol *SpillLabel = SpillLabels[I].first;
308 MachineBasicBlock::iterator Pos = SpillLabels[I].first;
309 ++Pos;
312310 CalleeSavedInfo &CSI = SpillLabels[I].second;
313311 int Offset = MFI->getObjectOffset(CSI.getFrameIdx());
314312 unsigned DRegNum = MRI->getDwarfRegNum(CSI.getReg(), true);
315 EmitCfiOffset(MBB, MBBI, dl, TII, MMI, DRegNum, Offset, SpillLabel);
313 EmitCfiOffset(MBB, Pos, dl, TII, MMI, DRegNum, Offset);
316314 }
317315 if (XFI->hasEHSpillSlot()) {
318316 // The unwinder requires stack slot & CFI offsets for the exception info.
322320 assert(SpillList.size()==2 && "Unexpected SpillList size");
323321 EmitCfiOffset(MBB, MBBI, dl, TII, MMI,
324322 MRI->getDwarfRegNum(SpillList[0].Reg, true),
325 SpillList[0].Offset, NULL);
323 SpillList[0].Offset);
326324 EmitCfiOffset(MBB, MBBI, dl, TII, MMI,
327325 MRI->getDwarfRegNum(SpillList[1].Reg, true),
328 SpillList[1].Offset, NULL);
326 SpillList[1].Offset);
329327 }
330328 }
331329 }
426424 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
427425 TII.storeRegToStackSlot(MBB, MI, Reg, true, it->getFrameIdx(), RC, TRI);
428426 if (emitFrameMoves) {
429 MCSymbol *SaveLabel = MF->getContext().CreateTempSymbol();
430 BuildMI(MBB, MI, DL, TII.get(XCore::PROLOG_LABEL)).addSym(SaveLabel);
431 XFI->getSpillLabels().push_back(std::make_pair(SaveLabel, *it));
427 auto Store = MI;
428 --Store;
429 XFI->getSpillLabels().push_back(std::make_pair(Store, *it));
432430 }
433431 }
434432 return true;
3636 bool ReturnStackOffsetSet;
3737 int VarArgsFrameIndex;
3838 mutable int CachedEStackSize;
39 std::vectorCSymbol*, CalleeSavedInfo> > SpillLabels;
39 std::vectorachineBasicBlock::iterator, CalleeSavedInfo>>
40 SpillLabels;
4041
4142 public:
4243 XCoreFunctionInfo() :
9495
9596 bool isLargeFrame(const MachineFunction &MF) const;
9697
97 std::vectorCSymbol*, CalleeSavedInfo> > &getSpillLabels() {
98 std::vectorachineBasicBlock::iterator, CalleeSavedInfo>> &
99 getSpillLabels() {
98100 return SpillLabels;
99101 }
100102 };
99 ; ... referring indirectly to stubs for its typeinfo ...
1010 ; CHECK: // @TType Encoding = indirect pcrel sdata8
1111 ; ... one of which is "int"'s typeinfo
12 ; CHECK: .Ltmp9:
13 ; CHECK-NEXT: .xword .L_ZTIi.DW.stub-.Ltmp9
12 ; CHECK: .Ltmp7:
13 ; CHECK-NEXT: .xword .L_ZTIi.DW.stub-.Ltmp7
1414
1515 ; .. and which is properly defined (in a writable section for the dynamic loader) later.
1616 ; CHECK: .section .data.rel,"aw"
88 ; statement shouldn't be implicitly defined.
99
1010 ; CHECK-LABEL: func:
11 ; CHECK: Ltmp3: @ Block address taken
11 ; CHECK: Ltmp1: @ Block address taken
1212 ; CHECK-NOT: @ implicit-def: R0
1313 ; CHECK: @ 4-byte Reload
1414
6868 store i8* blockaddress(@foo, %L5), i8** @nextaddr, align 4
6969 ret i32 %res.3
7070 }
71 ; ARM: .long Ltmp1-(LPC{{.*}}+8)
72 ; THUMB: .long Ltmp1-(LPC{{.*}}+4)
71 ; ARM: .long Ltmp0-(LPC{{.*}}+8)
72 ; THUMB: .long Ltmp0-(LPC{{.*}}+4)
7373 ; THUMB: .long _nextaddr-([[NEXTADDR_PCBASE]]+4)
74 ; THUMB2: .long Ltmp1
74 ; THUMB2: .long Ltmp0
1717 ; CHECK-NEXT: Ltmp0:
1818
1919 ; CHECK: _bar: ## @bar
20 ; CHECK-NEXT: Ltmp3:
20 ; CHECK-NEXT: Ltmp2:
2121
2222 ; CHECK: ## FDE CIE Offset
2323 ; CHECK-NEXT: .long
2929 ; CHECK: ## FDE CIE Offset
3030 ; CHECK-NEXT: .long
3131 ; CHECK-NEXT: Ltmp[[NUM1:[0-9]*]]:
32 ; CHECK-NEXT: Ltmp[[NUM2:[0-9]*]] = Ltmp3-Ltmp[[NUM1]] ## FDE initial location
32 ; CHECK-NEXT: Ltmp[[NUM2:[0-9]*]] = Ltmp2-Ltmp[[NUM1]] ## FDE initial location
3333 ; CHECK-NEXT: {{.quad|.long}} Ltmp[[NUM2]]
3434
3535
3737 ; OLD-NEXT: Ltmp0:
3838
3939 ; OLD: _bar: ## @bar
40 ; OLD-NEXT: Ltmp3:
40 ; OLD-NEXT: Ltmp2:
4141
4242 ; OLD: ## FDE CIE Offset
4343 ; OLD-NEXT: .long
4747 ; OLD: ## FDE CIE Offset
4848 ; OLD-NEXT: .long
4949 ; OLD-NEXT: Ltmp[[NUM1:[0-9]*]]:
50 ; OLD-NEXT: {{.quad|.long}} Ltmp3-Ltmp[[NUM1]] ## FDE initial location
50 ; OLD-NEXT: {{.quad|.long}} Ltmp2-Ltmp[[NUM1]] ## FDE initial location
151151
152152 for (unsigned i = 0, e = NumberedInstructions->size(); i != e; ++i) {
153153 const AsmWriterInst *Inst = getAsmWriterInstByID(i);
154 if (Inst == 0) continue; // PHI, INLINEASM, PROLOG_LABEL, etc.
154 if (Inst == 0)
155 continue; // PHI, INLINEASM, CFI_INSTRUCTION, etc.
155156
156157 std::string Command;
157158 if (Inst->Operands.empty())
293293 void CodeGenTarget::ComputeInstrsByEnum() const {
294294 // The ordering here must match the ordering in TargetOpcodes.h.
295295 static const char *const FixedInstrs[] = {
296 "PHI", "INLINEASM", "PROLOG_LABEL", "EH_LABEL",
296 "PHI", "INLINEASM", "CFI_INSTRUCTION", "EH_LABEL",
297297 "GC_LABEL", "KILL", "EXTRACT_SUBREG", "INSERT_SUBREG",
298298 "IMPLICIT_DEF", "SUBREG_TO_REG", "COPY_TO_REGCLASS", "DBG_VALUE",
299299 "REG_SEQUENCE", "COPY", "BUNDLE", "LIFETIME_START",