llvm.org GIT mirror llvm / 7d6a2cb
Revert "[SLP] Additional tests with the cost of vector operations." This reverts commit a61718435fc4118c82f8aa6133fd81f803789c1e. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@288371 91177308-0d34-0410-b5e6-96231b3b80d8 Alexey Bataev 3 years ago
2 changed file(s) with 1 addition(s) and 20 deletion(s). Raw diff Collapse all Expand all
3333
3434 ; CHECK-LABEL: reduction_cost_int
3535 ; CHECK: cost of 17 {{.*}} extractelement
36 ; AVX-LABEL: reduction_cost_int
37 ; AVX: cost of 5 {{.*}} extractelement
3836
3937 %r = extractelement <8 x i32> %bin.rdx.3, i32 0
4038 ret i32 %r
0 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
1 ; RUN: opt -slp-vectorizer -slp-vectorize-hor -S -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 -debug < %s 2>&1 | FileCheck %s
2 ; RUN: opt -slp-vectorizer -slp-vectorize-hor -S -mtriple=x86_64-unknown-linux-gnu -mcpu=core2 -debug < %s 2>&1 | FileCheck --check-prefix=SSE2 %s
1 ; RUN: opt -slp-vectorizer -slp-vectorize-hor -S -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 < %s | FileCheck %s
32
43 ; int test(unsigned int *p) {
54 ; int sum = 0;
87 ; return sum;
98 ; }
109
11 ; Vector cost is 5, Scalar cost is 32
12 ; CHECK: Adding cost -27 for reduction that starts with %7 = load i32, i32* %arrayidx.7, align 4 (It is a splitting reduction)
13 ; Vector cost is 17, Scalar cost is 16
14 ; SSE2: Adding cost 1 for reduction that starts with %7 = load i32, i32* %arrayidx.7, align 4 (It is a splitting reduction)
1510 define i32 @test(i32* nocapture readonly %p) {
1611 ; CHECK-LABEL: @test(
1712 ; CHECK: [[BC:%.*]] = bitcast i32* %p to <8 x i32>*
2419 ; CHECK-NEXT: [[BIN_RDX4:%.*]] = add <8 x i32> [[BIN_RDX2]], [[RDX_SHUF3]]
2520 ; CHECK-NEXT: [[TMP2:%.*]] = extractelement <8 x i32> [[BIN_RDX4]], i32 0
2621 ; CHECK: ret i32 [[TMP2]]
27 ;
28 ; SSE2-LABEL: @test(
29 ; SSE2: [[BC:%.*]] = bitcast i32* %p to <8 x i32>*
30 ; SSE2-NEXT: [[LD:%.*]] = load <8 x i32>, <8 x i32>* [[BC]], align 4
31 ; SSE2: [[RDX_SHUF:%.*]] = shufflevector <8 x i32> [[LD]], <8 x i32> undef, <8 x i32>
32 ; SSE2-NEXT: [[BIN_RDX:%.*]] = add <8 x i32> [[LD]], [[RDX_SHUF]]
33 ; SSE2-NEXT: [[RDX_SHUF1:%.*]] = shufflevector <8 x i32> [[BIN_RDX]], <8 x i32> undef, <8 x i32>
34 ; SSE2-NEXT: [[BIN_RDX2:%.*]] = add <8 x i32> [[BIN_RDX]], [[RDX_SHUF1]]
35 ; SSE2-NEXT: [[RDX_SHUF3:%.*]] = shufflevector <8 x i32> [[BIN_RDX2]], <8 x i32> undef, <8 x i32>
36 ; SSE2-NEXT: [[BIN_RDX4:%.*]] = add <8 x i32> [[BIN_RDX2]], [[RDX_SHUF3]]
37 ; SSE2-NEXT: [[TMP2:%.*]] = extractelement <8 x i32> [[BIN_RDX4]], i32 0
38 ; SSE2: ret i32 [[TMP2]]
3922 ;
4023 entry:
4124 %0 = load i32, i32* %p, align 4