llvm.org GIT mirror llvm / 7d5a61e
For 64-bit the rest of the general regs are ok for the q constraint. Make sure we can emit both the high and low versions of those registers. Fixes rdar://10392864 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145579 91177308-0d34-0410-b5e6-96231b3b80d8 Eric Christopher 8 years ago
2 changed file(s) with 24 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
664664 case MVT::i8:
665665 if (High) {
666666 switch (Reg) {
667 default: return 0;
667 default: return getX86SubSuperRegister(Reg, MVT::i64, High);
668668 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
669669 return X86::AH;
670670 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
784784 return X86::R15D;
785785 }
786786 case MVT::i64:
787 // For 64-bit mode if we've requested a "high" register and the
788 // Q or r constraints we want one of these high registers or
789 // just the register name otherwise.
790 if (High) {
791 switch (Reg) {
792 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
793 return X86::SI;
794 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
795 return X86::DI;
796 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
797 return X86::BP;
798 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
799 return X86::SP;
800 // Fallthrough.
801 }
802 }
787803 switch (Reg) {
788804 default: return Reg;
789805 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1919 call void asm sideeffect "$0", "q"(double %tmp) nounwind
2020 ret void
2121 }
22
23 ; rdar://10392864
24 define void @test4(i8 signext %val, i8 signext %a, i8 signext %b, i8 signext %c, i8 signext %d) nounwind {
25 entry:
26 %0 = tail call { i8, i8, i8, i8, i8 } asm "foo $1, $2, $3, $4, $1\0Axchgb ${0:b}, ${0:h}", "=q,={ax},={bx},={cx},={dx},0,1,2,3,4,~{dirflag},~{fpsr},~{flags}"(i8 %val, i8 %a, i8 %b, i8 %c, i8 %d) nounwind
27 ret void
28 }