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[SelectionDAG] Remove ISD::FP_ROUND_INREG I don't think anything in tree creates this node. So all of this code appears to be dead. Code coverage agrees http://lab.llvm.org:8080/coverage/coverage-reports/llvm/coverage/Users/buildslave/jenkins/workspace/clang-stage2-coverage-R/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp.html Differential Revision: https://reviews.llvm.org/D67312 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371431 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper a month ago
10 changed file(s) with 3 addition(s) and 68 deletion(s). Raw diff Collapse all Expand all
3838 point (e.g. maybe you would like to give an example of the
3939 functionality, or simply have a lot to talk about), see the `NOTE` below
4040 for adding a new subsection.
41
42 * The ISD::FP_ROUND_INREG opcode and related code was removed from SelectionDAG.
4143
4244 .. NOTE
4345 If you would like to document a larger change, then you can add a
574574 /// 2 Round to +inf
575575 /// 3 Round to -inf
576576 FLT_ROUNDS_,
577
578 /// X = FP_ROUND_INREG(Y, VT) - This operator takes an FP register, and
579 /// rounds it to a floating point value. It then promotes it and returns it
580 /// in a register of the same size. This operation effectively just
581 /// discards excess precision. The type to round down to is specified by
582 /// the VT operand, a VTSDNode.
583 FP_ROUND_INREG,
584577
585578 /// X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
586579 FP_EXTEND,
439439 SDValue visitFP_TO_SINT(SDNode *N);
440440 SDValue visitFP_TO_UINT(SDNode *N);
441441 SDValue visitFP_ROUND(SDNode *N);
442 SDValue visitFP_ROUND_INREG(SDNode *N);
443442 SDValue visitFP_EXTEND(SDNode *N);
444443 SDValue visitFNEG(SDNode *N);
445444 SDValue visitFABS(SDNode *N);
18131812 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N);
18141813 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N);
18151814 case ISD::FP_ROUND: return visitFP_ROUND(N);
1816 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N);
18171815 case ISD::FP_EXTEND: return visitFP_EXTEND(N);
18181816 case ISD::FNEG: return visitFNEG(N);
18191817 case ISD::FABS: return visitFABS(N);
1314613144
1314713145 if (SDValue NewVSel = matchVSelectOpSizesWithSetCC(N))
1314813146 return NewVSel;
13149
13150 return SDValue();
13151 }
13152
13153 SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
13154 SDValue N0 = N->getOperand(0);
13155 EVT VT = N->getValueType(0);
13156 EVT EVT = cast(N->getOperand(1))->getVT();
13157 ConstantFPSDNode *N0CFP = dyn_cast(N0);
13158
13159 // fold (fp_round_inreg c1fp) -> c1fp
13160 if (N0CFP && isTypeLegal(EVT)) {
13161 SDLoc DL(N);
13162 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), DL, EVT);
13163 return DAG.getNode(ISD::FP_EXTEND, DL, VT, Round);
13164 }
1316513147
1316613148 return SDValue();
1316713149 }
10121012 Action = TLI.getOperationAction(Node->getOpcode(),
10131013 Node->getOperand(0).getValueType());
10141014 break;
1015 case ISD::FP_ROUND_INREG:
10161015 case ISD::SIGN_EXTEND_INREG: {
10171016 EVT InnerType = cast(Node->getOperand(1))->getVT();
10181017 Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
28612860 Results.push_back(Tmp1);
28622861 break;
28632862 }
2864 case ISD::FP_ROUND_INREG: {
2865 // The only way we can lower this is to turn it into a TRUNCSTORE,
2866 // EXTLOAD pair, targeting a temporary location (a stack slot).
2867
2868 // NOTE: there is a choice here between constantly creating new stack
2869 // slots and always reusing the same one. We currently always create
2870 // new ones, as reuse may inhibit scheduling.
2871 EVT ExtraVT = cast(Node->getOperand(1))->getVT();
2872 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
2873 Node->getValueType(0), dl);
2874 Results.push_back(Tmp1);
2875 break;
2876 }
28772863 case ISD::UINT_TO_FP:
28782864 if (TLI.expandUINT_TO_FP(Node, Tmp1, DAG)) {
28792865 Results.push_back(Tmp1);
458458 Node->getValueType(0), Scale);
459459 break;
460460 }
461 case ISD::FP_ROUND_INREG:
462 Action = TLI.getOperationAction(Node->getOpcode(),
463 cast(Node->getOperand(1))->getVT());
464 break;
465461 case ISD::SINT_TO_FP:
466462 case ISD::UINT_TO_FP:
467463 case ISD::VECREDUCE_ADD:
5151 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break;
5252 case ISD::STRICT_FP_ROUND: R = ScalarizeVecRes_STRICT_FP_ROUND(N); break;
5353 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break;
54 case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break;
5554 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break;
5655 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break;
5756 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast(N));break;
851850 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
852851 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
853852 case ISD::INSERT_SUBVECTOR: SplitVecRes_INSERT_SUBVECTOR(N, Lo, Hi); break;
854 case ISD::FP_ROUND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
855853 case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
856854 case ISD::FCOPYSIGN: SplitVecRes_FCOPYSIGN(N, Lo, Hi); break;
857855 case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
27072705 case ISD::BUILD_VECTOR: Res = WidenVecRes_BUILD_VECTOR(N); break;
27082706 case ISD::CONCAT_VECTORS: Res = WidenVecRes_CONCAT_VECTORS(N); break;
27092707 case ISD::EXTRACT_SUBVECTOR: Res = WidenVecRes_EXTRACT_SUBVECTOR(N); break;
2710 case ISD::FP_ROUND_INREG: Res = WidenVecRes_InregOp(N); break;
27112708 case ISD::INSERT_VECTOR_ELT: Res = WidenVecRes_INSERT_VECTOR_ELT(N); break;
27122709 case ISD::LOAD: Res = WidenVecRes_LOAD(N); break;
27132710 case ISD::SCALAR_TO_VECTOR: Res = WidenVecRes_SCALAR_TO_VECTOR(N); break;
51535153 if (N2C && N2C->isNullValue())
51545154 return N1;
51555155 break;
5156 case ISD::FP_ROUND_INREG: {
5157 EVT EVT = cast(N2)->getVT();
5158 assert(VT == N1.getValueType() && "Not an inreg round!");
5159 assert(VT.isFloatingPoint() && EVT.isFloatingPoint() &&
5160 "Cannot FP_ROUND_INREG integer types");
5161 assert(EVT.isVector() == VT.isVector() &&
5162 "FP_ROUND_INREG type should be vector iff the operand "
5163 "type is vector!");
5164 assert((!EVT.isVector() ||
5165 EVT.getVectorNumElements() == VT.getVectorNumElements()) &&
5166 "Vector element counts must match in FP_ROUND_INREG");
5167 assert(EVT.bitsLE(VT) && "Not rounding down!");
5168 (void)EVT;
5169 if (cast(N2)->getVT() == VT) return N1; // Not actually rounding.
5170 break;
5171 }
51725156 case ISD::FP_ROUND:
51735157 assert(VT.isFloatingPoint() &&
51745158 N1.getValueType().isFloatingPoint() &&
53795363 std::swap(N1, N2);
53805364 } else {
53815365 switch (Opcode) {
5382 case ISD::FP_ROUND_INREG:
53835366 case ISD::SIGN_EXTEND_INREG:
53845367 case ISD::SUB:
53855368 return getUNDEF(VT); // fold op(undef, arg2) -> undef
91569139 getShiftAmountOperand(Operands[0].getValueType(),
91579140 Operands[1])));
91589141 break;
9159 case ISD::SIGN_EXTEND_INREG:
9160 case ISD::FP_ROUND_INREG: {
9142 case ISD::SIGN_EXTEND_INREG: {
91619143 EVT ExtVT = cast(Operands[1])->getVT().getVectorElementType();
91629144 Scalars.push_back(getNode(N->getOpcode(), dl, EltVT,
91639145 Operands[0],
318318 case ISD::FP_ROUND: return "fp_round";
319319 case ISD::STRICT_FP_ROUND: return "strict_fp_round";
320320 case ISD::FLT_ROUNDS_: return "flt_rounds";
321 case ISD::FP_ROUND_INREG: return "fp_round_inreg";
322321 case ISD::FP_EXTEND: return "fp_extend";
323322 case ISD::STRICT_FP_EXTEND: return "strict_fp_extend";
324323
949949 setOperationAction(ISD::FP_TO_UINT , MVT::v4f64, Expand);
950950
951951 setOperationAction(ISD::FP_ROUND , MVT::v4f32, Legal);
952 setOperationAction(ISD::FP_ROUND_INREG , MVT::v4f32, Expand);
953952 setOperationAction(ISD::FP_EXTEND, MVT::v4f64, Legal);
954953
955954 setOperationAction(ISD::FNEG , MVT::v4f64, Legal);
325325 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
326326 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
327327 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
328 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
329328
330329 setOperationAction(ISD::FREM , MVT::f32 , Expand);
331330 setOperationAction(ISD::FREM , MVT::f64 , Expand);