llvm.org GIT mirror llvm / 7d2bb38
Add an x86 prefix encoding for instructions that would decode to a different instruction with 0xf2/f3/66 were in front of them, but don't themselves have a prefix. For now this doesn't change any bbehavior, but plan to use it to fix some bugs in the disassembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201538 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 5 years ago
9 changed file(s) with 214 addition(s) and 186 deletion(s). Raw diff Collapse all Expand all
334334 // no prefix.
335335 //
336336 OpPrefixShift = 9,
337 OpPrefixMask = 0x3 << OpPrefixShift,
338
339 // PD - Prefix code for packed double precision vector floating point
340 // operations performed in the SSE registers.
341 PD = 1 << OpPrefixShift,
337 OpPrefixMask = 0x7 << OpPrefixShift,
338
339 // PS, PD - Prefix code for packed single and double precision vector
340 // floating point operations performed in the SSE registers.
341 PS = 1 << OpPrefixShift, PD = 2 << OpPrefixShift,
342342
343343 // XS, XD - These prefix codes are for single and double precision scalar
344344 // floating point operations performed in the SSE registers.
345 XS = 2 << OpPrefixShift, XD = 3 << OpPrefixShift,
345 XS = 3 << OpPrefixShift, XD = 4 << OpPrefixShift,
346346
347347 //===------------------------------------------------------------------===//
348348 // OpMap - This field determines which opcode map this instruction
349349 // belongs to. i.e. one-byte, two-byte, 0x0f 0x38, 0x0f 0x3a, etc.
350350 //
351 OpMapShift = OpPrefixShift + 2,
351 OpMapShift = OpPrefixShift + 3,
352352 OpMapMask = 0x1f << OpMapShift,
353353
354354 // OB - OneByte - Set if this instruction has a one byte opcode.
849849 }
850850
851851 defm VCMPPSZ : avx512_cmp_packed
852 "ps", SSEPackedSingle>, TB, EVEX_4V, EVEX_V512,
852 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
853853 EVEX_CD8<32, CD8VF>;
854854 defm VCMPPDZ : avx512_cmp_packed
855855 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
929929
930930 let Predicates = [HasAVX512] in {
931931 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
932 VEX, TB;
932 VEX, PS;
933933 defm KMOVW : avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
934 VEX, TB;
934 VEX, PS;
935935 }
936936
937937 let Predicates = [HasAVX512] in {
10041004 multiclass avx512_mask_unop_w opc, string OpcodeStr,
10051005 SDPatternOperator OpNode> {
10061006 defm W : avx512_mask_unop,
1007 VEX, TB;
1007 VEX, PS;
10081008 }
10091009
10101010 defm KNOT : avx512_mask_unop_w<0x44, "knot", not>;
10411041 multiclass avx512_mask_binop_w opc, string OpcodeStr,
10421042 SDPatternOperator OpNode> {
10431043 defm W : avx512_mask_binop,
1044 VEX_4V, VEX_L, TB;
1044 VEX_4V, VEX_L, PS;
10451045 }
10461046
10471047 def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
11391139
11401140 multiclass avx512_mask_testop_w opc, string OpcodeStr, SDNode OpNode> {
11411141 defm W : avx512_mask_testop,
1142 VEX, TB;
1142 VEX, PS;
11431143 }
11441144
11451145 defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
12311231
12321232 defm VMOVAPSZ : avx512_mov_packed<0x28, VR512, VK16WM, f512mem, alignedloadv16f32,
12331233 "vmovaps", SSEPackedSingle>,
1234 TB, EVEX_V512, EVEX_CD8<32, CD8VF>;
1234 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
12351235 defm VMOVAPDZ : avx512_mov_packed<0x28, VR512, VK8WM, f512mem, alignedloadv8f64,
12361236 "vmovapd", SSEPackedDouble>,
12371237 PD, EVEX_V512, VEX_W,
12381238 EVEX_CD8<64, CD8VF>;
12391239 defm VMOVUPSZ : avx512_mov_packed<0x10, VR512, VK16WM, f512mem, loadv16f32,
12401240 "vmovups", SSEPackedSingle>,
1241 TB, EVEX_V512, EVEX_CD8<32, CD8VF>;
1241 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
12421242 defm VMOVUPDZ : avx512_mov_packed<0x10, VR512, VK8WM, f512mem, loadv8f64,
12431243 "vmovupd", SSEPackedDouble, 0>,
12441244 PD, EVEX_V512, VEX_W,
12461246 def VMOVAPSZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
12471247 "vmovaps\t{$src, $dst|$dst, $src}",
12481248 [(alignedstore512 (v16f32 VR512:$src), addr:$dst)],
1249 SSEPackedSingle>, EVEX, EVEX_V512, TB, EVEX_CD8<32, CD8VF>;
1249 SSEPackedSingle>, EVEX, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
12501250 def VMOVAPDZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
12511251 "vmovapd\t{$src, $dst|$dst, $src}",
12521252 [(alignedstore512 (v8f64 VR512:$src), addr:$dst)],
12551255 def VMOVUPSZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
12561256 "vmovups\t{$src, $dst|$dst, $src}",
12571257 [(store (v16f32 VR512:$src), addr:$dst)],
1258 SSEPackedSingle>, EVEX, EVEX_V512, TB, EVEX_CD8<32, CD8VF>;
1258 SSEPackedSingle>, EVEX, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
12591259 def VMOVUPDZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
12601260 "vmovupd\t{$src, $dst|$dst, $src}",
12611261 [(store (v8f64 VR512:$src), addr:$dst)],
19011901
19021902 defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
19031903 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1904 SSEPackedSingle>, TB, EVEX_V512, EVEX_CD8<32, CD8VF>;
1904 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
19051905 defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
19061906 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
19071907 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
19081908 defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
19091909 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1910 SSEPackedSingle>, TB, EVEX_V512, EVEX_CD8<32, CD8VF>;
1910 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
19111911 defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
19121912 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
19131913 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
20612061
20622062 defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VR512, v16f32, f512mem,
20632063 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2064 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, TB, EVEX_CD8<32, CD8VF>;
2064 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
20652065
20662066 defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VR512, v8f64, f512mem,
20672067 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
20702070
20712071 defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VR512, v16f32, f512mem,
20722072 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2073 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, TB, EVEX_CD8<32, CD8VF>;
2073 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
20742074 defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VR512, v8f64, f512mem,
20752075 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
20762076 SSE_ALU_ITINS_P.d, 1>,
20792079 defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VR512, v16f32, f512mem,
20802080 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
20812081 SSE_ALU_ITINS_P.s, 1>,
2082 EVEX_V512, TB, EVEX_CD8<32, CD8VF>;
2082 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
20832083 defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VR512, v16f32, f512mem,
20842084 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
20852085 SSE_ALU_ITINS_P.s, 1>,
2086 EVEX_V512, TB, EVEX_CD8<32, CD8VF>;
2086 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
20872087
20882088 defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VR512, v8f64, f512mem,
20892089 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
20962096
20972097 defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VR512, v16f32, f512mem,
20982098 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2099 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, TB, EVEX_CD8<32, CD8VF>;
2099 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
21002100 defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VR512, v16f32, f512mem,
21012101 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2102 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, TB, EVEX_CD8<32, CD8VF>;
2102 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
21032103
21042104 defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VR512, v8f64, f512mem,
21052105 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
28832883
28842884 defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
28852885 memopv4f64, f256mem, v8f64, v8f32,
2886 SSEPackedDouble>, EVEX_V512, TB,
2886 SSEPackedDouble>, EVEX_V512, PS,
28872887 EVEX_CD8<32, CD8VH>;
28882888 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
28892889 (VCVTPS2PDZrm addr:$src)>;
29022902
29032903 defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
29042904 memopv8i64, i512mem, v16f32, v16i32,
2905 SSEPackedSingle>, EVEX_V512, TB,
2905 SSEPackedSingle>, EVEX_V512, PS,
29062906 EVEX_CD8<32, CD8VF>;
29072907
29082908 defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
29222922
29232923 defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
29242924 memopv16f32, f512mem, v16i32, v16f32,
2925 SSEPackedSingle>, EVEX_V512, TB,
2925 SSEPackedSingle>, EVEX_V512, PS,
29262926 EVEX_CD8<32, CD8VF>;
29272927
29282928 // cvttps2udq (src, 0, mask-all-ones, sae-current)
29322932
29332933 defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
29342934 memopv8f64, f512mem, v8i32, v8f64,
2935 SSEPackedDouble>, EVEX_V512, TB, VEX_W,
2935 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
29362936 EVEX_CD8<64, CD8VF>;
29372937
29382938 // cvttpd2udq (src, 0, mask-all-ones, sae-current)
30023002
30033003 defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
30043004 memopv16f32, f512mem, SSEPackedSingle>,
3005 TB, EVEX_V512, EVEX_CD8<32, CD8VF>;
3005 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
30063006 defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
30073007 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
3008 TB, EVEX_V512, EVEX_CD8<64, CD8VF>;
3008 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
30093009
30103010 def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
30113011 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
30623062
30633063 let Defs = [EFLAGS], Predicates = [HasAVX512] in {
30643064 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
3065 "ucomiss">, TB, EVEX, VEX_LIG,
3065 "ucomiss">, PS, EVEX, VEX_LIG,
30663066 EVEX_CD8<32, CD8VT1>;
30673067 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
30683068 "ucomisd">, PD, EVEX,
30693069 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
30703070 let Pattern = [] in {
30713071 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
3072 "comiss">, TB, EVEX, VEX_LIG,
3072 "comiss">, PS, EVEX, VEX_LIG,
30733073 EVEX_CD8<32, CD8VT1>;
30743074 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
30753075 "comisd">, PD, EVEX,
30773077 }
30783078 let isCodeGenOnly = 1 in {
30793079 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
3080 load, "ucomiss">, TB, EVEX, VEX_LIG,
3080 load, "ucomiss">, PS, EVEX, VEX_LIG,
30813081 EVEX_CD8<32, CD8VT1>;
30823082 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
30833083 load, "ucomisd">, PD, EVEX,
30843084 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
30853085
30863086 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
3087 load, "comiss">, TB, EVEX, VEX_LIG,
3087 load, "comiss">, PS, EVEX, VEX_LIG,
30883088 EVEX_CD8<32, CD8VT1>;
30893089 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
30903090 load, "comisd">, PD, EVEX,
38403840 }
38413841
38423842 defm VSHUFPSZ : avx512_shufp
3843 SSEPackedSingle>, TB, EVEX_V512, EVEX_CD8<32, CD8VF>;
3843 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
38443844 defm VSHUFPDZ : avx512_shufp
38453845 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
38463846
13101310 }
13111311
13121312 let Predicates = [HasBMI], Defs = [EFLAGS] in {
1313 defm ANDN32 : bmi_andn<"andn{l}", GR32, i32mem, loadi32>, T8, VEX_4V;
1314 defm ANDN64 : bmi_andn<"andn{q}", GR64, i64mem, loadi64>, T8, VEX_4V, VEX_W;
1313 defm ANDN32 : bmi_andn<"andn{l}", GR32, i32mem, loadi32>, T8PS, VEX_4V;
1314 defm ANDN64 : bmi_andn<"andn{q}", GR64, i64mem, loadi64>, T8PS, VEX_4V, VEX_W;
13151315 }
13161316
13171317 let Predicates = [HasBMI] in {
113113 def CD8VT8 : CD8VForm<7>; // v := 8
114114
115115 // Class specifying the prefix used an opcode extension.
116 class Prefix val> {
117 bits<2> Value = val;
116 class Prefix val> {
117 bits<3> Value = val;
118118 }
119119 def NoPrfx : Prefix<0>;
120 def PD : Prefix<1>;
121 def XS : Prefix<2>;
122 def XD : Prefix<3>;
120 def PS : Prefix<1>;
121 def PD : Prefix<2>;
122 def XS : Prefix<3>;
123 def XD : Prefix<4>;
123124
124125 // Class specifying the opcode map.
125126 class Map val> {
181182 class TA { Map OpMap = TA; }
182183 class A6 { Map OpMap = A6; }
183184 class A7 { Map OpMap = A7; }
184 class XOP8 { Map OpMap = XOP8; }
185 class XOP9 { Map OpMap = XOP9; }
186 class XOPA { Map OpMap = XOPA; }
185 class XOP8 { Map OpMap = XOP8; Prefix OpPrefix = PS; }
186 class XOP9 { Map OpMap = XOP9; Prefix OpPrefix = PS; }
187 class XOPA { Map OpMap = XOPA; Prefix OpPrefix = PS; }
188 class PS : TB { Prefix OpPrefix = PS; }
187189 class PD : TB { Prefix OpPrefix = PD; }
188190 class XD : TB { Prefix OpPrefix = XD; }
189191 class XS : TB { Prefix OpPrefix = XS; }
192 class T8PS : T8 { Prefix OpPrefix = PS; }
190193 class T8PD : T8 { Prefix OpPrefix = PD; }
191194 class T8XD : T8 { Prefix OpPrefix = XD; }
192195 class T8XS : T8 { Prefix OpPrefix = XS; }
196 class TAPS : TA { Prefix OpPrefix = PS; }
193197 class TAPD : TA { Prefix OpPrefix = PD; }
194198 class TAXD : TA { Prefix OpPrefix = XD; }
195199 class VEX { Encoding OpEnc = EncVEX; }
281285 let TSFlags{5-0} = FormBits;
282286 let TSFlags{7-6} = OpSize.Value;
283287 let TSFlags{8} = hasAdSizePrefix;
284 let TSFlags{10-9} = OpPrefix.Value;
285 let TSFlags{15-11} = OpMap.Value;
286 let TSFlags{16} = hasREX_WPrefix;
287 let TSFlags{20-17} = ImmT.Value;
288 let TSFlags{23-21} = FPForm.Value;
289 let TSFlags{24} = hasLockPrefix;
290 let TSFlags{25} = hasREPPrefix;
291 let TSFlags{27-26} = ExeDomain.Value;
292 let TSFlags{29-28} = OpEnc.Value;
293 let TSFlags{37-30} = Opcode;
294 let TSFlags{38} = hasVEX_WPrefix;
295 let TSFlags{39} = hasVEX_4V;
296 let TSFlags{40} = hasVEX_4VOp3;
297 let TSFlags{41} = hasVEX_i8ImmReg;
298 let TSFlags{42} = hasVEX_L;
299 let TSFlags{43} = ignoresVEX_L;
300 let TSFlags{44} = hasEVEX_K;
301 let TSFlags{45} = hasEVEX_Z;
302 let TSFlags{46} = hasEVEX_L2;
303 let TSFlags{47} = hasEVEX_B;
304 let TSFlags{49-48} = EVEX_CD8E;
305 let TSFlags{52-50} = EVEX_CD8V;
306 let TSFlags{53} = has3DNow0F0FOpcode;
307 let TSFlags{54} = hasMemOp4Prefix;
308 let TSFlags{55} = hasEVEX_RC;
288 let TSFlags{11-9} = OpPrefix.Value;
289 let TSFlags{16-12} = OpMap.Value;
290 let TSFlags{17} = hasREX_WPrefix;
291 let TSFlags{21-18} = ImmT.Value;
292 let TSFlags{24-22} = FPForm.Value;
293 let TSFlags{25} = hasLockPrefix;
294 let TSFlags{26} = hasREPPrefix;
295 let TSFlags{28-27} = ExeDomain.Value;
296 let TSFlags{30-29} = OpEnc.Value;
297 let TSFlags{38-31} = Opcode;
298 let TSFlags{39} = hasVEX_WPrefix;
299 let TSFlags{40} = hasVEX_4V;
300 let TSFlags{41} = hasVEX_4VOp3;
301 let TSFlags{42} = hasVEX_i8ImmReg;
302 let TSFlags{43} = hasVEX_L;
303 let TSFlags{44} = ignoresVEX_L;
304 let TSFlags{45} = hasEVEX_K;
305 let TSFlags{46} = hasEVEX_Z;
306 let TSFlags{47} = hasEVEX_L2;
307 let TSFlags{48} = hasEVEX_B;
308 let TSFlags{50-49} = EVEX_CD8E;
309 let TSFlags{53-51} = EVEX_CD8V;
310 let TSFlags{54} = has3DNow0F0FOpcode;
311 let TSFlags{55} = hasMemOp4Prefix;
312 let TSFlags{56} = hasEVEX_RC;
309313 }
310314
311315 class PseudoI pattern>
473477 // SSE1 Instruction Templates:
474478 //
475479 // SSI - SSE1 instructions with XS prefix.
476 // PSI - SSE1 instructions with TB prefix.
477 // PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
480 // PSI - SSE1 instructions with PS prefix.
481 // PSIi8 - SSE1 instructions with ImmT == Imm8 and PS prefix.
478482 // VSSI - SSE1 instructions with XS prefix in AVX form.
479 // VPSI - SSE1 instructions with TB prefix in AVX form, packed single.
483 // VPSI - SSE1 instructions with PS prefix in AVX form, packed single.
480484
481485 class SSI o, Format F, dag outs, dag ins, string asm,
482486 list pattern, InstrItinClass itin = NoItinerary>
486490 : Ii8, XS, Requires<[UseSSE1]>;
487491 class PSI o, Format F, dag outs, dag ins, string asm,
488492 list pattern, InstrItinClass itin = NoItinerary>
489 : I, TB,
493 : I, PS,
490494 Requires<[UseSSE1]>;
491495 class PSIi8 o, Format F, dag outs, dag ins, string asm,
492496 list pattern, InstrItinClass itin = NoItinerary>
493 : Ii8, TB,
497 : Ii8, PS,
494498 Requires<[UseSSE1]>;
495499 class VSSI o, Format F, dag outs, dag ins, string asm,
496500 list pattern, InstrItinClass itin = NoItinerary>
498502 Requires<[HasAVX]>;
499503 class VPSI o, Format F, dag outs, dag ins, string asm,
500504 list pattern, InstrItinClass itin = NoItinerary>
501 : I, TB,
505 : I, PS,
502506 Requires<[HasAVX]>;
503507
504508 // SSE2 Instruction Templates:
682686 // AVX5128I - AVX-512 instructions with T8PD prefix.
683687 // AVX512AIi8 - AVX-512 instructions with TAPD prefix and ImmT = Imm8.
684688 // AVX512PDI - AVX-512 instructions with PD, double packed.
685 // AVX512PSI - AVX-512 instructions with TB, single packed.
689 // AVX512PSI - AVX-512 instructions with PS, single packed.
686690 // AVX512XS8I - AVX-512 instructions with T8 and XS prefixes.
687691 // AVX512XSI - AVX-512 instructions with XS prefix, generic domain.
688692 // AVX512BI - AVX-512 instructions with PD, int packed domain.
726730 Requires<[HasAVX512]>;
727731 class AVX512PSI o, Format F, dag outs, dag ins, string asm,
728732 list pattern, InstrItinClass itin = NoItinerary>
729 : I, TB,
733 : I, PS,
730734 Requires<[HasAVX512]>;
731735 class AVX512PIi8 o, Format F, dag outs, dag ins, string asm,
732736 list pattern, Domain d, InstrItinClass itin = NoItinerary>
853857 // MMXI32 - MMX instructions with TB prefix valid only in 32 bit mode.
854858 // MMXI64 - MMX instructions with TB prefix valid only in 64 bit mode.
855859 // MMX2I - MMX / SSE2 instructions with PD prefix.
856 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
857 // MMXIi8 - MMX instructions with ImmT == Imm8 and TB prefix.
860 // MMXIi8 - MMX instructions with ImmT == Imm8 and PS prefix.
861 // MMXIi8 - MMX instructions with ImmT == Imm8 and PS prefix.
858862 // MMXID - MMX instructions with XD prefix.
859863 // MMXIS - MMX instructions with XS prefix.
860864 class MMXI o, Format F, dag outs, dag ins, string asm,
861865 list pattern, InstrItinClass itin = NoItinerary>
862 : I, TB, Requires<[HasMMX]>;
866 : I, PS, Requires<[HasMMX]>;
863867 class MMXI32 o, Format F, dag outs, dag ins, string asm,
864868 list pattern, InstrItinClass itin = NoItinerary>
865 : I, TB, Requires<[HasMMX,Not64BitMode]>;
869 : I, PS, Requires<[HasMMX,Not64BitMode]>;
866870 class MMXI64 o, Format F, dag outs, dag ins, string asm,
867871 list pattern, InstrItinClass itin = NoItinerary>
868 : I, TB, Requires<[HasMMX,In64BitMode]>;
872 : I, PS, Requires<[HasMMX,In64BitMode]>;
869873 class MMXRI o, Format F, dag outs, dag ins, string asm,
870874 list pattern, InstrItinClass itin = NoItinerary>
871 : I, TB, REX_W, Requires<[HasMMX]>;
875 : I, PS, REX_W, Requires<[HasMMX]>;
872876 class MMX2I o, Format F, dag outs, dag ins, string asm,
873877 list pattern, InstrItinClass itin = NoItinerary>
874878 : I, PD, Requires<[HasMMX]>;
875879 class MMXIi8 o, Format F, dag outs, dag ins, string asm,
876880 list pattern, InstrItinClass itin = NoItinerary>
877 : Ii8, TB, Requires<[HasMMX]>;
881 : Ii8, PS, Requires<[HasMMX]>;
878882 class MMXID o, Format F, dag outs, dag ins, string asm,
879883 list pattern, InstrItinClass itin = NoItinerary>
880884 : Ii8, XD, Requires<[HasMMX]>;
10791079 def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
10801080 "bsf{w}\t{$src, $dst|$dst, $src}",
10811081 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))],
1082 IIC_BIT_SCAN_REG>, TB, OpSize16, Sched<[WriteShift]>;
1082 IIC_BIT_SCAN_REG>, PS, OpSize16, Sched<[WriteShift]>;
10831083 def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
10841084 "bsf{w}\t{$src, $dst|$dst, $src}",
10851085 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))],
1086 IIC_BIT_SCAN_MEM>, TB, OpSize16, Sched<[WriteShiftLd]>;
1086 IIC_BIT_SCAN_MEM>, PS, OpSize16, Sched<[WriteShiftLd]>;
10871087 def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
10881088 "bsf{l}\t{$src, $dst|$dst, $src}",
10891089 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))],
1090 IIC_BIT_SCAN_REG>, TB, OpSize32,
1091 Sched<[WriteShift]>;
1090 IIC_BIT_SCAN_REG>, PS, OpSize32, Sched<[WriteShift]>;
10921091 def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
10931092 "bsf{l}\t{$src, $dst|$dst, $src}",
10941093 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))],
1095 IIC_BIT_SCAN_MEM>, TB, OpSize32, Sched<[WriteShiftLd]>;
1094 IIC_BIT_SCAN_MEM>, PS, OpSize32, Sched<[WriteShiftLd]>;
10961095 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
10971096 "bsf{q}\t{$src, $dst|$dst, $src}",
10981097 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))],
1099 IIC_BIT_SCAN_REG>, TB, Sched<[WriteShift]>;
1098 IIC_BIT_SCAN_REG>, PS, Sched<[WriteShift]>;
11001099 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
11011100 "bsf{q}\t{$src, $dst|$dst, $src}",
11021101 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))],
1103 IIC_BIT_SCAN_MEM>, TB, Sched<[WriteShiftLd]>;
1102 IIC_BIT_SCAN_MEM>, PS, Sched<[WriteShiftLd]>;
11041103
11051104 def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
11061105 "bsr{w}\t{$src, $dst|$dst, $src}",
11071106 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))],
1108 IIC_BIT_SCAN_REG>,
1109 TB, OpSize16, Sched<[WriteShift]>;
1107 IIC_BIT_SCAN_REG>, PS, OpSize16, Sched<[WriteShift]>;
11101108 def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
11111109 "bsr{w}\t{$src, $dst|$dst, $src}",
11121110 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))],
1113 IIC_BIT_SCAN_MEM>, TB,
1114 OpSize16, Sched<[WriteShiftLd]>;
1111 IIC_BIT_SCAN_MEM>, PS, OpSize16, Sched<[WriteShiftLd]>;
11151112 def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
11161113 "bsr{l}\t{$src, $dst|$dst, $src}",
11171114 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))],
1118 IIC_BIT_SCAN_REG>, TB, OpSize32,
1119 Sched<[WriteShift]>;
1115 IIC_BIT_SCAN_REG>, PS, OpSize32, Sched<[WriteShift]>;
11201116 def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
11211117 "bsr{l}\t{$src, $dst|$dst, $src}",
11221118 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))],
1123 IIC_BIT_SCAN_MEM>, TB, OpSize32, Sched<[WriteShiftLd]>;
1119 IIC_BIT_SCAN_MEM>, PS, OpSize32, Sched<[WriteShiftLd]>;
11241120 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
11251121 "bsr{q}\t{$src, $dst|$dst, $src}",
1126 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))], IIC_BIT_SCAN_REG>, TB,
1127 Sched<[WriteShift]>;
1122 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))],
1123 IIC_BIT_SCAN_REG>, PS, Sched<[WriteShift]>;
11281124 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
11291125 "bsr{q}\t{$src, $dst|$dst, $src}",
11301126 [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))],
1131 IIC_BIT_SCAN_MEM>, TB, Sched<[WriteShiftLd]>;
1127 IIC_BIT_SCAN_MEM>, PS, Sched<[WriteShiftLd]>;
11321128 } // Defs = [EFLAGS]
11331129
11341130 let SchedRW = [WriteMicrocoded] in {
18651861 def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
18661862 "movbe{w}\t{$src, $dst|$dst, $src}",
18671863 [(set GR16:$dst, (bswap (loadi16 addr:$src)))], IIC_MOVBE>,
1868 OpSize16, T8;
1864 OpSize16, T8PS;
18691865 def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
18701866 "movbe{l}\t{$src, $dst|$dst, $src}",
18711867 [(set GR32:$dst, (bswap (loadi32 addr:$src)))], IIC_MOVBE>,
1872 OpSize32, T8;
1868 OpSize32, T8PS;
18731869 def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
18741870 "movbe{q}\t{$src, $dst|$dst, $src}",
18751871 [(set GR64:$dst, (bswap (loadi64 addr:$src)))], IIC_MOVBE>,
1876 T8;
1872 T8PS;
18771873 }
18781874 let SchedRW = [WriteStore] in {
18791875 def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
18801876 "movbe{w}\t{$src, $dst|$dst, $src}",
18811877 [(store (bswap GR16:$src), addr:$dst)], IIC_MOVBE>,
1882 OpSize16, T8;
1878 OpSize16, T8PS;
18831879 def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
18841880 "movbe{l}\t{$src, $dst|$dst, $src}",
18851881 [(store (bswap GR32:$src), addr:$dst)], IIC_MOVBE>,
1886 OpSize32, T8;
1882 OpSize32, T8PS;
18871883 def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
18881884 "movbe{q}\t{$src, $dst|$dst, $src}",
18891885 [(store (bswap GR64:$src), addr:$dst)], IIC_MOVBE>,
1890 T8;
1886 T8PS;
18911887 }
18921888 }
18931889
19901986 let hasSideEffects = 0 in {
19911987 def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src),
19921988 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
1993 []>, T8, VEX_4V;
1989 []>, T8PS, VEX_4V;
19941990 let mayLoad = 1 in
19951991 def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src),
19961992 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"),
1997 []>, T8, VEX_4V;
1993 []>, T8PS, VEX_4V;
19981994 }
19991995 }
20001996
20352031 def rr : I
20362032 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
20372033 [(set RC:$dst, (Int RC:$src1, RC:$src2)), (implicit EFLAGS)]>,
2038 T8, VEX_4VOp3;
2034 T8PS, VEX_4VOp3;
20392035 def rm : I
20402036 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
20412037 [(set RC:$dst, (Int (ld_frag addr:$src1), RC:$src2)),
2042 (implicit EFLAGS)]>, T8, VEX_4VOp3;
2038 (implicit EFLAGS)]>, T8PS, VEX_4VOp3;
20432039 }
20442040
20452041 let Predicates = [HasBMI], Defs = [EFLAGS] in {
523523 // -- Conversion Instructions
524524 defm MMX_CVTPS2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtps2pi,
525525 f64mem, load, "cvtps2pi\t{$src, $dst|$dst, $src}",
526 MMX_CVT_PS_ITINS, SSEPackedSingle>, TB;
526 MMX_CVT_PS_ITINS, SSEPackedSingle>, PS;
527527 defm MMX_CVTPD2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtpd2pi,
528528 f128mem, memop, "cvtpd2pi\t{$src, $dst|$dst, $src}",
529529 MMX_CVT_PD_ITINS, SSEPackedDouble>, PD;
530530 defm MMX_CVTTPS2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttps2pi,
531531 f64mem, load, "cvttps2pi\t{$src, $dst|$dst, $src}",
532 MMX_CVT_PS_ITINS, SSEPackedSingle>, TB;
532 MMX_CVT_PS_ITINS, SSEPackedSingle>, PS;
533533 defm MMX_CVTTPD2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttpd2pi,
534534 f128mem, memop, "cvttpd2pi\t{$src, $dst|$dst, $src}",
535535 MMX_CVT_PD_ITINS, SSEPackedDouble>, PD;
540540 defm MMX_CVTPI2PS : sse12_cvt_pint_3addr<0x2A, VR64, VR128,
541541 int_x86_sse_cvtpi2ps,
542542 i64mem, load, "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
543 SSEPackedSingle>, TB;
543 SSEPackedSingle>, PS;
544544 }
545545
546546 // Extract / Insert
811811
812812 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
813813 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
814 TB, VEX;
814 PS, VEX;
815815 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
816816 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
817817 PD, VEX;
818818 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
819819 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
820 TB, VEX;
820 PS, VEX;
821821 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
822822 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
823823 PD, VEX;
824824
825825 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
826826 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
827 TB, VEX, VEX_L;
827 PS, VEX, VEX_L;
828828 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
829829 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
830830 PD, VEX, VEX_L;
831831 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
832832 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
833 TB, VEX, VEX_L;
833 PS, VEX, VEX_L;
834834 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
835835 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
836836 PD, VEX, VEX_L;
837837 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
838838 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
839 TB;
839 PS;
840840 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
841841 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
842842 PD;
843843 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
844844 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
845 TB;
845 PS;
846846 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
847847 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
848848 PD;
11411141 [(set VR128:$dst,
11421142 (psnode VR128:$src1,
11431143 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
1144 itin, SSEPackedSingle>, TB,
1144 itin, SSEPackedSingle>, PS,
11451145 Sched<[WriteShuffleLd, ReadAfterLd]>;
11461146
11471147 def PDrm : PI
17201720 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
17211721 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
17221722 SSEPackedSingle, SSE_CVT_PS>,
1723 TB, VEX, Requires<[HasAVX]>;
1723 PS, VEX, Requires<[HasAVX]>;
17241724 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, i256mem,
17251725 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
17261726 SSEPackedSingle, SSE_CVT_PS>,
1727 TB, VEX, VEX_L, Requires<[HasAVX]>;
1727 PS, VEX, VEX_L, Requires<[HasAVX]>;
17281728
17291729 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
17301730 "cvtdq2ps\t{$src, $dst|$dst, $src}",
17311731 SSEPackedSingle, SSE_CVT_PS>,
1732 TB, Requires<[UseSSE2]>;
1732 PS, Requires<[UseSSE2]>;
17331733
17341734 let Predicates = [UseAVX] in {
17351735 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
21272127 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
21282128 "vcvtps2pd\t{$src, $dst|$dst, $src}",
21292129 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2130 IIC_SSE_CVT_PD_RR>, TB, VEX, Sched<[WriteCvtF2F]>;
2130 IIC_SSE_CVT_PD_RR>, PS, VEX, Sched<[WriteCvtF2F]>;
21312131 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
21322132 "vcvtps2pd\t{$src, $dst|$dst, $src}",
21332133 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2134 IIC_SSE_CVT_PD_RM>, TB, VEX, Sched<[WriteCvtF2FLd]>;
2134 IIC_SSE_CVT_PD_RM>, PS, VEX, Sched<[WriteCvtF2FLd]>;
21352135 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
21362136 "vcvtps2pd\t{$src, $dst|$dst, $src}",
21372137 [(set VR256:$dst,
21382138 (int_x86_avx_cvt_ps2_pd_256 VR128:$src))],
2139 IIC_SSE_CVT_PD_RR>, TB, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2139 IIC_SSE_CVT_PD_RR>, PS, VEX, VEX_L, Sched<[WriteCvtF2F]>;
21402140 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
21412141 "vcvtps2pd\t{$src, $dst|$dst, $src}",
21422142 [(set VR256:$dst,
21432143 (int_x86_avx_cvt_ps2_pd_256 (loadv4f32 addr:$src)))],
2144 IIC_SSE_CVT_PD_RM>, TB, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2144 IIC_SSE_CVT_PD_RM>, PS, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
21452145 }
21462146
21472147 let Predicates = [UseSSE2] in {
21482148 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
21492149 "cvtps2pd\t{$src, $dst|$dst, $src}",
21502150 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2151 IIC_SSE_CVT_PD_RR>, TB, Sched<[WriteCvtF2F]>;
2151 IIC_SSE_CVT_PD_RR>, PS, Sched<[WriteCvtF2F]>;
21522152 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
21532153 "cvtps2pd\t{$src, $dst|$dst, $src}",
21542154 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2155 IIC_SSE_CVT_PD_RM>, TB, Sched<[WriteCvtF2FLd]>;
2155 IIC_SSE_CVT_PD_RM>, PS, Sched<[WriteCvtF2FLd]>;
21562156 }
21572157
21582158 // Convert Packed DW Integers to Packed Double FP
23902390
23912391 let Defs = [EFLAGS] in {
23922392 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2393 "ucomiss">, TB, VEX, VEX_LIG;
2393 "ucomiss">, PS, VEX, VEX_LIG;
23942394 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
23952395 "ucomisd">, PD, VEX, VEX_LIG;
23962396 let Pattern = [] in {
23972397 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2398 "comiss">, TB, VEX, VEX_LIG;
2398 "comiss">, PS, VEX, VEX_LIG;
23992399 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
24002400 "comisd">, PD, VEX, VEX_LIG;
24012401 }
24022402
24032403 let isCodeGenOnly = 1 in {
24042404 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2405 load, "ucomiss">, TB, VEX;
2405 load, "ucomiss">, PS, VEX;
24062406 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
24072407 load, "ucomisd">, PD, VEX;
24082408
24092409 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2410 load, "comiss">, TB, VEX;
2410 load, "comiss">, PS, VEX;
24112411 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
24122412 load, "comisd">, PD, VEX;
24132413 }
24142414 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2415 "ucomiss">, TB;
2415 "ucomiss">, PS;
24162416 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
24172417 "ucomisd">, PD;
24182418
24192419 let Pattern = [] in {
24202420 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2421 "comiss">, TB;
2421 "comiss">, PS;
24222422 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
24232423 "comisd">, PD;
24242424 }
24252425
24262426 let isCodeGenOnly = 1 in {
24272427 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2428 load, "ucomiss">, TB;
2428 load, "ucomiss">, PS;
24292429 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
24302430 load, "ucomisd">, PD;
24312431
24322432 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2433 "comiss">, TB;
2433 "comiss">, PS;
24342434 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
24352435 "comisd">, PD;
24362436 }
24672467 defm VCMPPS : sse12_cmp_packed
24682468 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
24692469 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2470 SSEPackedSingle>, TB, VEX_4V;
2470 SSEPackedSingle>, PS, VEX_4V;
24712471 defm VCMPPD : sse12_cmp_packed
24722472 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
24732473 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
24752475 defm VCMPPSY : sse12_cmp_packed
24762476 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
24772477 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2478 SSEPackedSingle>, TB, VEX_4V, VEX_L;
2478 SSEPackedSingle>, PS, VEX_4V, VEX_L;
24792479 defm VCMPPDY : sse12_cmp_packed
24802480 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
24812481 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
24842484 defm CMPPS : sse12_cmp_packed
24852485 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
24862486 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2487 SSEPackedSingle, SSE_ALU_F32P>, TB;
2487 SSEPackedSingle, SSE_ALU_F32P>, PS;
24882488 defm CMPPD : sse12_cmp_packed
24892489 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
24902490 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
25482548
25492549 defm VSHUFPS : sse12_shuffle
25502550 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2551 loadv4f32, SSEPackedSingle>, TB, VEX_4V;
2551 loadv4f32, SSEPackedSingle>, PS, VEX_4V;
25522552 defm VSHUFPSY : sse12_shuffle
25532553 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2554 loadv8f32, SSEPackedSingle>, TB, VEX_4V, VEX_L;
2554 loadv8f32, SSEPackedSingle>, PS, VEX_4V, VEX_L;
25552555 defm VSHUFPD : sse12_shuffle
25562556 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
25572557 loadv2f64, SSEPackedDouble>, PD, VEX_4V;
25622562 let Constraints = "$src1 = $dst" in {
25632563 defm SHUFPS : sse12_shuffle
25642564 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2565 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>, TB;
2565 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>, PS;
25662566 defm SHUFPD : sse12_shuffle
25672567 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
25682568 memopv2f64, SSEPackedDouble, 1 /* cvt to pshufd */>, PD;
26372637
26382638 defm VUNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, loadv4f32,
26392639 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2640 SSEPackedSingle>, TB, VEX_4V;
2640 SSEPackedSingle>, PS, VEX_4V;
26412641 defm VUNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, loadv2f64,
26422642 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
26432643 SSEPackedDouble>, PD, VEX_4V;
26442644 defm VUNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, loadv4f32,
26452645 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2646 SSEPackedSingle>, TB, VEX_4V;
2646 SSEPackedSingle>, PS, VEX_4V;
26472647 defm VUNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, loadv2f64,
26482648 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
26492649 SSEPackedDouble>, PD, VEX_4V;
26502650
26512651 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, X86Unpckh, v8f32, loadv8f32,
26522652 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2653 SSEPackedSingle>, TB, VEX_4V, VEX_L;
2653 SSEPackedSingle>, PS, VEX_4V, VEX_L;
26542654 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, X86Unpckh, v4f64, loadv4f64,
26552655 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
26562656 SSEPackedDouble>, PD, VEX_4V, VEX_L;
26572657 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, X86Unpckl, v8f32, loadv8f32,
26582658 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2659 SSEPackedSingle>, TB, VEX_4V, VEX_L;
2659 SSEPackedSingle>, PS, VEX_4V, VEX_L;
26602660 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, X86Unpckl, v4f64, loadv4f64,
26612661 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
26622662 SSEPackedDouble>, PD, VEX_4V, VEX_L;
26642664 let Constraints = "$src1 = $dst" in {
26652665 defm UNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
26662666 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2667 SSEPackedSingle>, TB;
2667 SSEPackedSingle>, PS;
26682668 defm UNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
26692669 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
26702670 SSEPackedDouble>, PD;
26712671 defm UNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
26722672 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2673 SSEPackedSingle>, TB;
2673 SSEPackedSingle>, PS;
26742674 defm UNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
26752675 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
26762676 SSEPackedDouble>, PD;
27292729
27302730 let Predicates = [HasAVX] in {
27312731 defm VMOVMSKPS : sse12_extr_sign_mask
2732 "movmskps", SSEPackedSingle>, TB, VEX;
2732 "movmskps", SSEPackedSingle>, PS, VEX;
27332733 defm VMOVMSKPD : sse12_extr_sign_mask
27342734 "movmskpd", SSEPackedDouble>, PD, VEX;
27352735 defm VMOVMSKPSY : sse12_extr_sign_mask
2736 "movmskps", SSEPackedSingle>, TB,
2736 "movmskps", SSEPackedSingle>, PS,
27372737 VEX, VEX_L;
27382738 defm VMOVMSKPDY : sse12_extr_sign_mask
27392739 "movmskpd", SSEPackedDouble>, PD,
27522752 }
27532753
27542754 defm MOVMSKPS : sse12_extr_sign_mask
2755 SSEPackedSingle>, TB;
2755 SSEPackedSingle>, PS;
27562756 defm MOVMSKPD : sse12_extr_sign_mask
27572757 SSEPackedDouble>, PD;
27582758
28372837 SDNode OpNode, OpndItins itins> {
28382838 defm V#NAME#PS : sse12_fp_packed
28392839 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, itins, 0>,
2840 TB, VEX_4V;
2840 PS, VEX_4V;
28412841
28422842 defm V#NAME#PD : sse12_fp_packed
28432843 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, itins, 0>,
28462846 let Constraints = "$src1 = $dst" in {
28472847 defm PS : sse12_fp_packed
28482848 f32, f128mem, memopfsf32, SSEPackedSingle, itins>,
2849 TB;
2849 PS;
28502850
28512851 defm PD : sse12_fp_packed
28522852 f64, f128mem, memopfsf64, SSEPackedDouble, itins>,
28762876 !strconcat(OpcodeStr, "ps"), f256mem,
28772877 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
28782878 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2879 (loadv4i64 addr:$src2)))], 0>, TB, VEX_4V, VEX_L;
2879 (loadv4i64 addr:$src2)))], 0>, PS, VEX_4V, VEX_L;
28802880
28812881 defm V#NAME#PDY : sse12_fp_packed_logical_rm
28822882 !strconcat(OpcodeStr, "pd"), f256mem,
28932893 defm V#NAME#PS : sse12_fp_packed_logical_rm
28942894 !strconcat(OpcodeStr, "ps"), f128mem, [],
28952895 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2896 (loadv2i64 addr:$src2)))], 0>, TB, VEX_4V;
2896 (loadv2i64 addr:$src2)))], 0>, PS, VEX_4V;
28972897
28982898 defm V#NAME#PD : sse12_fp_packed_logical_rm
28992899 !strconcat(OpcodeStr, "pd"), f128mem,
29082908 !strconcat(OpcodeStr, "ps"), f128mem,
29092909 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
29102910 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2911 (memopv2i64 addr:$src2)))]>, TB;
2911 (memopv2i64 addr:$src2)))]>, PS;
29122912
29132913 defm PD : sse12_fp_packed_logical_rm
29142914 !strconcat(OpcodeStr, "pd"), f128mem,
29462946 SDNode OpNode, SizeItins itins> {
29472947 defm V#NAME#PS : sse12_fp_packed
29482948 VR128, v4f32, f128mem, loadv4f32,
2949 SSEPackedSingle, itins.s, 0>, TB, VEX_4V;
2949 SSEPackedSingle, itins.s, 0>, PS, VEX_4V;
29502950 defm V#NAME#PD : sse12_fp_packed
29512951 VR128, v2f64, f128mem, loadv2f64,
29522952 SSEPackedDouble, itins.d, 0>, PD, VEX_4V;
29532953
29542954 defm V#NAME#PSY : sse12_fp_packed
29552955 OpNode, VR256, v8f32, f256mem, loadv8f32,
2956 SSEPackedSingle, itins.s, 0>, TB, VEX_4V, VEX_L;
2956 SSEPackedSingle, itins.s, 0>, PS, VEX_4V, VEX_L;
29572957 defm V#NAME#PDY : sse12_fp_packed
29582958 OpNode, VR256, v4f64, f256mem, loadv4f64,
29592959 SSEPackedDouble, itins.d, 0>, PD, VEX_4V, VEX_L;
29612961 let Constraints = "$src1 = $dst" in {
29622962 defm PS : sse12_fp_packed
29632963 v4f32, f128mem, memopv4f32, SSEPackedSingle,
2964 itins.s>, TB;
2964 itins.s>, PS;
29652965 defm PD : sse12_fp_packed
29662966 v2f64, f128mem, memopv2f64, SSEPackedDouble,
29672967 itins.d>, PD;
36863686 "movnti{l}\t{$src, $dst|$dst, $src}",
36873687 [(nontemporalstore (i32 GR32:$src), addr:$dst)],
36883688 IIC_SSE_MOVNT>,
3689 TB, Requires<[HasSSE2]>;
3689 PS, Requires<[HasSSE2]>;
36903690 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
36913691 "movnti{q}\t{$src, $dst|$dst, $src}",
36923692 [(nontemporalstore (i64 GR64:$src), addr:$dst)],
36933693 IIC_SSE_MOVNT>,
3694 TB, Requires<[HasSSE2]>;
3694 PS, Requires<[HasSSE2]>;
36953695 } // SchedRW = [WriteStore]
36963696
36973697 } // AddedComplexity
80588058 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
80598059 // Zero All YMM registers
80608060 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
8061 [(int_x86_avx_vzeroall)]>, TB, VEX, VEX_L, Requires<[HasAVX]>;
8061 [(int_x86_avx_vzeroall)]>, PS, VEX, VEX_L, Requires<[HasAVX]>;
80628062
80638063 // Zero Upper bits of YMM registers
80648064 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
8065 [(int_x86_avx_vzeroupper)]>, TB, VEX, Requires<[HasAVX]>;
8065 [(int_x86_avx_vzeroupper)]>, PS, VEX, Requires<[HasAVX]>;
80668066 }
80678067
80688068 //===----------------------------------------------------------------------===//
3939 // 0F 01 C3
4040 def VMRESUME : I<0x01, MRM_C3, (outs), (ins), "vmresume", []>, TB;
4141 def VMPTRLDm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
42 "vmptrld\t$vmcs", []>, TB;
42 "vmptrld\t$vmcs", []>, PS;
4343 def VMPTRSTm : I<0xC7, MRM7m, (outs i64mem:$vmcs), (ins),
4444 "vmptrst\t$vmcs", []>, TB;
4545 def VMREAD64rm : I<0x78, MRMDestMem, (outs i64mem:$dst), (ins GR64:$src),
46 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB, Requires<[In64BitMode]>;
46 "vmread{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>;
4747 def VMREAD64rr : I<0x78, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
48 "vmread{q}\t{$src, $dst|$dst, $src}", []>, TB, Requires<[In64BitMode]>;
48 "vmread{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>;
4949 def VMREAD32rm : I<0x78, MRMDestMem, (outs i32mem:$dst), (ins GR32:$src),
50 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB, Requires<[Not64BitMode]>;
50 "vmread{l}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[Not64BitMode]>;
5151 def VMREAD32rr : I<0x78, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
52 "vmread{l}\t{$src, $dst|$dst, $src}", []>, TB, Requires<[Not64BitMode]>;
52 "vmread{l}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[Not64BitMode]>;
5353 def VMWRITE64rm : I<0x79, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
54 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB, Requires<[In64BitMode]>;
54 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>;
5555 def VMWRITE64rr : I<0x79, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
56 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, TB, Requires<[In64BitMode]>;
56 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>;
5757 def VMWRITE32rm : I<0x79, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
58 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB, Requires<[Not64BitMode]>;
58 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[Not64BitMode]>;
5959 def VMWRITE32rr : I<0x79, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
60 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, TB, Requires<[Not64BitMode]>;
60 "vmwrite{l}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[Not64BitMode]>;
6161 // 0F 01 C4
6262 def VMXOFF : I<0x01, MRM_C4, (outs), (ins), "vmxoff", []>, TB;
6363 def VMXON : I<0xC7, MRM6m, (outs), (ins i64mem:$vmxon),
8383 };
8484
8585 enum {
86 PD = 1, XS = 2, XD = 3
86 PS = 1, PD = 2, XS = 3, XD = 4
8787 };
8888
8989 enum {
258258 insnContext = EVEX_KB(IC_EVEX_L_W_XS);
259259 else if (OpPrefix == X86Local::XD)
260260 insnContext = EVEX_KB(IC_EVEX_L_W_XD);
261 else
261 else if (OpPrefix == X86Local::PS)
262262 insnContext = EVEX_KB(IC_EVEX_L_W);
263 else {
264 errs() << "Instruction does not use a prefix: " << Name << "\n";
265 llvm_unreachable("Invalid prefix");
266 }
263267 } else if (HasVEX_LPrefix) {
264268 // VEX_L
265269 if (OpPrefix == X86Local::PD)
268272 insnContext = EVEX_KB(IC_EVEX_L_XS);
269273 else if (OpPrefix == X86Local::XD)
270274 insnContext = EVEX_KB(IC_EVEX_L_XD);
271 else
275 else if (OpPrefix == X86Local::PS)
272276 insnContext = EVEX_KB(IC_EVEX_L);
277 else {
278 errs() << "Instruction does not use a prefix: " << Name << "\n";
279 llvm_unreachable("Invalid prefix");
280 }
273281 }
274282 else if (HasEVEX_L2Prefix && HasVEX_WPrefix) {
275283 // EVEX_L2 & VEX_W
279287 insnContext = EVEX_KB(IC_EVEX_L2_W_XS);
280288 else if (OpPrefix == X86Local::XD)
281289 insnContext = EVEX_KB(IC_EVEX_L2_W_XD);
282 else
290 else if (OpPrefix == X86Local::PS)
283291 insnContext = EVEX_KB(IC_EVEX_L2_W);
292 else {
293 errs() << "Instruction does not use a prefix: " << Name << "\n";
294 llvm_unreachable("Invalid prefix");
295 }
284296 } else if (HasEVEX_L2Prefix) {
285297 // EVEX_L2
286298 if (OpPrefix == X86Local::PD)
289301 insnContext = EVEX_KB(IC_EVEX_L2_XD);
290302 else if (OpPrefix == X86Local::XS)
291303 insnContext = EVEX_KB(IC_EVEX_L2_XS);
292 else
304 else if (OpPrefix == X86Local::PS)
293305 insnContext = EVEX_KB(IC_EVEX_L2);
306 else {
307 errs() << "Instruction does not use a prefix: " << Name << "\n";
308 llvm_unreachable("Invalid prefix");
309 }
294310 }
295311 else if (HasVEX_WPrefix) {
296312 // VEX_W
300316 insnContext = EVEX_KB(IC_EVEX_W_XS);
301317 else if (OpPrefix == X86Local::XD)
302318 insnContext = EVEX_KB(IC_EVEX_W_XD);
303 else
319 else if (OpPrefix == X86Local::PS)
304320 insnContext = EVEX_KB(IC_EVEX_W);
321 else {
322 errs() << "Instruction does not use a prefix: " << Name << "\n";
323 llvm_unreachable("Invalid prefix");
324 }
305325 }
306326 // No L, no W
307327 else if (OpPrefix == X86Local::PD)
321341 insnContext = IC_VEX_L_W_XS;
322342 else if (OpPrefix == X86Local::XD)
323343 insnContext = IC_VEX_L_W_XD;
324 else
344 else if (OpPrefix == X86Local::PS)
325345 insnContext = IC_VEX_L_W;
346 else {
347 errs() << "Instruction does not use a prefix: " << Name << "\n";
348 llvm_unreachable("Invalid prefix");
349 }
326350 } else if (OpPrefix == X86Local::PD && HasVEX_LPrefix)
327351 insnContext = IC_VEX_L_OPSIZE;
328352 else if (OpPrefix == X86Local::PD && HasVEX_WPrefix)
337361 insnContext = IC_VEX_W_XS;
338362 else if (HasVEX_WPrefix && OpPrefix == X86Local::XD)
339363 insnContext = IC_VEX_W_XD;
340 else if (HasVEX_WPrefix)
364 else if (HasVEX_WPrefix && OpPrefix == X86Local::PS)
341365 insnContext = IC_VEX_W;
342 else if (HasVEX_LPrefix)
366 else if (HasVEX_LPrefix && OpPrefix == X86Local::PS)
343367 insnContext = IC_VEX_L;
344368 else if (OpPrefix == X86Local::XD)
345369 insnContext = IC_VEX_XD;
346370 else if (OpPrefix == X86Local::XS)
347371 insnContext = IC_VEX_XS;
348 else
372 else if (OpPrefix == X86Local::PS)
349373 insnContext = IC_VEX;
374 else {
375 errs() << "Instruction does not use a prefix: " << Name << "\n";
376 llvm_unreachable("Invalid prefix");
377 }
350378 } else if (Is64Bit || HasREX_WPrefix) {
351379 if (HasREX_WPrefix && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD))
352380 insnContext = IC_64BIT_REXW_OPSIZE;