llvm.org GIT mirror llvm / 7d0dde0
TargetPassConfig: Keep a reference to an LLVMTargetMachine; NFC TargetPassConfig is not useful for targets that do not use the CodeGen library, so we may just as well store a pointer to an LLVMTargetMachine instead of just to a TargetMachine. While at it, also change the constructor to take a reference instead of a pointer as the TM must not be nullptr. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304247 91177308-0d34-0410-b5e6-96231b3b80d8 Matthias Braun 3 years ago
19 changed file(s) with 48 addition(s) and 48 deletion(s). Raw diff Collapse all Expand all
2121
2222 class PassConfigImpl;
2323 class ScheduleDAGInstrs;
24 class TargetMachine;
24 class LLVMTargetMachine;
2525 struct MachineSchedContext;
2626
2727 // The old pass manager infrastructure is hidden in a legacy namespace now.
102102 bool AddingMachinePasses;
103103
104104 protected:
105 TargetMachine *TM;
105 LLVMTargetMachine *TM;
106106 PassConfigImpl *Impl; // Internal data structures
107107 bool Initialized; // Flagged after all passes are configured.
108108
119119 bool RequireCodeGenSCCOrder;
120120
121121 public:
122 TargetPassConfig(TargetMachine *tm, PassManagerBase &pm);
122 TargetPassConfig(LLVMTargetMachine &TM, PassManagerBase &pm);
123123 // Dummy constructor.
124124 TargetPassConfig();
125125
260260
261261 // Out of line constructor provides default values for pass options and
262262 // registers all common codegen passes.
263 TargetPassConfig::TargetPassConfig(TargetMachine *tm, PassManagerBase &pm)
263 TargetPassConfig::TargetPassConfig(LLVMTargetMachine &TM, PassManagerBase &pm)
264264 : ImmutablePass(ID), PM(&pm), Started(true), Stopped(false),
265 AddingMachinePasses(false), TM(tm), Impl(nullptr), Initialized(false),
265 AddingMachinePasses(false), TM(&TM), Impl(nullptr), Initialized(false),
266266 DisableVerify(false), EnableTailMerge(true),
267267 RequireCodeGenSCCOrder(false) {
268268
281281 substitutePass(&PostRAMachineLICMID, &MachineLICMID);
282282
283283 if (StringRef(PrintMachineInstrs.getValue()).equals(""))
284 TM->Options.PrintMachineCode = true;
285
286 if (TM->Options.EnableIPRA)
284 TM.Options.PrintMachineCode = true;
285
286 if (TM.Options.EnableIPRA)
287287 setRequiresCodeGenSCCOrder();
288288 }
289289
309309 ///
310310 /// Targets may override this to extend TargetPassConfig.
311311 TargetPassConfig *LLVMTargetMachine::createPassConfig(PassManagerBase &PM) {
312 return new TargetPassConfig(this, PM);
312 return new TargetPassConfig(*this, PM);
313313 }
314314
315315 TargetPassConfig::TargetPassConfig()
255255 /// AArch64 Code Generator Pass Configuration Options.
256256 class AArch64PassConfig : public TargetPassConfig {
257257 public:
258 AArch64PassConfig(AArch64TargetMachine *TM, PassManagerBase &PM)
258 AArch64PassConfig(AArch64TargetMachine &TM, PassManagerBase &PM)
259259 : TargetPassConfig(TM, PM) {
260 if (TM->getOptLevel() != CodeGenOpt::None)
260 if (TM.getOptLevel() != CodeGenOpt::None)
261261 substitutePass(&PostRASchedulerID, &PostMachineSchedulerID);
262262 }
263263
316316 }
317317
318318 TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) {
319 return new AArch64PassConfig(this, PM);
319 return new AArch64PassConfig(*this, PM);
320320 }
321321
322322 void AArch64PassConfig::addIRPasses() {
455455
456456 class AMDGPUPassConfig : public TargetPassConfig {
457457 public:
458 AMDGPUPassConfig(TargetMachine *TM, PassManagerBase &PM)
458 AMDGPUPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
459459 : TargetPassConfig(TM, PM) {
460460 // Exceptions and StackMaps are not supported, so these passes will never do
461461 // anything.
486486
487487 class R600PassConfig final : public AMDGPUPassConfig {
488488 public:
489 R600PassConfig(TargetMachine *TM, PassManagerBase &PM)
489 R600PassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
490490 : AMDGPUPassConfig(TM, PM) {}
491491
492492 ScheduleDAGInstrs *createMachineScheduler(
502502
503503 class GCNPassConfig final : public AMDGPUPassConfig {
504504 public:
505 GCNPassConfig(TargetMachine *TM, PassManagerBase &PM)
505 GCNPassConfig(LLVMTargetMachine &TM, PassManagerBase &PM)
506506 : AMDGPUPassConfig(TM, PM) {}
507507
508508 GCNTargetMachine &getGCNTargetMachine() const {
681681 }
682682
683683 TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
684 return new R600PassConfig(this, PM);
684 return new R600PassConfig(*this, PM);
685685 }
686686
687687 //===----------------------------------------------------------------------===//
843843 }
844844
845845 TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
846 return new GCNPassConfig(this, PM);
847 }
848
846 return new GCNPassConfig(*this, PM);
847 }
848
381381 /// ARM Code Generator Pass Configuration Options.
382382 class ARMPassConfig : public TargetPassConfig {
383383 public:
384 ARMPassConfig(ARMBaseTargetMachine *TM, PassManagerBase &PM)
384 ARMPassConfig(ARMBaseTargetMachine &TM, PassManagerBase &PM)
385385 : TargetPassConfig(TM, PM) {}
386386
387387 ARMBaseTargetMachine &getARMTargetMachine() const {
418418 "ARM Execution Dependency Fix", false, false)
419419
420420 TargetPassConfig *ARMBaseTargetMachine::createPassConfig(PassManagerBase &PM) {
421 return new ARMPassConfig(this, PM);
421 return new ARMPassConfig(*this, PM);
422422 }
423423
424424 void ARMPassConfig::addIRPasses() {
5656 /// AVR Code Generator Pass Configuration Options.
5757 class AVRPassConfig : public TargetPassConfig {
5858 public:
59 AVRPassConfig(AVRTargetMachine *TM, PassManagerBase &PM)
59 AVRPassConfig(AVRTargetMachine &TM, PassManagerBase &PM)
6060 : TargetPassConfig(TM, PM) {}
6161
6262 AVRTargetMachine &getAVRTargetMachine() const {
7070 } // namespace
7171
7272 TargetPassConfig *AVRTargetMachine::createPassConfig(PassManagerBase &PM) {
73 return new AVRPassConfig(this, PM);
73 return new AVRPassConfig(*this, PM);
7474 }
7575
7676 extern "C" void LLVMInitializeAVRTarget() {
5757 // BPF Code Generator Pass Configuration Options.
5858 class BPFPassConfig : public TargetPassConfig {
5959 public:
60 BPFPassConfig(BPFTargetMachine *TM, PassManagerBase &PM)
60 BPFPassConfig(BPFTargetMachine &TM, PassManagerBase &PM)
6161 : TargetPassConfig(TM, PM) {}
6262
6363 BPFTargetMachine &getBPFTargetMachine() const {
6969 }
7070
7171 TargetPassConfig *BPFTargetMachine::createPassConfig(PassManagerBase &PM) {
72 return new BPFPassConfig(this, PM);
72 return new BPFPassConfig(*this, PM);
7373 }
7474
7575 // Install an instruction selector pass using
222222 /// Hexagon Code Generator Pass Configuration Options.
223223 class HexagonPassConfig : public TargetPassConfig {
224224 public:
225 HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM)
225 HexagonPassConfig(HexagonTargetMachine &TM, PassManagerBase &PM)
226226 : TargetPassConfig(TM, PM) {}
227227
228228 HexagonTargetMachine &getHexagonTargetMachine() const {
244244 } // namespace
245245
246246 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
247 return new HexagonPassConfig(this, PM);
247 return new HexagonPassConfig(*this, PM);
248248 }
249249
250250 void HexagonPassConfig::addIRPasses() {
7575 // Lanai Code Generator Pass Configuration Options.
7676 class LanaiPassConfig : public TargetPassConfig {
7777 public:
78 LanaiPassConfig(LanaiTargetMachine *TM, PassManagerBase *PassManager)
78 LanaiPassConfig(LanaiTargetMachine &TM, PassManagerBase *PassManager)
7979 : TargetPassConfig(TM, *PassManager) {}
8080
8181 LanaiTargetMachine &getLanaiTargetMachine() const {
9090
9191 TargetPassConfig *
9292 LanaiTargetMachine::createPassConfig(PassManagerBase &PassManager) {
93 return new LanaiPassConfig(this, &PassManager);
93 return new LanaiPassConfig(*this, &PassManager);
9494 }
9595
9696 // Install an instruction selector pass.
5151 /// MSP430 Code Generator Pass Configuration Options.
5252 class MSP430PassConfig : public TargetPassConfig {
5353 public:
54 MSP430PassConfig(MSP430TargetMachine *TM, PassManagerBase &PM)
54 MSP430PassConfig(MSP430TargetMachine &TM, PassManagerBase &PM)
5555 : TargetPassConfig(TM, PM) {}
5656
5757 MSP430TargetMachine &getMSP430TargetMachine() const {
6464 } // namespace
6565
6666 TargetPassConfig *MSP430TargetMachine::createPassConfig(PassManagerBase &PM) {
67 return new MSP430PassConfig(this, PM);
67 return new MSP430PassConfig(*this, PM);
6868 }
6969
7070 bool MSP430PassConfig::addInstSelector() {
200200 /// Mips Code Generator Pass Configuration Options.
201201 class MipsPassConfig : public TargetPassConfig {
202202 public:
203 MipsPassConfig(MipsTargetMachine *TM, PassManagerBase &PM)
203 MipsPassConfig(MipsTargetMachine &TM, PassManagerBase &PM)
204204 : TargetPassConfig(TM, PM) {
205205 // The current implementation of long branch pass requires a scratch
206206 // register ($at) to be available before branch instructions. Tail merging
226226 } // end anonymous namespace
227227
228228 TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM) {
229 return new MipsPassConfig(this, PM);
229 return new MipsPassConfig(*this, PM);
230230 }
231231
232232 void MipsPassConfig::addIRPasses() {
131131
132132 class NVPTXPassConfig : public TargetPassConfig {
133133 public:
134 NVPTXPassConfig(NVPTXTargetMachine *TM, PassManagerBase &PM)
134 NVPTXPassConfig(NVPTXTargetMachine &TM, PassManagerBase &PM)
135135 : TargetPassConfig(TM, PM) {}
136136
137137 NVPTXTargetMachine &getNVPTXTargetMachine() const {
162162 } // end anonymous namespace
163163
164164 TargetPassConfig *NVPTXTargetMachine::createPassConfig(PassManagerBase &PM) {
165 return new NVPTXPassConfig(this, PM);
165 return new NVPTXPassConfig(*this, PM);
166166 }
167167
168168 void NVPTXTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
295295 /// PPC Code Generator Pass Configuration Options.
296296 class PPCPassConfig : public TargetPassConfig {
297297 public:
298 PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
298 PPCPassConfig(PPCTargetMachine &TM, PassManagerBase &PM)
299299 : TargetPassConfig(TM, PM) {}
300300
301301 PPCTargetMachine &getPPCTargetMachine() const {
315315 } // end anonymous namespace
316316
317317 TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
318 return new PPCPassConfig(this, PM);
318 return new PPCPassConfig(*this, PM);
319319 }
320320
321321 void PPCPassConfig::addIRPasses() {
5555 }
5656
5757 TargetPassConfig *RISCVTargetMachine::createPassConfig(PassManagerBase &PM) {
58 return new TargetPassConfig(this, PM);
58 return new TargetPassConfig(*this, PM);
5959 }
113113 /// Sparc Code Generator Pass Configuration Options.
114114 class SparcPassConfig : public TargetPassConfig {
115115 public:
116 SparcPassConfig(SparcTargetMachine *TM, PassManagerBase &PM)
116 SparcPassConfig(SparcTargetMachine &TM, PassManagerBase &PM)
117117 : TargetPassConfig(TM, PM) {}
118118
119119 SparcTargetMachine &getSparcTargetMachine() const {
127127 } // namespace
128128
129129 TargetPassConfig *SparcTargetMachine::createPassConfig(PassManagerBase &PM) {
130 return new SparcPassConfig(this, PM);
130 return new SparcPassConfig(*this, PM);
131131 }
132132
133133 void SparcPassConfig::addIRPasses() {
118118 /// SystemZ Code Generator Pass Configuration Options.
119119 class SystemZPassConfig : public TargetPassConfig {
120120 public:
121 SystemZPassConfig(SystemZTargetMachine *TM, PassManagerBase &PM)
121 SystemZPassConfig(SystemZTargetMachine &TM, PassManagerBase &PM)
122122 : TargetPassConfig(TM, PM) {}
123123
124124 SystemZTargetMachine &getSystemZTargetMachine() const {
211211 }
212212
213213 TargetPassConfig *SystemZTargetMachine::createPassConfig(PassManagerBase &PM) {
214 return new SystemZPassConfig(this, PM);
214 return new SystemZPassConfig(*this, PM);
215215 }
216216
217217 TargetIRAnalysis SystemZTargetMachine::getTargetIRAnalysis() {
128128 /// WebAssembly Code Generator Pass Configuration Options.
129129 class WebAssemblyPassConfig final : public TargetPassConfig {
130130 public:
131 WebAssemblyPassConfig(WebAssemblyTargetMachine *TM, PassManagerBase &PM)
131 WebAssemblyPassConfig(WebAssemblyTargetMachine &TM, PassManagerBase &PM)
132132 : TargetPassConfig(TM, PM) {}
133133
134134 WebAssemblyTargetMachine &getWebAssemblyTargetMachine() const {
153153
154154 TargetPassConfig *
155155 WebAssemblyTargetMachine::createPassConfig(PassManagerBase &PM) {
156 return new WebAssemblyPassConfig(this, PM);
156 return new WebAssemblyPassConfig(*this, PM);
157157 }
158158
159159 FunctionPass *WebAssemblyPassConfig::createTargetRegisterAllocator(bool) {
322322 /// X86 Code Generator Pass Configuration Options.
323323 class X86PassConfig : public TargetPassConfig {
324324 public:
325 X86PassConfig(X86TargetMachine *TM, PassManagerBase &PM)
325 X86PassConfig(X86TargetMachine &TM, PassManagerBase &PM)
326326 : TargetPassConfig(TM, PM) {}
327327
328328 X86TargetMachine &getX86TargetMachine() const {
368368 "X86 Execution Dependency Fix", false, false)
369369
370370 TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
371 return new X86PassConfig(this, PM);
371 return new X86PassConfig(*this, PM);
372372 }
373373
374374 void X86PassConfig::addIRPasses() {
5353 /// XCore Code Generator Pass Configuration Options.
5454 class XCorePassConfig : public TargetPassConfig {
5555 public:
56 XCorePassConfig(XCoreTargetMachine *TM, PassManagerBase &PM)
56 XCorePassConfig(XCoreTargetMachine &TM, PassManagerBase &PM)
5757 : TargetPassConfig(TM, PM) {}
5858
5959 XCoreTargetMachine &getXCoreTargetMachine() const {
6969 } // end anonymous namespace
7070
7171 TargetPassConfig *XCoreTargetMachine::createPassConfig(PassManagerBase &PM) {
72 return new XCorePassConfig(this, PM);
72 return new XCorePassConfig(*this, PM);
7373 }
7474
7575 void XCorePassConfig::addIRPasses() {