llvm.org GIT mirror llvm / 7cf6af5
[CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@312053 91177308-0d34-0410-b5e6-96231b3b80d8 Eugene Zelenko 3 years ago
8 changed file(s) with 339 addition(s) and 187 deletion(s). Raw diff Collapse all Expand all
1212 //
1313 //===----------------------------------------------------------------------===//
1414
15 #include "llvm/ADT/APInt.h"
16 #include "llvm/ADT/ArrayRef.h"
1517 #include "llvm/ADT/DenseMap.h"
18 #include "llvm/ADT/PointerIntPair.h"
19 #include "llvm/ADT/STLExtras.h"
1620 #include "llvm/ADT/SetVector.h"
17 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/ADT/SmallPtrSet.h"
22 #include "llvm/ADT/SmallVector.h"
1823 #include "llvm/ADT/Statistic.h"
1924 #include "llvm/Analysis/BlockFrequencyInfo.h"
2025 #include "llvm/Analysis/BranchProbabilityInfo.h"
21 #include "llvm/Analysis/CFG.h"
26 #include "llvm/Analysis/ConstantFolding.h"
2227 #include "llvm/Analysis/InstructionSimplify.h"
2328 #include "llvm/Analysis/LoopInfo.h"
2429 #include "llvm/Analysis/MemoryBuiltins.h"
2732 #include "llvm/Analysis/TargetTransformInfo.h"
2833 #include "llvm/Analysis/ValueTracking.h"
2934 #include "llvm/CodeGen/Analysis.h"
30 #include "llvm/CodeGen/Passes.h"
35 #include "llvm/CodeGen/ISDOpcodes.h"
36 #include "llvm/CodeGen/MachineValueType.h"
37 #include "llvm/CodeGen/SelectionDAGNodes.h"
3138 #include "llvm/CodeGen/TargetPassConfig.h"
39 #include "llvm/CodeGen/ValueTypes.h"
40 #include "llvm/IR/Argument.h"
41 #include "llvm/IR/Attributes.h"
42 #include "llvm/IR/BasicBlock.h"
3243 #include "llvm/IR/CallSite.h"
44 #include "llvm/IR/Constant.h"
3345 #include "llvm/IR/Constants.h"
3446 #include "llvm/IR/DataLayout.h"
3547 #include "llvm/IR/DerivedTypes.h"
3648 #include "llvm/IR/Dominators.h"
3749 #include "llvm/IR/Function.h"
3850 #include "llvm/IR/GetElementPtrTypeIterator.h"
51 #include "llvm/IR/GlobalValue.h"
52 #include "llvm/IR/GlobalVariable.h"
3953 #include "llvm/IR/IRBuilder.h"
4054 #include "llvm/IR/InlineAsm.h"
55 #include "llvm/IR/InstrTypes.h"
56 #include "llvm/IR/Instruction.h"
4157 #include "llvm/IR/Instructions.h"
4258 #include "llvm/IR/IntrinsicInst.h"
59 #include "llvm/IR/Intrinsics.h"
60 #include "llvm/IR/LLVMContext.h"
4361 #include "llvm/IR/MDBuilder.h"
62 #include "llvm/IR/Module.h"
63 #include "llvm/IR/Operator.h"
4464 #include "llvm/IR/PatternMatch.h"
4565 #include "llvm/IR/Statepoint.h"
66 #include "llvm/IR/Type.h"
67 #include "llvm/IR/Use.h"
68 #include "llvm/IR/User.h"
69 #include "llvm/IR/Value.h"
4670 #include "llvm/IR/ValueHandle.h"
4771 #include "llvm/IR/ValueMap.h"
4872 #include "llvm/Pass.h"
73 #include "llvm/Support/BlockFrequency.h"
4974 #include "llvm/Support/BranchProbability.h"
75 #include "llvm/Support/Casting.h"
5076 #include "llvm/Support/CommandLine.h"
77 #include "llvm/Support/Compiler.h"
5178 #include "llvm/Support/Debug.h"
79 #include "llvm/Support/ErrorHandling.h"
80 #include "llvm/Support/MathExtras.h"
5281 #include "llvm/Support/raw_ostream.h"
5382 #include "llvm/Target/TargetLowering.h"
83 #include "llvm/Target/TargetMachine.h"
84 #include "llvm/Target/TargetOptions.h"
5485 #include "llvm/Target/TargetSubtargetInfo.h"
5586 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
56 #include "llvm/Transforms/Utils/BuildLibCalls.h"
5787 #include "llvm/Transforms/Utils/BypassSlowDivision.h"
5888 #include "llvm/Transforms/Utils/Cloning.h"
5989 #include "llvm/Transforms/Utils/Local.h"
6090 #include "llvm/Transforms/Utils/SimplifyLibCalls.h"
6191 #include "llvm/Transforms/Utils/ValueMapper.h"
92 #include
93 #include
94 #include
95 #include
96 #include
97 #include
98 #include
99 #include
62100
63101 using namespace llvm;
64102 using namespace llvm::PatternMatch;
156194 "memcmp that is only being compared against zero."));
157195
158196 namespace {
159 typedef SmallPtrSet SetOfInstrs;
160 typedef PointerIntPair TypeIsSExt;
161 typedef DenseMap InstrToOrigTy;
162 typedef SmallVector SExts;
163 typedef DenseMap ValueToSExts;
197
198 using SetOfInstrs = SmallPtrSet;
199 using TypeIsSExt = PointerIntPair;
200 using InstrToOrigTy = DenseMap;
201 using SExts = SmallVector;
202 using ValueToSExts = DenseMap;
203
164204 class TypePromotionTransaction;
165205
166206 class CodeGenPrepare : public FunctionPass {
167 const TargetMachine *TM;
207 const TargetMachine *TM = nullptr;
168208 const TargetSubtargetInfo *SubtargetInfo;
169 const TargetLowering *TLI;
209 const TargetLowering *TLI = nullptr;
170210 const TargetRegisterInfo *TRI;
171 const TargetTransformInfo *TTI;
211 const TargetTransformInfo *TTI = nullptr;
172212 const TargetLibraryInfo *TLInfo;
173213 const LoopInfo *LI;
174214 std::unique_ptr BFI;
185225
186226 /// Keeps track of all instructions inserted for the current function.
187227 SetOfInstrs InsertedInsts;
228
188229 /// Keeps track of the type of the related instruction before their
189230 /// promotion for the current function.
190231 InstrToOrigTy PromotedInsts;
205246 bool OptSize;
206247
207248 /// DataLayout for the Function being processed.
208 const DataLayout *DL;
249 const DataLayout *DL = nullptr;
209250
210251 public:
211252 static char ID; // Pass identification, replacement for typeid
212 CodeGenPrepare()
213 : FunctionPass(ID), TM(nullptr), TLI(nullptr), TTI(nullptr),
214 DL(nullptr) {
253
254 CodeGenPrepare() : FunctionPass(ID) {
215255 initializeCodeGenPreparePass(*PassRegistry::getPassRegistry());
216256 }
257
217258 bool runOnFunction(Function &F) override;
218259
219260 StringRef getPassName() const override { return "CodeGen Prepare"; }
265306 bool simplifyOffsetableRelocate(Instruction &I);
266307 bool splitIndirectCriticalEdges(Function &F);
267308 };
268 }
309
310 } // end anonymous namespace
269311
270312 char CodeGenPrepare::ID = 0;
313
271314 INITIALIZE_PASS_BEGIN(CodeGenPrepare, DEBUG_TYPE,
272315 "Optimize for code generation", false, false)
273316 INITIALIZE_PASS_DEPENDENCY(ProfileSummaryInfoWrapperPass)
826869 return true;
827870 }
828871
829
830872 /// Eliminate a basic block that has only phi's and an unconditional branch in
831873 /// it.
832874 void CodeGenPrepare::eliminateMostlyEmptyBlock(BasicBlock *BB) {
11511193 /// reduce the number of virtual registers that must be created and coalesced.
11521194 ///
11531195 /// Return true if any changes are made.
1154 ///
11551196 static bool OptimizeNoopCopyExpression(CastInst *CI, const TargetLowering &TLI,
11561197 const DataLayout &DL) {
11571198 // Sink only "cheap" (or nop) address-space casts. This is a weaker condition
16561697 }
16571698
16581699 namespace {
1700
16591701 // This class provides helper functions to expand a memcmp library call into an
16601702 // inline expansion.
16611703 class MemCmpExpansion {
16621704 struct ResultBlock {
1663 BasicBlock *BB;
1664 PHINode *PhiSrc1;
1665 PHINode *PhiSrc2;
1666 ResultBlock();
1705 BasicBlock *BB = nullptr;
1706 PHINode *PhiSrc1 = nullptr;
1707 PHINode *PhiSrc2 = nullptr;
1708
1709 ResultBlock() = default;
16671710 };
16681711
16691712 CallInst *CI;
17011744 public:
17021745 MemCmpExpansion(CallInst *CI, uint64_t Size, unsigned MaxLoadSize,
17031746 unsigned NumLoadsPerBlock, const DataLayout &DL);
1747
17041748 Value *getMemCmpExpansion(uint64_t Size);
17051749 };
1706 } // namespace
1707
1708 MemCmpExpansion::ResultBlock::ResultBlock()
1709 : BB(nullptr), PhiSrc1(nullptr), PhiSrc2(nullptr) {}
1750
1751 } // end anonymous namespace
17101752
17111753 // Initialize the basic block structure required for expansion of memcmp call
17121754 // with given maximum load size and memcmp size parameter.
17211763 const DataLayout &TheDataLayout)
17221764 : CI(CI), MaxLoadSize(MaxLoadSize), NumLoadsPerBlock(LoadsPerBlock),
17231765 DL(TheDataLayout), Builder(CI) {
1724
17251766 // A memcmp with zero-comparison with only one block of load and compare does
17261767 // not need to set up any extra blocks. This case could be handled in the DAG,
17271768 // but since we have all of the machinery to flexibly expand any memcpy here,
26322673 /// This is an extended version of TargetLowering::AddrMode
26332674 /// which holds actual Value*'s for register values.
26342675 struct ExtAddrMode : public TargetLowering::AddrMode {
2635 Value *BaseReg;
2636 Value *ScaledReg;
2637 ExtAddrMode() : BaseReg(nullptr), ScaledReg(nullptr) {}
2676 Value *BaseReg = nullptr;
2677 Value *ScaledReg = nullptr;
2678
2679 ExtAddrMode() = default;
2680
26382681 void print(raw_ostream &OS) const;
26392682 void dump() const;
26402683
26442687 (HasBaseReg == O.HasBaseReg) && (Scale == O.Scale);
26452688 }
26462689 };
2690
2691 } // end anonymous namespace
26472692
26482693 #ifndef NDEBUG
26492694 static inline raw_ostream &operator<<(raw_ostream &OS, const ExtAddrMode &AM) {
26902735 }
26912736 #endif
26922737
2738 namespace {
2739
26932740 /// \brief This class provides transaction based operation on the IR.
26942741 /// Every change made through this class is recorded in the internal state and
26952742 /// can be undone (rollback) until commit is called.
26962743 class TypePromotionTransaction {
2697
26982744 /// \brief This represents the common interface of the individual transaction.
26992745 /// Each class implements the logic for doing one specific modification on
27002746 /// the IR via the TypePromotionTransaction.
27082754 /// The constructor performs the related action on the IR.
27092755 TypePromotionAction(Instruction *Inst) : Inst(Inst) {}
27102756
2711 virtual ~TypePromotionAction() {}
2757 virtual ~TypePromotionAction() = default;
27122758
27132759 /// \brief Undo the modification done by this action.
27142760 /// When this method is called, the IR must be in the same state as it was
27352781 Instruction *PrevInst;
27362782 BasicBlock *BB;
27372783 } Point;
2784
27382785 /// Remember whether or not the instruction had a previous instruction.
27392786 bool HasPrevInstruction;
27402787
27892836 class OperandSetter : public TypePromotionAction {
27902837 /// Original operand of the instruction.
27912838 Value *Origin;
2839
27922840 /// Index of the modified instruction.
27932841 unsigned Idx;
27942842
28462894 /// \brief Build a truncate instruction.
28472895 class TruncBuilder : public TypePromotionAction {
28482896 Value *Val;
2897
28492898 public:
28502899 /// \brief Build a truncate instruction of \p Opnd producing a \p Ty
28512900 /// result.
28702919 /// \brief Build a sign extension instruction.
28712920 class SExtBuilder : public TypePromotionAction {
28722921 Value *Val;
2922
28732923 public:
28742924 /// \brief Build a sign extension instruction of \p Opnd producing a \p Ty
28752925 /// result.
28952945 /// \brief Build a zero extension instruction.
28962946 class ZExtBuilder : public TypePromotionAction {
28972947 Value *Val;
2948
28982949 public:
28992950 /// \brief Build a zero extension instruction of \p Opnd producing a \p Ty
29002951 /// result.
29452996 struct InstructionAndIdx {
29462997 /// The instruction using the instruction.
29472998 Instruction *Inst;
2999
29483000 /// The index where this instruction is used for Inst.
29493001 unsigned Idx;
3002
29503003 InstructionAndIdx(Instruction *Inst, unsigned Idx)
29513004 : Inst(Inst), Idx(Idx) {}
29523005 };
29533006
29543007 /// Keep track of the original uses (pair Instruction, Index).
29553008 SmallVector OriginalUses;
2956 typedef SmallVectorImpl::iterator use_iterator;
3009
3010 using use_iterator = SmallVectorImpl::iterator;
29573011
29583012 public:
29593013 /// \brief Replace all the use of \p Inst by \p New.
29843038 class InstructionRemover : public TypePromotionAction {
29853039 /// Original position of the instruction.
29863040 InsertionHandler Inserter;
3041
29873042 /// Helper structure to hide all the link to the instruction. In other
29883043 /// words, this helps to do as if the instruction was removed.
29893044 OperandsHider Hider;
3045
29903046 /// Keep track of the uses replaced, if any.
2991 UsesReplacer *Replacer;
3047 UsesReplacer *Replacer = nullptr;
3048
29923049 /// Keep track of instructions removed.
29933050 SetOfInstrs &RemovedInsts;
29943051
30003057 InstructionRemover(Instruction *Inst, SetOfInstrs &RemovedInsts,
30013058 Value *New = nullptr)
30023059 : TypePromotionAction(Inst), Inserter(Inst), Hider(Inst),
3003 Replacer(nullptr), RemovedInsts(RemovedInsts) {
3060 RemovedInsts(RemovedInsts) {
30043061 if (New)
30053062 Replacer = new UsesReplacer(Inst, New);
30063063 DEBUG(dbgs() << "Do: InstructionRemover: " << *Inst << "\n");
30293086 /// Restoration point.
30303087 /// The restoration point is a pointer to an action instead of an iterator
30313088 /// because the iterator may be invalidated but not the pointer.
3032 typedef const TypePromotionAction *ConstRestorationPt;
3089 using ConstRestorationPt = const TypePromotionAction *;
30333090
30343091 TypePromotionTransaction(SetOfInstrs &RemovedInsts)
30353092 : RemovedInsts(RemovedInsts) {}
30363093
30373094 /// Advocate every changes made in that transaction.
30383095 void commit();
3096
30393097 /// Undo all the changes made after the given point.
30403098 void rollback(ConstRestorationPt Point);
3099
30413100 /// Get the current restoration point.
30423101 ConstRestorationPt getRestorationPoint() const;
30433102
30453104 /// @{
30463105 /// Same as Instruction::setOperand.
30473106 void setOperand(Instruction *Inst, unsigned Idx, Value *NewVal);
3107
30483108 /// Same as Instruction::eraseFromParent.
30493109 void eraseInstruction(Instruction *Inst, Value *NewVal = nullptr);
3110
30503111 /// Same as Value::replaceAllUsesWith.
30513112 void replaceAllUsesWith(Instruction *Inst, Value *New);
3113
30523114 /// Same as Value::mutateType.
30533115 void mutateType(Instruction *Inst, Type *NewTy);
3116
30543117 /// Same as IRBuilder::createTrunc.
30553118 Value *createTrunc(Instruction *Opnd, Type *Ty);
3119
30563120 /// Same as IRBuilder::createSExt.
30573121 Value *createSExt(Instruction *Inst, Value *Opnd, Type *Ty);
3122
30583123 /// Same as IRBuilder::createZExt.
30593124 Value *createZExt(Instruction *Inst, Value *Opnd, Type *Ty);
3125
30603126 /// Same as Instruction::moveBefore.
30613127 void moveBefore(Instruction *Inst, Instruction *Before);
30623128 /// @}
30643130 private:
30653131 /// The ordered list of actions made so far.
30663132 SmallVector, 16> Actions;
3067 typedef SmallVectorImpl>::iterator CommitPt;
3133
3134 using CommitPt = SmallVectorImpl>::iterator;
3135
30683136 SetOfInstrs &RemovedInsts;
30693137 };
30703138
3139 } // end anonymous namespace
3140
30713141 void TypePromotionTransaction::setOperand(Instruction *Inst, unsigned Idx,
30723142 Value *NewVal) {
3073 Actions.push_back(
3074 make_unique(Inst, Idx, NewVal));
3143 Actions.push_back(llvm::make_unique(
3144 Inst, Idx, NewVal));
30753145 }
30763146
30773147 void TypePromotionTransaction::eraseInstruction(Instruction *Inst,
30783148 Value *NewVal) {
30793149 Actions.push_back(
3080 make_unique(Inst,
3081 RemovedInsts, NewVal));
3150 llvm::make_unique(
3151 Inst, RemovedInsts, NewVal));
30823152 }
30833153
30843154 void TypePromotionTransaction::replaceAllUsesWith(Instruction *Inst,
30853155 Value *New) {
3086 Actions.push_back(make_unique(Inst, New));
3156 Actions.push_back(
3157 llvm::make_unique(Inst, New));
30873158 }
30883159
30893160 void TypePromotionTransaction::mutateType(Instruction *Inst, Type *NewTy) {
3090 Actions.push_back(make_unique(Inst, NewTy));
3161 Actions.push_back(
3162 llvm::make_unique(Inst, NewTy));
30913163 }
30923164
30933165 Value *TypePromotionTransaction::createTrunc(Instruction *Opnd,
31173189 void TypePromotionTransaction::moveBefore(Instruction *Inst,
31183190 Instruction *Before) {
31193191 Actions.push_back(
3120 make_unique(Inst, Before));
3192 llvm::make_unique(
3193 Inst, Before));
31213194 }
31223195
31233196 TypePromotionTransaction::ConstRestorationPt
31393212 Curr->undo();
31403213 }
31413214 }
3215
3216 namespace {
31423217
31433218 /// \brief A helper class for matching addressing modes.
31443219 ///
31613236
31623237 /// The instructions inserted by other CodeGenPrepare optimizations.
31633238 const SetOfInstrs &InsertedInsts;
3239
31643240 /// A map from the instructions to their type before promotion.
31653241 InstrToOrigTy &PromotedInsts;
3242
31663243 /// The ongoing transaction where every action should be registered.
31673244 TypePromotionTransaction &TPT;
31683245
31843261 PromotedInsts(PromotedInsts), TPT(TPT) {
31853262 IgnoreProfitability = false;
31863263 }
3264
31873265 public:
3188
31893266 /// Find the maximal addressing mode that a load/store of V can fold,
31903267 /// give an access type of AccessTy. This returns a list of involved
31913268 /// instructions in AddrModeInsts.
32103287 (void)Success; assert(Success && "Couldn't select *anything*?");
32113288 return Result;
32123289 }
3290
32133291 private:
32143292 bool matchScaledValue(Value *ScaleReg, int64_t Scale, unsigned Depth);
32153293 bool matchAddr(Value *V, unsigned Depth);
32223300 bool isPromotionProfitable(unsigned NewCost, unsigned OldCost,
32233301 Value *PromotedOperand) const;
32243302 };
3303
3304 } // end anonymous namespace
32253305
32263306 /// Try adding ScaleReg*Scale to the current addressing mode.
32273307 /// Return true and update AddrMode if this addr mode is legal for the target,
33273407 ISDOpcode, TLI.getValueType(DL, PromotedInst->getType()));
33283408 }
33293409
3410 namespace {
3411
33303412 /// \brief Hepler class to perform type promotion.
33313413 class TypePromotionHelper {
33323414 /// \brief Utility function to check whether or not a sign or zero extension
34033485
34043486 public:
34053487 /// Type for the utility function that promotes the operand of Ext.
3406 typedef Value *(*Action)(Instruction *Ext, TypePromotionTransaction &TPT,
3407 InstrToOrigTy &PromotedInsts,
3408 unsigned &CreatedInstsCost,
3409 SmallVectorImpl *Exts,
3410 SmallVectorImpl *Truncs,
3411 const TargetLowering &TLI);
3488 using Action = Value *(*)(Instruction *Ext, TypePromotionTransaction &TPT,
3489 InstrToOrigTy &PromotedInsts,
3490 unsigned &CreatedInstsCost,
3491 SmallVectorImpl *Exts,
3492 SmallVectorImpl *Truncs,
3493 const TargetLowering &TLI);
3494
34123495 /// \brief Given a sign/zero extend instruction \p Ext, return the approriate
34133496 /// action to promote the operand of \p Ext instead of using Ext.
34143497 /// \return NULL if no promotable action is possible with the current
34233506 const InstrToOrigTy &PromotedInsts);
34243507 };
34253508
3509 } // end anonymous namespace
3510
34263511 bool TypePromotionHelper::canGetThrough(const Instruction *Inst,
34273512 Type *ConsideredExtType,
34283513 const InstrToOrigTy &PromotedInsts,
35213606 }
35223607
35233608 Value *TypePromotionHelper::promoteOperandForTruncAndAnyExt(
3524 llvm::Instruction *SExt, TypePromotionTransaction &TPT,
3609 Instruction *SExt, TypePromotionTransaction &TPT,
35253610 InstrToOrigTy &PromotedInsts, unsigned &CreatedInstsCost,
35263611 SmallVectorImpl *Exts,
35273612 SmallVectorImpl *Truncs, const TargetLowering &TLI) {
42654350
42664351 return true;
42674352 }
4268
4269 } // end anonymous namespace
42704353
42714354 /// Return true if the specified values are defined in a
42724355 /// different basic block than BB.
51585241 // b2:
51595242 // x = phi x1', x2'
51605243 // y = and x, 0xff
5161 //
5162
51635244 bool CodeGenPrepare::optimizeLoadExt(LoadInst *Load) {
5164
51655245 if (!Load->isSimple() ||
51665246 !(Load->getType()->isIntegerTy() || Load->getType()->isPointerTy()))
51675247 return false;
52005280 }
52015281
52025282 switch (I->getOpcode()) {
5203 case llvm::Instruction::And: {
5283 case Instruction::And: {
52045284 auto *AndC = dyn_cast(I->getOperand(1));
52055285 if (!AndC)
52065286 return false;
52145294 break;
52155295 }
52165296
5217 case llvm::Instruction::Shl: {
5297 case Instruction::Shl: {
52185298 auto *ShlC = dyn_cast(I->getOperand(1));
52195299 if (!ShlC)
52205300 return false;
52235303 break;
52245304 }
52255305
5226 case llvm::Instruction::Trunc: {
5306 case Instruction::Trunc: {
52275307 EVT TruncVT = TLI->getValueType(*DL, I->getType());
52285308 unsigned TruncBitWidth = TruncVT.getSizeInBits();
52295309 DemandBits.setLowBits(TruncBitWidth);
56275707
56285708
56295709 namespace {
5710
56305711 /// \brief Helper class to promote a scalar operation to a vector one.
56315712 /// This class is used to move downward extractelement transition.
56325713 /// E.g.,
56545735
56555736 /// The transition being moved downwards.
56565737 Instruction *Transition;
5738
56575739 /// The sequence of instructions to be promoted.
56585740 SmallVector InstsToBePromoted;
5741
56595742 /// Cost of combining a store and an extract.
56605743 unsigned StoreExtractCombineCost;
5744
56615745 /// Instruction that will be combined with the transition.
5662 Instruction *CombineInst;
5746 Instruction *CombineInst = nullptr;
56635747
56645748 /// \brief The instruction that represents the current end of the transition.
56655749 /// Since we are faking the promotion until we reach the end of the chain
57655849 /// where \p Val is only
57665850 /// used at the index of the extract.
57675851 Value *getConstantVector(Constant *Val, bool UseSplat) const {
5768 unsigned ExtractIdx = UINT_MAX;
5852 unsigned ExtractIdx = std::numeric_limits::max();
57695853 if (!UseSplat) {
57705854 // If we cannot determine where the constant must be, we have to
57715855 // use a splat constant.
58195903 const TargetTransformInfo &TTI, Instruction *Transition,
58205904 unsigned CombineCost)
58215905 : DL(DL), TLI(TLI), TTI(TTI), Transition(Transition),
5822 StoreExtractCombineCost(CombineCost), CombineInst(nullptr) {
5906 StoreExtractCombineCost(CombineCost) {
58235907 assert(Transition && "Do not know how to promote null");
58245908 }
58255909
58945978 return true;
58955979 }
58965980 };
5897 } // End of anonymous namespace.
5981
5982 } // end anonymous namespace
58985983
58995984 void VectorPromoteHelper::promoteImpl(Instruction *ToBePromoted) {
59005985 // At this point, we know that all the operands of ToBePromoted but Def
59416026 /// Try to push the extractelement towards the stores when the target
59426027 /// has this feature and this is profitable.
59436028 bool CodeGenPrepare::optimizeExtractElementInst(Instruction *Inst) {
5944 unsigned CombineCost = UINT_MAX;
6029 unsigned CombineCost = std::numeric_limits::max();
59456030 if (DisableStoreExtract || !TLI ||
59466031 (!StressStoreExtract &&
59476032 !TLI->canCombineStoreAndExtract(Inst->getOperand(0)->getType(),
63286413 /// \brief Scale down both weights to fit into uint32_t.
63296414 static void scaleWeights(uint64_t &NewTrue, uint64_t &NewFalse) {
63306415 uint64_t NewMax = (NewTrue > NewFalse) ? NewTrue : NewFalse;
6331 uint32_t Scale = (NewMax / UINT32_MAX) + 1;
6416 uint32_t Scale = (NewMax / std::numeric_limits::max()) + 1;
63326417 NewTrue = NewTrue / Scale;
63336418 NewFalse = NewFalse / Scale;
63346419 }
None //===-- ImplicitNullChecks.cpp - Fold null checks into memory accesses ----===//
0 //===- ImplicitNullChecks.cpp - Fold null checks into memory accesses -----===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
2525 //
2626 //===----------------------------------------------------------------------===//
2727
28 #include "llvm/ADT/DenseSet.h"
28 #include "llvm/ADT/ArrayRef.h"
29 #include "llvm/ADT/None.h"
30 #include "llvm/ADT/Optional.h"
31 #include "llvm/ADT/STLExtras.h"
2932 #include "llvm/ADT/SmallVector.h"
3033 #include "llvm/ADT/Statistic.h"
3134 #include "llvm/Analysis/AliasAnalysis.h"
35 #include "llvm/Analysis/MemoryLocation.h"
3236 #include "llvm/CodeGen/FaultMaps.h"
37 #include "llvm/CodeGen/MachineBasicBlock.h"
3338 #include "llvm/CodeGen/MachineFunction.h"
3439 #include "llvm/CodeGen/MachineFunctionPass.h"
40 #include "llvm/CodeGen/MachineInstr.h"
3541 #include "llvm/CodeGen/MachineInstrBuilder.h"
3642 #include "llvm/CodeGen/MachineMemOperand.h"
37 #include "llvm/CodeGen/MachineModuleInfo.h"
3843 #include "llvm/CodeGen/MachineOperand.h"
3944 #include "llvm/CodeGen/MachineRegisterInfo.h"
40 #include "llvm/CodeGen/Passes.h"
45 #include "llvm/CodeGen/PseudoSourceValue.h"
4146 #include "llvm/IR/BasicBlock.h"
42 #include "llvm/IR/Instruction.h"
47 #include "llvm/IR/DebugLoc.h"
4348 #include "llvm/IR/LLVMContext.h"
49 #include "llvm/MC/MCInstrDesc.h"
50 #include "llvm/MC/MCRegisterInfo.h"
51 #include "llvm/Pass.h"
4452 #include "llvm/Support/CommandLine.h"
45 #include "llvm/Support/Debug.h"
4653 #include "llvm/Target/TargetInstrInfo.h"
54 #include "llvm/Target/TargetOpcodes.h"
55 #include "llvm/Target/TargetRegisterInfo.h"
4756 #include "llvm/Target/TargetSubtargetInfo.h"
57 #include
58 #include
59 #include
4860
4961 using namespace llvm;
5062
151163 const TargetInstrInfo *TII = nullptr;
152164 const TargetRegisterInfo *TRI = nullptr;
153165 AliasAnalysis *AA = nullptr;
154 MachineModuleInfo *MMI = nullptr;
155166 MachineFrameInfo *MFI = nullptr;
156167
157168 bool analyzeBlockForNullChecks(MachineBasicBlock &MBB,
165176 AR_MayAlias,
166177 AR_WillAliasEverything
167178 };
179
168180 /// Returns AR_NoAlias if \p MI memory operation does not alias with
169181 /// \p PrevMI, AR_MayAlias if they may alias and AR_WillAliasEverything if
170182 /// they may alias and any further memory operation may alias with \p PrevMI.
175187 SR_Unsuitable,
176188 SR_Impossible
177189 };
190
178191 /// Return SR_Suitable if \p MI a memory operation that can be used to
179192 /// implicitly null check the value in \p PointerReg, SR_Unsuitable if
180193 /// \p MI cannot be used to null check and SR_Impossible if there is
199212 }
200213
201214 bool runOnMachineFunction(MachineFunction &MF) override;
215
202216 void getAnalysisUsage(AnalysisUsage &AU) const override {
203217 AU.addRequired();
204218 MachineFunctionPass::getAnalysisUsage(AU);
210224 }
211225 };
212226
213 }
227 } // end anonymous namespace
214228
215229 bool ImplicitNullChecks::canHandle(const MachineInstr *MI) {
216230 if (MI->isCall() || MI->hasUnmodeledSideEffects())
229243 ImplicitNullChecks::computeDependence(const MachineInstr *MI,
230244 ArrayRef Block) {
231245 assert(llvm::all_of(Block, canHandle) && "Check this first!");
232 assert(!llvm::is_contained(Block, MI) && "Block must be exclusive of MI!");
246 assert(!is_contained(Block, MI) && "Block must be exclusive of MI!");
233247
234248 Optional::iterator> Dep;
235249
279293 bool ImplicitNullChecks::runOnMachineFunction(MachineFunction &MF) {
280294 TII = MF.getSubtarget().getInstrInfo();
281295 TRI = MF.getRegInfo().getTargetRegisterInfo();
282 MMI = &MF.getMMI();
283296 MFI = &MF.getFrameInfo();
284297 AA = &getAnalysis().getAAResults();
285298
442455 /// NullCheckList and return true, else return false.
443456 bool ImplicitNullChecks::analyzeBlockForNullChecks(
444457 MachineBasicBlock &MBB, SmallVectorImpl &NullCheckList) {
445 typedef TargetInstrInfo::MachineBranchPredicate MachineBranchPredicate;
458 using MachineBranchPredicate = TargetInstrInfo::MachineBranchPredicate;
446459
447460 MDNode *BranchMD = nullptr;
448461 if (auto *BB = MBB.getBasicBlock())
556569 }
557570
558571 // If MI re-defines the PointerReg then we cannot move further.
559 if (any_of(MI.operands(), [&](MachineOperand &MO) {
572 if (llvm::any_of(MI.operands(), [&](MachineOperand &MO) {
560573 return MO.isReg() && MO.getReg() && MO.isDef() &&
561574 TRI->regsOverlap(MO.getReg(), PointerReg);
562575 }))
675688 }
676689 }
677690
678
679691 char ImplicitNullChecks::ID = 0;
692
680693 char &llvm::ImplicitNullChecksID = ImplicitNullChecks::ID;
694
681695 INITIALIZE_PASS_BEGIN(ImplicitNullChecks, DEBUG_TYPE,
682696 "Implicit null checks", false, false)
683697 INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
None //===-------- InlineSpiller.cpp - Insert spills and restores inline -------===//
0 //===- InlineSpiller.cpp - Insert spills and restores inline --------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
1111 //
1212 //===----------------------------------------------------------------------===//
1313
14 #include "LiveRangeCalc.h"
1415 #include "Spiller.h"
1516 #include "SplitKit.h"
17 #include "llvm/ADT/ArrayRef.h"
18 #include "llvm/ADT/DenseMap.h"
1619 #include "llvm/ADT/MapVector.h"
20 #include "llvm/ADT/None.h"
21 #include "llvm/ADT/STLExtras.h"
1722 #include "llvm/ADT/SetVector.h"
23 #include "llvm/ADT/SmallPtrSet.h"
24 #include "llvm/ADT/SmallVector.h"
1825 #include "llvm/ADT/Statistic.h"
19 #include "llvm/ADT/TinyPtrVector.h"
2026 #include "llvm/Analysis/AliasAnalysis.h"
27 #include "llvm/CodeGen/LiveInterval.h"
2128 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
2229 #include "llvm/CodeGen/LiveRangeEdit.h"
2330 #include "llvm/CodeGen/LiveStackAnalysis.h"
31 #include "llvm/CodeGen/MachineBasicBlock.h"
2432 #include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
25 #include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
2633 #include "llvm/CodeGen/MachineDominators.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
2834 #include "llvm/CodeGen/MachineFunction.h"
35 #include "llvm/CodeGen/MachineFunctionPass.h"
36 #include "llvm/CodeGen/MachineInstr.h"
2937 #include "llvm/CodeGen/MachineInstrBuilder.h"
3038 #include "llvm/CodeGen/MachineInstrBundle.h"
3139 #include "llvm/CodeGen/MachineLoopInfo.h"
40 #include "llvm/CodeGen/MachineOperand.h"
3241 #include "llvm/CodeGen/MachineRegisterInfo.h"
42 #include "llvm/CodeGen/SlotIndexes.h"
3343 #include "llvm/CodeGen/VirtRegMap.h"
34 #include "llvm/IR/DebugInfo.h"
44 #include "llvm/Support/BlockFrequency.h"
45 #include "llvm/Support/BranchProbability.h"
3546 #include "llvm/Support/CommandLine.h"
47 #include "llvm/Support/Compiler.h"
3648 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/ErrorHandling.h"
3750 #include "llvm/Support/raw_ostream.h"
3851 #include "llvm/Target/TargetInstrInfo.h"
52 #include "llvm/Target/TargetOpcodes.h"
53 #include "llvm/Target/TargetRegisterInfo.h"
54 #include "llvm/Target/TargetSubtargetInfo.h"
55 #include
56 #include
57 #include
58 #include
59 #include
3960
4061 using namespace llvm;
4162
5576 cl::desc("Disable inline spill hoisting"));
5677
5778 namespace {
79
5880 class HoistSpillHelper : private LiveRangeEdit::Delegate {
5981 MachineFunction &MF;
6082 LiveIntervals &LIS;
6385 MachineDominatorTree &MDT;
6486 MachineLoopInfo &Loops;
6587 VirtRegMap &VRM;
66 MachineFrameInfo &MFI;
6788 MachineRegisterInfo &MRI;
6889 const TargetInstrInfo &TII;
6990 const TargetRegisterInfo &TRI;
7394
7495 // Map from StackSlot to its original register.
7596 DenseMap StackSlotToReg;
97
7698 // Map from pair of (StackSlot and Original VNI) to a set of spills which
7799 // have the same stackslot and have equal values defined by Original VNI.
78100 // These spills are mergeable and are hoist candiates.
79 typedef MapVector, SmallPtrSet>
80 MergeableSpillsMap;
101 using MergeableSpillsMap =
102 MapVector, SmallPtrSet>;
81103 MergeableSpillsMap MergeableSpills;
82104
83105 /// This is the map from original register to a set containing all its
113135 AA(&pass.getAnalysis().getAAResults()),
114136 MDT(pass.getAnalysis()),
115137 Loops(pass.getAnalysis()), VRM(vrm),
116 MFI(mf.getFrameInfo()), MRI(mf.getRegInfo()),
117 TII(*mf.getSubtarget().getInstrInfo()),
138 MRI(mf.getRegInfo()), TII(*mf.getSubtarget().getInstrInfo()),
118139 TRI(*mf.getSubtarget().getRegisterInfo()),
119140 MBFI(pass.getAnalysis()),
120141 IPA(LIS, mf.getNumBlockIDs()) {}
134155 MachineDominatorTree &MDT;
135156 MachineLoopInfo &Loops;
136157 VirtRegMap &VRM;
137 MachineFrameInfo &MFI;
138158 MachineRegisterInfo &MRI;
139159 const TargetInstrInfo &TII;
140160 const TargetRegisterInfo &TRI;
162182 // Object records spills information and does the hoisting.
163183 HoistSpillHelper HSpiller;
164184
165 ~InlineSpiller() override {}
185 ~InlineSpiller() override = default;
166186
167187 public:
168188 InlineSpiller(MachineFunctionPass &pass, MachineFunction &mf, VirtRegMap &vrm)
171191 AA(&pass.getAnalysis().getAAResults()),
172192 MDT(pass.getAnalysis()),
173193 Loops(pass.getAnalysis()), VRM(vrm),
174 MFI(mf.getFrameInfo()), MRI(mf.getRegInfo()),
175 TII(*mf.getSubtarget().getInstrInfo()),
194 MRI(mf.getRegInfo()), TII(*mf.getSubtarget().getInstrInfo()),
176195 TRI(*mf.getSubtarget().getRegisterInfo()),
177196 MBFI(pass.getAnalysis()),
178197 HSpiller(pass, mf, vrm) {}
195214 void reMaterializeAll();
196215
197216 bool coalesceStackAccess(MachineInstr *MI, unsigned Reg);
198 bool foldMemoryOperand(ArrayRef*, unsigned> >,
217 bool foldMemoryOperand(ArrayRef *, unsigned>>,
199218 MachineInstr *LoadMI = nullptr);
200219 void insertReload(unsigned VReg, SlotIndex, MachineBasicBlock::iterator MI);
201220 void insertSpill(unsigned VReg, bool isKill, MachineBasicBlock::iterator MI);
203222 void spillAroundUses(unsigned Reg);
204223 void spillAll();
205224 };
206 }
207
208 namespace llvm {
209
210 Spiller::~Spiller() { }
211 void Spiller::anchor() { }
212
213 Spiller *createInlineSpiller(MachineFunctionPass &pass,
214 MachineFunction &mf,
215 VirtRegMap &vrm) {
225
226 } // end anonymous namespace
227
228 Spiller::~Spiller() = default;
229
230 void Spiller::anchor() {}
231
232 Spiller *llvm::createInlineSpiller(MachineFunctionPass &pass,
233 MachineFunction &mf,
234 VirtRegMap &vrm) {
216235 return new InlineSpiller(pass, mf, vrm);
217 }
218
219236 }
220237
221238 //===----------------------------------------------------------------------===//
456473 } while (!WorkList.empty());
457474 }
458475
459
460476 //===----------------------------------------------------------------------===//
461477 // Rematerialization
462478 //===----------------------------------------------------------------------===//
495511
496512 /// reMaterializeFor - Attempt to rematerialize before MI instead of reloading.
497513 bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg, MachineInstr &MI) {
498
499514 // Analyze instruction
500515 SmallVector, 8> Ops;
501516 MIBundleOperands::VirtRegInfo RI =
653668 DEBUG(dbgs() << RegsToSpill.size() << " registers to spill after remat.\n");
654669 }
655670
656
657671 //===----------------------------------------------------------------------===//
658672 // Spilling
659673 //===----------------------------------------------------------------------===//
730744 /// @param LoadMI Load instruction to use instead of stack slot when non-null.
731745 /// @return True on success.
732746 bool InlineSpiller::
733 foldMemoryOperand(ArrayRef*, unsigned> > Ops,
747 foldMemoryOperand(ArrayRef *, unsigned>> Ops,
734748 MachineInstr *LoadMI) {
735749 if (Ops.empty())
736750 return false;
10751089 }
10761090
10771091 /// Optimizations after all the reg selections and spills are done.
1078 ///
10791092 void InlineSpiller::postOptimization() { HSpiller.hoistAllSpills(); }
10801093
10811094 /// When a spill is inserted, add the spill to MergeableSpills map.
1082 ///
10831095 void HoistSpillHelper::addToMergeableSpills(MachineInstr &Spill, int StackSlot,
10841096 unsigned Original) {
10851097 StackSlotToReg[StackSlot] = Original;
10911103
10921104 /// When a spill is removed, remove the spill from MergeableSpills map.
10931105 /// Return true if the spill is removed successfully.
1094 ///
10951106 bool HoistSpillHelper::rmFromMergeableSpills(MachineInstr &Spill,
10961107 int StackSlot) {
10971108 int Original = StackSlotToReg[StackSlot];
11051116
11061117 /// Check BB to see if it is a possible target BB to place a hoisted spill,
11071118 /// i.e., there should be a living sibling of OrigReg at the insert point.
1108 ///
11091119 bool HoistSpillHelper::isSpillCandBB(unsigned OrigReg, VNInfo &OrigVNI,
11101120 MachineBasicBlock &BB, unsigned &LiveReg) {
11111121 SlotIndex Idx;
11321142
11331143 /// Remove redundant spills in the same BB. Save those redundant spills in
11341144 /// SpillsToRm, and save the spill to keep and its BB in SpillBBToSpill map.
1135 ///
11361145 void HoistSpillHelper::rmRedundantSpills(
11371146 SmallPtrSet &Spills,
11381147 SmallVectorImpl &SpillsToRm,
11651174 /// time. \p SpillBBToSpill will be populated as part of the process and
11661175 /// maps a basic block to the first store occurring in the basic block.
11671176 /// \post SpillsToRm.union(Spills\@post) == Spills\@pre
1168 ///
11691177 void HoistSpillHelper::getVisitOrders(
11701178 MachineBasicBlock *Root, SmallPtrSet &Spills,
11711179 SmallVectorImpl &Orders,
12531261 /// Try to hoist spills according to BB hotness. The spills to removed will
12541262 /// be saved in \p SpillsToRm. The spills to be inserted will be saved in
12551263 /// \p SpillsToIns.
1256 ///
12571264 void HoistSpillHelper::runHoistSpills(
12581265 unsigned OrigReg, VNInfo &OrigVNI, SmallPtrSet &Spills,
12591266 SmallVectorImpl &SpillsToRm,
12791286 // nodes set and the cost of all the spills inside those nodes.
12801287 // The nodes set are the locations where spills are to be inserted
12811288 // in the subtree of current node.
1282 typedef std::pair, BlockFrequency>
1283 NodesCostPair;
1289 using NodesCostPair =
1290 std::pair, BlockFrequency>;
12841291 DenseMap SpillsInSubTreeMap;
1292
12851293 // Iterate Orders set in reverse order, which will be a bottom-up order
12861294 // in the dominator tree. Once we visit a dom tree node, we know its
12871295 // children have already been visited and the spill locations in the
13901398 /// bottom-up order, and for each node, we will decide whether to hoist spills
13911399 /// inside its subtree to that node. In this way, we can get benefit locally
13921400 /// even if hoisting all the equal spills to one cold place is impossible.
1393 ///
13941401 void HoistSpillHelper::hoistAllSpills() {
13951402 SmallVector NewVRegs;
13961403 LiveRangeEdit Edit(nullptr, NewVRegs, MF, LIS, &VRM, this);
1111 //===----------------------------------------------------------------------===//
1212
1313 #include "llvm/ADT/DenseMap.h"
14 #include "llvm/ADT/STLExtras.h"
1415 #include "llvm/ADT/SetVector.h"
1516 #include "llvm/ADT/SmallVector.h"
1617 #include "llvm/ADT/Statistic.h"
18 #include "llvm/ADT/iterator_range.h"
19 #include "llvm/CodeGen/MachineBasicBlock.h"
1720 #include "llvm/CodeGen/MachineFunction.h"
1821 #include "llvm/CodeGen/MachineFunctionPass.h"
22 #include "llvm/CodeGen/MachineInstr.h"
23 #include "llvm/CodeGen/MachineOperand.h"
1924 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/Passes.h"
25 #include "llvm/MC/MCRegisterInfo.h"
2126 #include "llvm/Pass.h"
2227 #include "llvm/Support/Debug.h"
2328 #include "llvm/Support/raw_ostream.h"
2429 #include "llvm/Target/TargetInstrInfo.h"
2530 #include "llvm/Target/TargetRegisterInfo.h"
2631 #include "llvm/Target/TargetSubtargetInfo.h"
32 #include
33 #include
34
2735 using namespace llvm;
2836
2937 #define DEBUG_TYPE "machine-cp"
3139 STATISTIC(NumDeletes, "Number of dead copies deleted");
3240
3341 namespace {
34 typedef SmallVector RegList;
35 typedef DenseMap SourceMap;
36 typedef DenseMap Reg2MIMap;
42
43 using RegList = SmallVector;
44 using SourceMap = DenseMap;
45 using Reg2MIMap = DenseMap;
3746
3847 class MachineCopyPropagation : public MachineFunctionPass {
3948 const TargetRegisterInfo *TRI;
4251
4352 public:
4453 static char ID; // Pass identification, replacement for typeid
54
4555 MachineCopyPropagation() : MachineFunctionPass(ID) {
4656 initializeMachineCopyPropagationPass(*PassRegistry::getPassRegistry());
4757 }
6676
6777 /// Candidates for deletion.
6878 SmallSetVector MaybeDeadCopies;
79
6980 /// Def -> available copies map.
7081 Reg2MIMap AvailCopyMap;
82
7183 /// Def -> copies map.
7284 Reg2MIMap CopyMap;
85
7386 /// Src -> Def map
7487 SourceMap SrcMap;
88
7589 bool Changed;
7690 };
77 }
91
92 } // end anonymous namespace
93
7894 char MachineCopyPropagation::ID = 0;
95
7996 char &llvm::MachineCopyPropagationID = MachineCopyPropagation::ID;
8097
8198 INITIALIZE_PASS(MachineCopyPropagation, DEBUG_TYPE,
373390
374391 return Changed;
375392 }
376
None //===-- MachineSink.cpp - Sinking for machine instructions ----------------===//
0 //===- MachineSink.cpp - Sinking for machine instructions -----------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
1717
1818 #include "llvm/ADT/SetVector.h"
1919 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/ADT/SmallVector.h"
2021 #include "llvm/ADT/SparseBitVector.h"
2122 #include "llvm/ADT/Statistic.h"
2223 #include "llvm/Analysis/AliasAnalysis.h"
3132 #include "llvm/CodeGen/MachineOperand.h"
3233 #include "llvm/CodeGen/MachinePostDominators.h"
3334 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/CodeGen/Passes.h"
35 #include "llvm/IR/BasicBlock.h"
3536 #include "llvm/IR/LLVMContext.h"
37 #include "llvm/Pass.h"
38 #include "llvm/Support/BranchProbability.h"
3639 #include "llvm/Support/CommandLine.h"
3740 #include "llvm/Support/Debug.h"
3841 #include "llvm/Support/raw_ostream.h"
9295 // Remember which edges we are about to split.
9396 // This is different from CEBCandidates since those edges
9497 // will be split.
95 SetVector*, MachineBasicBlock*> > ToSplit;
98 SetVector *, MachineBasicBlock *>> ToSplit;
9699
97100 SparseBitVector<> RegsToClearKillFlags;
98101
99 typedef std::map>
100 AllSuccsCache;
102 using AllSuccsCache =
103 std::map>;
101104
102105 public:
103106 static char ID; // Pass identification
132135 bool isWorthBreakingCriticalEdge(MachineInstr &MI,
133136 MachineBasicBlock *From,
134137 MachineBasicBlock *To);
138
135139 /// \brief Postpone the splitting of the given critical
136140 /// edge (\p From, \p To).
137141 ///
149153 MachineBasicBlock *To,
150154 bool BreakPHIEdge);
151155 bool SinkInstruction(MachineInstr &MI, bool &SawStore,
156
152157 AllSuccsCache &AllSuccessors);
153158 bool AllUsesDominatedByBlock(unsigned Reg, MachineBasicBlock *MBB,
154159 MachineBasicBlock *DefMBB,
171176 } // end anonymous namespace
172177
173178 char MachineSinking::ID = 0;
179
174180 char &llvm::MachineSinkingID = MachineSinking::ID;
181
175182 INITIALIZE_PASS_BEGIN(MachineSinking, DEBUG_TYPE,
176183 "Machine code sinking", false, false)
177184 INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo)
569576 SmallVector &
570577 MachineSinking::GetAllSortedSuccessors(MachineInstr &MI, MachineBasicBlock *MBB,
571578 AllSuccsCache &AllSuccessors) const {
572
573579 // Do we have the sorted successors in cache ?
574580 auto Succs = AllSuccessors.find(MBB);
575581 if (Succs != AllSuccessors.end())
710716 static bool SinkingPreventsImplicitNullCheck(MachineInstr &MI,
711717 const TargetInstrInfo *TII,
712718 const TargetRegisterInfo *TRI) {
713 typedef TargetInstrInfo::MachineBranchPredicate MachineBranchPredicate;
719 using MachineBranchPredicate = TargetInstrInfo::MachineBranchPredicate;
714720
715721 auto *MBB = MI.getParent();
716722 if (MBB->pred_size() != 1)
782788 // If there are no outputs, it must have side-effects.
783789 if (!SuccToSinkTo)
784790 return false;
785
786791
787792 // If the instruction to move defines a dead physical register which is live
788793 // when leaving the basic block, don't move it because it could turn into a
None //===--- llvm/CodeGen/Spiller.h - Spiller -*- C++ -*-----------------------===//
0 //===- llvm/CodeGen/Spiller.h - Spiller -------------------------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
1111
1212 namespace llvm {
1313
14 class LiveRangeEdit;
15 class MachineFunction;
16 class MachineFunctionPass;
17 class VirtRegMap;
18 class LiveIntervals;
14 class LiveRangeEdit;
15 class MachineFunction;
16 class MachineFunctionPass;
17 class VirtRegMap;
1918
2019 /// Spiller interface.
2120 ///
2322 /// demand.
2423 class Spiller {
2524 virtual void anchor();
25
2626 public:
2727 virtual ~Spiller() = 0;
2828
2929 /// spill - Spill the LRE.getParent() live interval.
3030 virtual void spill(LiveRangeEdit &LRE) = 0;
31 virtual void postOptimization(){};
31
32 virtual void postOptimization() {}
3233 };
3334
3435 /// Create and return a spiller that will insert spill code directly instead
3637 Spiller *createInlineSpiller(MachineFunctionPass &pass,
3738 MachineFunction &mf,
3839 VirtRegMap &vrm);
39 }
4040
41 #endif
41 } // end namespace llvm
42
43 #endif // LLVM_LIB_CODEGEN_SPILLER_H
None //===---------- SplitKit.cpp - Toolkit for splitting live ranges ----------===//
0 //===- SplitKit.cpp - Toolkit for splitting live ranges -------------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
1212 //===----------------------------------------------------------------------===//
1313
1414 #include "SplitKit.h"
15 #include "LiveRangeCalc.h"
16 #include "llvm/ADT/ArrayRef.h"
17 #include "llvm/ADT/DenseSet.h"
18 #include "llvm/ADT/None.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/SmallPtrSet.h"
21 #include "llvm/ADT/SmallVector.h"
1522 #include "llvm/ADT/Statistic.h"
23 #include "llvm/CodeGen/LiveInterval.h"
1624 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
1725 #include "llvm/CodeGen/LiveRangeEdit.h"
26 #include "llvm/CodeGen/MachineBasicBlock.h"
1827 #include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
1928 #include "llvm/CodeGen/MachineDominators.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstr.h"
2031 #include "llvm/CodeGen/MachineInstrBuilder.h"
2132 #include "llvm/CodeGen/MachineLoopInfo.h"
33 #include "llvm/CodeGen/MachineOperand.h"
2234 #include "llvm/CodeGen/MachineRegisterInfo.h"
35 #include "llvm/CodeGen/SlotIndexes.h"
2336 #include "llvm/CodeGen/VirtRegMap.h"
37 #include "llvm/IR/DebugLoc.h"
38 #include "llvm/MC/LaneBitmask.h"
39 #include "llvm/Support/Allocator.h"
40 #include "llvm/Support/BlockFrequency.h"
41 #include "llvm/Support/Compiler.h"
2442 #include "llvm/Support/Debug.h"
25 #include "llvm/Support/MathExtras.h"
43 #include "llvm/Support/ErrorHandling.h"
2644 #include "llvm/Support/raw_ostream.h"
2745 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Target/TargetMachine.h"
46 #include "llvm/Target/TargetOpcodes.h"
47 #include "llvm/Target/TargetRegisterInfo.h"
48 #include "llvm/Target/TargetSubtargetInfo.h"
49 #include
50 #include
51 #include
52 #include
53 #include
54 #include
2955
3056 using namespace llvm;
3157
124150 SplitAnalysis::SplitAnalysis(const VirtRegMap &vrm, const LiveIntervals &lis,
125151 const MachineLoopInfo &mli)
126152 : MF(vrm.getMachineFunction()), VRM(vrm), LIS(lis), Loops(mli),
127 TII(*MF.getSubtarget().getInstrInfo()), CurLI(nullptr),
128 IPA(lis, MF.getNumBlockIDs()) {}
153 TII(*MF.getSubtarget().getInstrInfo()), IPA(lis, MF.getNumBlockIDs()) {}
129154
130155 void SplitAnalysis::clear() {
131156 UseSlots.clear();
199224 // Loop over basic blocks where CurLI is live.
200225 MachineFunction::iterator MFI =
201226 LIS.getMBBFromIndex(LVI->start)->getIterator();
202 for (;;) {
227 while (true) {
203228 BlockInfo BI;
204229 BI.MBB = &*MFI;
205230 SlotIndex Start, Stop;
300325 MachineFunction::const_iterator MFI =
301326 LIS.getMBBFromIndex(LVI->start)->getIterator();
302327 SlotIndex Stop = LIS.getMBBEndIdx(&*MFI);
303 for (;;) {
328 while (true) {
304329 ++Count;
305330 LVI = li->advanceTo(LVI, Stop);
306331 if (LVI == LVE)
331356 CurLI = li;
332357 analyzeUses();
333358 }
334
335359
336360 //===----------------------------------------------------------------------===//
337361 // Split Editor
346370 MRI(vrm.getMachineFunction().getRegInfo()), MDT(mdt),
347371 TII(*vrm.getMachineFunction().getSubtarget().getInstrInfo()),
348372 TRI(*vrm.getMachineFunction().getSubtarget().getRegisterInfo()),
349 MBFI(mbfi), Edit(nullptr), OpenIdx(0), SpillMode(SM_Partition),
350 RegAssign(Allocator) {}
373 MBFI(mbfi), RegAssign(Allocator) {}
351374
352375 void SplitEditor::reset(LiveRangeEdit &LRE, ComplementSpillMode SM) {
353376 Edit = &LRE;
571594 LaneBitmask LanesLeft = LaneMask & ~(TRI.getSubRegIndexLaneMask(BestIdx));
572595 while (LanesLeft.any()) {
573596 unsigned BestIdx = 0;
574 int BestCover = INT_MIN;
597 int BestCover = std::numeric_limits::min();
575598 for (unsigned Idx : PossibleIndexes) {
576599 LaneBitmask SubRegMask = TRI.getSubRegIndexLaneMask(Idx);
577600 // Early exit if we found a perfect match.
874897
875898 // Best candidate so far.
876899 MachineBasicBlock *BestMBB = MBB;
877 unsigned BestDepth = UINT_MAX;
878
879 for (;;) {
900 unsigned BestDepth = std::numeric_limits::max();
901
902 while (true) {
880903 const MachineLoop *Loop = Loops.getLoopFor(MBB);
881904
882905 // MBB isn't in a loop, it doesn't get any better. All dominators have a
9771000
9781001 // Track the nearest common dominator for all back-copies for each ParentVNI,
9791002 // indexed by ParentVNI->id.
980 typedef std::pair DomPair;
1003 using DomPair = std::pair;
9811004 SmallVector NearestDom(Parent->getNumValNums());
9821005 // The total cost of all the back-copies for each ParentVNI.
9831006 SmallVector Costs(Parent->getNumValNums());
10861109
10871110 removeBackCopies(BackCopies);
10881111 }
1089
10901112
10911113 /// transferValues - Transfer all possible values to the new live ranges.
10921114 /// Values that were rematerialized are left alone, they need LRCalc.extend().
12751297 struct ExtPoint {
12761298 ExtPoint(const MachineOperand &O, unsigned R, SlotIndex N)
12771299 : MO(O), RegIdx(R), Next(N) {}
1300
12781301 MachineOperand MO;
12791302 unsigned RegIdx;
12801303 SlotIndex Next;
14851508 assert(!LRMap || LRMap->size() == Edit->size());
14861509 }
14871510
1488
14891511 //===----------------------------------------------------------------------===//
14901512 // Single Block Splitting
14911513 //===----------------------------------------------------------------------===//
15231545 }
15241546 }
15251547
1526
15271548 //===----------------------------------------------------------------------===//
15281549 // Global Live Range Splitting Support
15291550 //===----------------------------------------------------------------------===//
16371658 useIntv(Start, Idx);
16381659 assert((!LeaveBefore || Idx <= LeaveBefore) && "Interference");
16391660 }
1640
16411661
16421662 void SplitEditor::splitRegInBlock(const SplitAnalysis::BlockInfo &BI,
16431663 unsigned IntvIn, SlotIndex LeaveBefore) {
None //===-------- SplitKit.h - Toolkit for splitting live ranges ----*- C++ -*-===//
0 //===- SplitKit.h - Toolkit for splitting live ranges -----------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
1616
1717 #include "LiveRangeCalc.h"
1818 #include "llvm/ADT/ArrayRef.h"
19 #include "llvm/ADT/BitVector.h"
1920 #include "llvm/ADT/DenseMap.h"
2021 #include "llvm/ADT/DenseSet.h"
2122 #include "llvm/ADT/IntervalMap.h"
23 #include "llvm/ADT/PointerIntPair.h"
2224 #include "llvm/ADT/SmallPtrSet.h"
25 #include "llvm/ADT/SmallVector.h"
26 #include "llvm/CodeGen/LiveInterval.h"
27 #include "llvm/CodeGen/MachineBasicBlock.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/SlotIndexes.h"
30 #include "llvm/MC/LaneBitmask.h"
31 #include "llvm/Support/Compiler.h"
32 #include
2333
2434 namespace llvm {
2535
26 class ConnectedVNInfoEqClasses;
27 class LiveInterval;
2836 class LiveIntervals;
2937 class LiveRangeEdit;
3038 class MachineBlockFrequencyInfo;
31 class MachineInstr;
39 class MachineDominatorTree;
3240 class MachineLoopInfo;
3341 class MachineRegisterInfo;
3442 class TargetInstrInfo;
3543 class TargetRegisterInfo;
3644 class VirtRegMap;
37 class VNInfo;
38 class raw_ostream;
3945
4046 /// Determines the latest safe point in a block in which we can insert a split,
4147 /// spill or other instruction related with CurLI.
115121
116122 private:
117123 // Current live interval.
118 const LiveInterval *CurLI;
124 const LiveInterval *CurLI = nullptr;
119125
120126 /// Insert Point Analysis.
121127 InsertPointAnalysis IPA;
199205 /// analyze(li).
200206 unsigned countLiveBlocks(const LiveInterval *li) const;
201207
202 typedef SmallPtrSet BlockPtrSet;
208 using BlockPtrSet = SmallPtrSet;
203209
204210 /// shouldSplitSingleBlock - Returns true if it would help to create a local
205211 /// live range for the instructions in BI. There is normally no benefit to
219225 return IPA.getLastInsertPointIter(*CurLI, *BB);
220226 }
221227 };
222
223228
224229 /// SplitEditor - Edit machine code and LiveIntervals for live range
225230 /// splitting.
244249 const MachineBlockFrequencyInfo &MBFI;
245250
246251 public:
247
248252 /// ComplementSpillMode - Select how the complement live range should be
249253 /// created. SplitEditor automatically creates interval 0 to contain
250254 /// anything that isn't added to another interval. This complement interval
272276 };
273277
274278 private:
275
276279 /// Edit - The current parent register and new intervals created.
277 LiveRangeEdit *Edit;
280 LiveRangeEdit *Edit = nullptr;
278281
279282 /// Index into Edit of the currently open interval.
280283 /// The index 0 is used for the complement, so the first interval started by
281284 /// openIntv will be 1.
282 unsigned OpenIdx;
285 unsigned OpenIdx = 0;
283286
284287 /// The current spill mode, selected by reset().
285 ComplementSpillMode SpillMode;
286
287 typedef IntervalMap RegAssignMap;
288 ComplementSpillMode SpillMode = SM_Partition;
289
290 using RegAssignMap = IntervalMap;
288291
289292 /// Allocator for the interval map. This will eventually be shared with
290293 /// SlotIndexes and LiveIntervals.
295298 /// Idx.
296299 RegAssignMap RegAssign;
297300
298 typedef PointerIntPair ValueForcePair;
299 typedef DenseMap, ValueForcePair> ValueMap;
301 using ValueForcePair = PointerIntPair;
302 using ValueMap = DenseMap, ValueForcePair>;
300303
301304 /// Values - keep track of the mapping from parent values to values in the new
302305 /// intervals. Given a pair (RegIdx, ParentVNI->id), Values contains:
418421 public:
419422 /// Create a new SplitEditor for editing the LiveInterval analyzed by SA.
420423 /// Newly created intervals will be appended to newIntervals.
421 SplitEditor(SplitAnalysis &SA, AliasAnalysis &AA, LiveIntervals&,
422 VirtRegMap&, MachineDominatorTree&,
423 MachineBlockFrequencyInfo &);
424 SplitEditor(SplitAnalysis &sa, AliasAnalysis &aa, LiveIntervals &lis,
425 VirtRegMap &vrm, MachineDominatorTree &mdt,
426 MachineBlockFrequencyInfo &mbfi);
424427
425428 /// reset - Prepare for a new split.
426429 void reset(LiveRangeEdit&, ComplementSpillMode = SM_Partition);
535538 unsigned IntvOut, SlotIndex EnterAfter);
536539 };
537540
538 }
539
540 #endif
541 } // end namespace llvm
542
543 #endif // LLVM_LIB_CODEGEN_SPLITKIT_H