llvm.org GIT mirror llvm / 7c90f73
Rename SPARC V8 target to be the LLVM SPARC target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25985 91177308-0d34-0410-b5e6-96231b3b80d8 Chris Lattner 13 years ago
18 changed file(s) with 556 addition(s) and 562 deletion(s). Raw diff Collapse all Expand all
None //===-- DelaySlotFiller.cpp - SparcV8 delay slot filler -------------------===//
0 //===-- DelaySlotFiller.cpp - SPARC delay slot filler ---------------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
1010 //
1111 //===----------------------------------------------------------------------===//
1212
13 #include "SparcV8.h"
13 #include "Sparc.h"
1414 #include "llvm/CodeGen/MachineFunctionPass.h"
1515 #include "llvm/CodeGen/MachineInstrBuilder.h"
1616 #include "llvm/Target/TargetMachine.h"
1717 #include "llvm/Target/TargetInstrInfo.h"
1818 #include "llvm/ADT/Statistic.h"
19
2019 using namespace llvm;
2120
2221 namespace {
23 Statistic<> FilledSlots ("delayslotfiller", "Num. of delay slots filled");
22 Statistic<> FilledSlots("delayslotfiller", "Num. of delay slots filled");
2423
2524 struct Filler : public MachineFunctionPass {
2625 /// Target machine description which we query for reg. names, data
2928 TargetMachine &TM;
3029 const TargetInstrInfo *TII;
3130
32 Filler (TargetMachine &tm) : TM (tm), TII (tm.getInstrInfo ()) { }
31 Filler(TargetMachine &tm) : TM(tm), TII(tm.getInstrInfo()) { }
3332
34 virtual const char *getPassName () const {
35 return "SparcV8 Delay Slot Filler";
33 virtual const char *getPassName() const {
34 return "SPARC Delay Slot Filler";
3635 }
3736
38 bool runOnMachineBasicBlock (MachineBasicBlock &MBB);
39 bool runOnMachineFunction (MachineFunction &F) {
37 bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
38 bool runOnMachineFunction(MachineFunction &F) {
4039 bool Changed = false;
41 for (MachineFunction::iterator FI = F.begin (), FE = F.end ();
40 for (MachineFunction::iterator FI = F.begin(), FE = F.end();
4241 FI != FE; ++FI)
43 Changed |= runOnMachineBasicBlock (*FI);
42 Changed |= runOnMachineBasicBlock(*FI);
4443 return Changed;
4544 }
4645
4746 };
4847 } // end of anonymous namespace
4948
50 /// createSparcV8DelaySlotFillerPass - Returns a pass that fills in delay
51 /// slots in SparcV8 MachineFunctions
49 /// createSparcDelaySlotFillerPass - Returns a pass that fills in delay
50 /// slots in Sparc MachineFunctions
5251 ///
53 FunctionPass *llvm::createSparcV8DelaySlotFillerPass (TargetMachine &tm) {
54 return new Filler (tm);
52 FunctionPass *llvm::createSparcDelaySlotFillerPass(TargetMachine &tm) {
53 return new Filler(tm);
5554 }
5655
5756 /// runOnMachineBasicBlock - Fill in delay slots for the given basic block.
5857 /// Currently, we fill delay slots with NOPs. We assume there is only one
5958 /// delay slot per delayed instruction.
6059 ///
61 bool Filler::runOnMachineBasicBlock (MachineBasicBlock &MBB) {
60 bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
6261 bool Changed = false;
63 for (MachineBasicBlock::iterator I = MBB.begin (); I != MBB.end (); ++I)
64 if (TII->hasDelaySlot (I->getOpcode ())) {
62 for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I)
63 if (TII->hasDelaySlot(I->getOpcode())) {
6564 MachineBasicBlock::iterator J = I;
6665 ++J;
67 BuildMI (MBB, J, V8::NOP, 0);
66 BuildMI(MBB, J, SP::NOP, 0);
6867 ++FilledSlots;
6968 Changed = true;
7069 }
None //===-- FPMover.cpp - SparcV8 double-precision floating point move fixer --===//
0 //===-- FPMover.cpp - Sparc double-precision floating point move fixer ----===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
1010 //
1111 //===----------------------------------------------------------------------===//
1212
13 #include "SparcV8.h"
14 #include "SparcV8Subtarget.h"
13 #include "Sparc.h"
14 #include "SparcSubtarget.h"
1515 #include "llvm/CodeGen/MachineFunctionPass.h"
1616 #include "llvm/CodeGen/MachineInstrBuilder.h"
1717 #include "llvm/Target/TargetMachine.h"
3333 FPMover(TargetMachine &tm) : TM(tm) { }
3434
3535 virtual const char *getPassName() const {
36 return "SparcV8 Double-FP Move Fixer";
36 return "Sparc Double-FP Move Fixer";
3737 }
3838
3939 bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
4141 };
4242 } // end of anonymous namespace
4343
44 /// createSparcV8FPMoverPass - Returns a pass that turns FpMOVD
44 /// createSparcFPMoverPass - Returns a pass that turns FpMOVD
4545 /// instructions into FMOVS instructions
4646 ///
47 FunctionPass *llvm::createSparcV8FPMoverPass(TargetMachine &tm) {
47 FunctionPass *llvm::createSparcFPMoverPass(TargetMachine &tm) {
4848 return new FPMover(tm);
4949 }
5050
5353 static void getDoubleRegPair(unsigned DoubleReg, unsigned &EvenReg,
5454 unsigned &OddReg) {
5555 static const unsigned EvenHalvesOfPairs[] = {
56 V8::F0, V8::F2, V8::F4, V8::F6, V8::F8, V8::F10, V8::F12, V8::F14,
57 V8::F16, V8::F18, V8::F20, V8::F22, V8::F24, V8::F26, V8::F28, V8::F30
56 SP::F0, SP::F2, SP::F4, SP::F6, SP::F8, SP::F10, SP::F12, SP::F14,
57 SP::F16, SP::F18, SP::F20, SP::F22, SP::F24, SP::F26, SP::F28, SP::F30
5858 };
5959 static const unsigned OddHalvesOfPairs[] = {
60 V8::F1, V8::F3, V8::F5, V8::F7, V8::F9, V8::F11, V8::F13, V8::F15,
61 V8::F17, V8::F19, V8::F21, V8::F23, V8::F25, V8::F27, V8::F29, V8::F31
60 SP::F1, SP::F3, SP::F5, SP::F7, SP::F9, SP::F11, SP::F13, SP::F15,
61 SP::F17, SP::F19, SP::F21, SP::F23, SP::F25, SP::F27, SP::F29, SP::F31
6262 };
6363 static const unsigned DoubleRegsInOrder[] = {
64 V8::D0, V8::D1, V8::D2, V8::D3, V8::D4, V8::D5, V8::D6, V8::D7, V8::D8,
65 V8::D9, V8::D10, V8::D11, V8::D12, V8::D13, V8::D14, V8::D15
64 SP::D0, SP::D1, SP::D2, SP::D3, SP::D4, SP::D5, SP::D6, SP::D7, SP::D8,
65 SP::D9, SP::D10, SP::D11, SP::D12, SP::D13, SP::D14, SP::D15
6666 };
6767 for (unsigned i = 0; i < sizeof(DoubleRegsInOrder)/sizeof(unsigned); ++i)
6868 if (DoubleRegsInOrder[i] == DoubleReg) {
7979 bool Changed = false;
8080 for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ) {
8181 MachineInstr *MI = I++;
82 if (MI->getOpcode() == V8::FpMOVD || MI->getOpcode() == V8::FpABSD ||
83 MI->getOpcode() == V8::FpNEGD) {
82 if (MI->getOpcode() == SP::FpMOVD || MI->getOpcode() == SP::FpABSD ||
83 MI->getOpcode() == SP::FpNEGD) {
8484 Changed = true;
8585 unsigned DestDReg = MI->getOperand(0).getReg();
8686 unsigned SrcDReg = MI->getOperand(1).getReg();
87 if (DestDReg == SrcDReg && MI->getOpcode() == V8::FpMOVD) {
87 if (DestDReg == SrcDReg && MI->getOpcode() == SP::FpMOVD) {
8888 MBB.erase(MI); // Eliminate the noop copy.
8989 ++NoopFpDs;
9090 continue;
9494 getDoubleRegPair(DestDReg, EvenDestReg, OddDestReg);
9595 getDoubleRegPair(SrcDReg, EvenSrcReg, OddSrcReg);
9696
97 if (MI->getOpcode() == V8::FpMOVD)
98 MI->setOpcode(V8::FMOVS);
99 else if (MI->getOpcode() == V8::FpNEGD)
100 MI->setOpcode(V8::FNEGS);
101 else if (MI->getOpcode() == V8::FpABSD)
102 MI->setOpcode(V8::FABSS);
97 if (MI->getOpcode() == SP::FpMOVD)
98 MI->setOpcode(SP::FMOVS);
99 else if (MI->getOpcode() == SP::FpNEGD)
100 MI->setOpcode(SP::FNEGS);
101 else if (MI->getOpcode() == SP::FpABSD)
102 MI->setOpcode(SP::FABSS);
103103 else
104104 assert(0 && "Unknown opcode!");
105105
108108 DEBUG(std::cerr << "FPMover: the modified instr is: " << *MI);
109109 // Insert copy for the other half of the double.
110110 if (DestDReg != SrcDReg) {
111 MI = BuildMI(MBB, I, V8::FMOVS, 1, OddDestReg).addReg(OddSrcReg);
111 MI = BuildMI(MBB, I, SP::FMOVS, 1, OddDestReg).addReg(OddSrcReg);
112112 DEBUG(std::cerr << "FPMover: the inserted instr is: " << *MI);
113113 }
114114 ++NumFpDs;
120120 bool FPMover::runOnMachineFunction(MachineFunction &F) {
121121 // If the target has V9 instructions, the fp-mover pseudos will never be
122122 // emitted. Avoid a scan of the instructions to improve compile time.
123 if (TM.getSubtargetV8Subtarget>().isV9())
123 if (TM.getSubtargetSubtarget>().isV9())
124124 return false;
125125
126126 bool Changed = false;
None ##===- lib/Target/SparcV8/Makefile -------------------------*- Makefile -*-===##
0 ##===- lib/Target/Sparc/Makefile ---------------------------*- Makefile -*-===##
11 #
22 # The LLVM Compiler Infrastructure
33 #
66 #
77 ##===----------------------------------------------------------------------===##
88 LEVEL = ../../..
9 LIBRARYNAME = LLVMSparcV8
10 TARGET = SparcV8
9 LIBRARYNAME = LLVMSparc
10 TARGET = Sparc
1111
1212 # Make sure that tblgen is run, first thing.
13 BUILT_SOURCES = SparcV8GenRegisterInfo.h.inc SparcV8GenRegisterNames.inc \
14 SparcV8GenRegisterInfo.inc SparcV8GenInstrNames.inc \
15 SparcV8GenInstrInfo.inc SparcV8GenAsmWriter.inc \
16 SparcV8GenDAGISel.inc SparcV8GenSubtarget.inc
13 BUILT_SOURCES = SparcGenRegisterInfo.h.inc SparcGenRegisterNames.inc \
14 SparcGenRegisterInfo.inc SparcGenInstrNames.inc \
15 SparcGenInstrInfo.inc SparcGenAsmWriter.inc \
16 SparcGenDAGISel.inc SparcGenSubtarget.inc
1717
1818 include $(LEVEL)/Makefile.common
1919
None //===-- SparcV8.h - Top-level interface for SparcV8 representation -*- C++ -*-//
0 //===-- Sparc.h - Top-level interface for Sparc representation --*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
77 //===----------------------------------------------------------------------===//
88 //
99 // This file contains the entry points for global functions defined in the LLVM
10 // SparcV8 back-end.
10 // Sparc back-end.
1111 //
1212 //===----------------------------------------------------------------------===//
1313
14 #ifndef TARGET_SPARCV8_H
15 #define TARGET_SPARCV8_H
14 #ifndef TARGET_SPARC_H
15 #define TARGET_SPARC_H
1616
1717 #include
1818 #include
1919
2020 namespace llvm {
21
2221 class FunctionPass;
2322 class TargetMachine;
2423
25 FunctionPass *createSparcV8ISelDag(TargetMachine &TM);
26
27 FunctionPass *createSparcV8CodePrinterPass(std::ostream &OS,
28 TargetMachine &TM);
29 FunctionPass *createSparcV8DelaySlotFillerPass(TargetMachine &TM);
30 FunctionPass *createSparcV8FPMoverPass(TargetMachine &TM);
24 FunctionPass *createSparcISelDag(TargetMachine &TM);
25 FunctionPass *createSparcCodePrinterPass(std::ostream &OS, TargetMachine &TM);
26 FunctionPass *createSparcDelaySlotFillerPass(TargetMachine &TM);
27 FunctionPass *createSparcFPMoverPass(TargetMachine &TM);
3128 } // end namespace llvm;
3229
33 // Defines symbolic names for SparcV8 registers. This defines a mapping from
30 // Defines symbolic names for Sparc registers. This defines a mapping from
3431 // register name to register number.
3532 //
36 #include "SparcV8GenRegisterNames.inc"
33 #include "SparcGenRegisterNames.inc"
3734
38 // Defines symbolic names for the SparcV8 instructions.
35 // Defines symbolic names for the Sparc instructions.
3936 //
40 #include "SparcV8GenInstrNames.inc"
37 #include "SparcGenInstrNames.inc"
4138
4239
4340 namespace llvm {
44 // Enums corresponding to SparcV8 condition codes, both icc's and fcc's. These
41 // Enums corresponding to Sparc condition codes, both icc's and fcc's. These
4542 // values must be kept in sync with the ones in the .td file.
46 namespace V8CC {
43 namespace SPCC {
4744 enum CondCodes {
4845 //ICC_A = 8 , // Always
4946 //ICC_N = 0 , // Never
8178 };
8279 }
8380
84 static const char *SPARCCondCodeToString(V8CC::CondCodes CC) {
81 static const char *SPARCCondCodeToString(SPCC::CondCodes CC) {
8582 switch (CC) {
8683 default: assert(0 && "Unknown condition code");
87 case V8CC::ICC_NE: return "ne";
88 case V8CC::ICC_E: return "e";
89 case V8CC::ICC_G: return "g";
90 case V8CC::ICC_LE: return "le";
91 case V8CC::ICC_GE: return "ge";
92 case V8CC::ICC_L: return "l";
93 case V8CC::ICC_GU: return "gu";
94 case V8CC::ICC_LEU: return "leu";
95 case V8CC::ICC_CC: return "cc";
96 case V8CC::ICC_CS: return "cs";
97 case V8CC::ICC_POS: return "pos";
98 case V8CC::ICC_NEG: return "neg";
99 case V8CC::ICC_VC: return "vc";
100 case V8CC::ICC_VS: return "vs";
101 case V8CC::FCC_U: return "u";
102 case V8CC::FCC_G: return "g";
103 case V8CC::FCC_UG: return "ug";
104 case V8CC::FCC_L: return "l";
105 case V8CC::FCC_UL: return "ul";
106 case V8CC::FCC_LG: return "lg";
107 case V8CC::FCC_NE: return "ne";
108 case V8CC::FCC_E: return "e";
109 case V8CC::FCC_UE: return "ue";
110 case V8CC::FCC_GE: return "ge";
111 case V8CC::FCC_UGE: return "uge";
112 case V8CC::FCC_LE: return "le";
113 case V8CC::FCC_ULE: return "ule";
114 case V8CC::FCC_O: return "o";
84 case SPCC::ICC_NE: return "ne";
85 case SPCC::ICC_E: return "e";
86 case SPCC::ICC_G: return "g";
87 case SPCC::ICC_LE: return "le";
88 case SPCC::ICC_GE: return "ge";
89 case SPCC::ICC_L: return "l";
90 case SPCC::ICC_GU: return "gu";
91 case SPCC::ICC_LEU: return "leu";
92 case SPCC::ICC_CC: return "cc";
93 case SPCC::ICC_CS: return "cs";
94 case SPCC::ICC_POS: return "pos";
95 case SPCC::ICC_NEG: return "neg";
96 case SPCC::ICC_VC: return "vc";
97 case SPCC::ICC_VS: return "vs";
98 case SPCC::FCC_U: return "u";
99 case SPCC::FCC_G: return "g";
100 case SPCC::FCC_UG: return "ug";
101 case SPCC::FCC_L: return "l";
102 case SPCC::FCC_UL: return "ul";
103 case SPCC::FCC_LG: return "lg";
104 case SPCC::FCC_NE: return "ne";
105 case SPCC::FCC_E: return "e";
106 case SPCC::FCC_UE: return "ue";
107 case SPCC::FCC_GE: return "ge";
108 case SPCC::FCC_UGE: return "uge";
109 case SPCC::FCC_LE: return "le";
110 case SPCC::FCC_ULE: return "ule";
111 case SPCC::FCC_O: return "o";
115112 }
116113 }
117114 } // end namespace llvm
None //===- SparcV8.td - Describe the SparcV8 Target Machine ---------*- C++ -*-===//
0 //===- Sparc.td - Describe the Sparc Target Machine -------------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
3333 // Register File Description
3434 //===----------------------------------------------------------------------===//
3535
36 include "SparcV8RegisterInfo.td"
36 include "SparcRegisterInfo.td"
3737
3838 //===----------------------------------------------------------------------===//
3939 // Instruction Descriptions
4040 //===----------------------------------------------------------------------===//
4141
42 include "SparcV8InstrInfo.td"
42 include "SparcInstrInfo.td"
4343
44 def SparcV8InstrInfo : InstrInfo {
44 def SparcInstrInfo : InstrInfo {
4545 // Define how we want to layout our target-specific information field.
4646 let TSFlagsFields = [];
4747 let TSFlagsShifts = [];
7373 // Declare the target which we are implementing
7474 //===----------------------------------------------------------------------===//
7575
76 def SparcV8 : Target {
76 def Sparc : Target {
7777 // Pointers are 32-bits in size.
7878 let PointerType = i32;
7979
8181 let CalleeSavedRegisters = [];
8282
8383 // Pull in Instruction Info:
84 let InstructionSet = SparcV8InstrInfo;
84 let InstructionSet = SparcInstrInfo;
8585 }
None //===-- SparcV8AsmPrinter.cpp - SparcV8 LLVM assembly writer --------------===//
0 //===-- SparcAsmPrinter.cpp - Sparc LLVM assembly writer ------------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
77 //===----------------------------------------------------------------------===//
88 //
99 // This file contains a printer that converts from our internal representation
10 // of machine-dependent LLVM code to GAS-format Sparc V8 assembly language.
10 // of machine-dependent LLVM code to GAS-format SPARC assembly language.
1111 //
1212 //===----------------------------------------------------------------------===//
1313
14 #include "SparcV8.h"
15 #include "SparcV8InstrInfo.h"
14 #include "Sparc.h"
15 #include "SparcInstrInfo.h"
1616 #include "llvm/Constants.h"
1717 #include "llvm/DerivedTypes.h"
1818 #include "llvm/Module.h"
3434 namespace {
3535 Statistic<> EmittedInsts("asm-printer", "Number of machine instrs printed");
3636
37 struct SparcV8AsmPrinter : public AsmPrinter {
38 SparcV8AsmPrinter(std::ostream &O, TargetMachine &TM) : AsmPrinter(O, TM) {
37 struct SparcAsmPrinter : public AsmPrinter {
38 SparcAsmPrinter(std::ostream &O, TargetMachine &TM) : AsmPrinter(O, TM) {
3939 Data16bitsDirective = "\t.half\t";
4040 Data32bitsDirective = "\t.word\t";
4141 Data64bitsDirective = 0; // .xword is only supported by V9.
5252 ValueMapTy NumberForBB;
5353
5454 virtual const char *getPassName() const {
55 return "SparcV8 Assembly Printer";
55 return "Sparc Assembly Printer";
5656 }
5757
5858 void printOperand(const MachineInstr *MI, int opNum);
5959 void printMemOperand(const MachineInstr *MI, int opNum);
60 void printV8CCOperand(const MachineInstr *MI, int opNum);
60 void printCCOperand(const MachineInstr *MI, int opNum);
6161
6262 bool printInstruction(const MachineInstr *MI); // autogenerated.
6363 bool runOnMachineFunction(MachineFunction &F);
6666 };
6767 } // end of anonymous namespace
6868
69 #include "SparcV8GenAsmWriter.inc"
70
71 /// createSparcV8CodePrinterPass - Returns a pass that prints the SparcV8
69 #include "SparcGenAsmWriter.inc"
70
71 /// createSparcCodePrinterPass - Returns a pass that prints the SPARC
7272 /// assembly code for a MachineFunction to the given output stream,
7373 /// using the given target machine description. This should work
7474 /// regardless of whether the function is in SSA form.
7575 ///
76 FunctionPass *llvm::createSparcV8CodePrinterPass (std::ostream &o,
77 TargetMachine &tm) {
78 return new SparcV8AsmPrinter(o, tm);
76 FunctionPass *llvm::createSparcCodePrinterPass(std::ostream &o,
77 TargetMachine &tm) {
78 return new SparcAsmPrinter(o, tm);
7979 }
8080
8181 /// runOnMachineFunction - This uses the printMachineInstruction()
8282 /// method to print assembly for each instruction.
8383 ///
84 bool SparcV8AsmPrinter::runOnMachineFunction(MachineFunction &MF) {
84 bool SparcAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
8585 SetupMachineFunction(MF);
8686
8787 // Print out constants referenced by the function
131131 return false;
132132 }
133133
134 void SparcV8AsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
134 void SparcAsmPrinter::printOperand(const MachineInstr *MI, int opNum) {
135135 const MachineOperand &MO = MI->getOperand (opNum);
136136 const MRegisterInfo &RI = *TM.getRegisterInfo();
137137 bool CloseParen = false;
138 if (MI->getOpcode() == V8::SETHIi && !MO.isRegister() && !MO.isImmediate()) {
138 if (MI->getOpcode() == SP::SETHIi && !MO.isRegister() && !MO.isImmediate()) {
139139 O << "%hi(";
140140 CloseParen = true;
141 } else if ((MI->getOpcode() == V8::ORri || MI->getOpcode() == V8::ADDri)
141 } else if ((MI->getOpcode() == SP::ORri || MI->getOpcode() == SP::ADDri)
142142 && !MO.isRegister() && !MO.isImmediate()) {
143143 O << "%lo(";
144144 CloseParen = true;
169169 return;
170170 }
171171 case MachineOperand::MO_PCRelativeDisp:
172 std::cerr << "Shouldn't use addPCDisp() when building SparcV8 MachineInstrs";
172 std::cerr << "Shouldn't use addPCDisp() when building Sparc MachineInstrs";
173173 abort ();
174174 return;
175175 case MachineOperand::MO_GlobalAddress:
188188 if (CloseParen) O << ")";
189189 }
190190
191 void SparcV8AsmPrinter::printMemOperand(const MachineInstr *MI, int opNum) {
191 void SparcAsmPrinter::printMemOperand(const MachineInstr *MI, int opNum) {
192192 printOperand(MI, opNum);
193193 MachineOperand::MachineOperandType OpTy = MI->getOperand(opNum+1).getType();
194194
195195 if ((OpTy == MachineOperand::MO_VirtualRegister ||
196196 OpTy == MachineOperand::MO_MachineRegister) &&
197 MI->getOperand(opNum+1).getReg() == V8::G0)
197 MI->getOperand(opNum+1).getReg() == SP::G0)
198198 return; // don't print "+%g0"
199199 if ((OpTy == MachineOperand::MO_SignExtendedImmed ||
200200 OpTy == MachineOperand::MO_UnextendedImmed) &&
212212 }
213213 }
214214
215 void SparcV8AsmPrinter::printV8CCOperand(const MachineInstr *MI, int opNum) {
215 void SparcAsmPrinter::printCCOperand(const MachineInstr *MI, int opNum) {
216216 int CC = (int)MI->getOperand(opNum).getImmedValue();
217 O << SPARCCondCodeToString((V8CC::CondCodes)CC);
218 }
219
220
221
222 bool SparcV8AsmPrinter::doInitialization(Module &M) {
217 O << SPARCCondCodeToString((SPCC::CondCodes)CC);
218 }
219
220
221
222 bool SparcAsmPrinter::doInitialization(Module &M) {
223223 Mang = new Mangler(M);
224224 return false; // success
225225 }
226226
227 bool SparcV8AsmPrinter::doFinalization(Module &M) {
227 bool SparcAsmPrinter::doFinalization(Module &M) {
228228 const TargetData &TD = TM.getTargetData();
229229
230230 // Print out module-level global variables here.
None //===-- SparcV8ISelDAGToDAG.cpp - A dag to dag inst selector for SparcV8 --===//
0 //===-- SparcISelDAGToDAG.cpp - A dag to dag inst selector for Sparc ------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
66 //
77 //===----------------------------------------------------------------------===//
88 //
9 // This file defines an instruction selector for the V8 target
9 // This file defines an instruction selector for the SPARC target.
1010 //
1111 //===----------------------------------------------------------------------===//
1212
13 #include "SparcV8.h"
14 #include "SparcV8TargetMachine.h"
13 #include "Sparc.h"
14 #include "SparcTargetMachine.h"
1515 #include "llvm/DerivedTypes.h"
1616 #include "llvm/Function.h"
1717 #include "llvm/CodeGen/MachineFrameInfo.h"
2929 // TargetLowering Implementation
3030 //===----------------------------------------------------------------------===//
3131
32 namespace V8ISD {
32 namespace SPISD {
3333 enum {
34 FIRST_NUMBER = ISD::BUILTIN_OP_END+V8::INSTRUCTION_LIST_END,
34 FIRST_NUMBER = ISD::BUILTIN_OP_END+SP::INSTRUCTION_LIST_END,
3535 CMPICC, // Compare two GPR operands, set icc.
3636 CMPFCC, // Compare two FP operands, set fcc.
3737 BRICC, // Branch to dest on icc condition
4444 FTOI, // FP to Int within a FP register.
4545 ITOF, // Int to FP within a FP register.
4646
47 CALL, // A V8 call instruction.
47 CALL, // A call instruction.
4848 RET_FLAG, // Return with a flag operand.
4949 };
5050 }
5151
5252 /// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
5353 /// condition.
54 static V8CC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
54 static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
5555 switch (CC) {
5656 default: assert(0 && "Unknown integer condition code!");
57 case ISD::SETEQ: return V8CC::ICC_E;
58 case ISD::SETNE: return V8CC::ICC_NE;
59 case ISD::SETLT: return V8CC::ICC_L;
60 case ISD::SETGT: return V8CC::ICC_G;
61 case ISD::SETLE: return V8CC::ICC_LE;
62 case ISD::SETGE: return V8CC::ICC_GE;
63 case ISD::SETULT: return V8CC::ICC_CS;
64 case ISD::SETULE: return V8CC::ICC_LEU;
65 case ISD::SETUGT: return V8CC::ICC_GU;
66 case ISD::SETUGE: return V8CC::ICC_CC;
57 case ISD::SETEQ: return SPCC::ICC_E;
58 case ISD::SETNE: return SPCC::ICC_NE;
59 case ISD::SETLT: return SPCC::ICC_L;
60 case ISD::SETGT: return SPCC::ICC_G;
61 case ISD::SETLE: return SPCC::ICC_LE;
62 case ISD::SETGE: return SPCC::ICC_GE;
63 case ISD::SETULT: return SPCC::ICC_CS;
64 case ISD::SETULE: return SPCC::ICC_LEU;
65 case ISD::SETUGT: return SPCC::ICC_GU;
66 case ISD::SETUGE: return SPCC::ICC_CC;
6767 }
6868 }
6969
7070 /// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
7171 /// FCC condition.
72 static V8CC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
72 static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
7373 switch (CC) {
7474 default: assert(0 && "Unknown fp condition code!");
75 case ISD::SETEQ: return V8CC::FCC_E;
76 case ISD::SETNE: return V8CC::FCC_NE;
77 case ISD::SETLT: return V8CC::FCC_L;
78 case ISD::SETGT: return V8CC::FCC_G;
79 case ISD::SETLE: return V8CC::FCC_LE;
80 case ISD::SETGE: return V8CC::FCC_GE;
81 case ISD::SETULT: return V8CC::FCC_UL;
82 case ISD::SETULE: return V8CC::FCC_ULE;
83 case ISD::SETUGT: return V8CC::FCC_UG;
84 case ISD::SETUGE: return V8CC::FCC_UGE;
85 case ISD::SETUO: return V8CC::FCC_U;
86 case ISD::SETO: return V8CC::FCC_O;
87 case ISD::SETONE: return V8CC::FCC_LG;
88 case ISD::SETUEQ: return V8CC::FCC_UE;
75 case ISD::SETEQ: return SPCC::FCC_E;
76 case ISD::SETNE: return SPCC::FCC_NE;
77 case ISD::SETLT: return SPCC::FCC_L;
78 case ISD::SETGT: return SPCC::FCC_G;
79 case ISD::SETLE: return SPCC::FCC_LE;
80 case ISD::SETGE: return SPCC::FCC_GE;
81 case ISD::SETULT: return SPCC::FCC_UL;
82 case ISD::SETULE: return SPCC::FCC_ULE;
83 case ISD::SETUGT: return SPCC::FCC_UG;
84 case ISD::SETUGE: return SPCC::FCC_UGE;
85 case ISD::SETUO: return SPCC::FCC_U;
86 case ISD::SETO: return SPCC::FCC_O;
87 case ISD::SETONE: return SPCC::FCC_LG;
88 case ISD::SETUEQ: return SPCC::FCC_UE;
8989 }
9090 }
9191
9292 namespace {
93 class SparcV8TargetLowering : public TargetLowering {
93 class SparcTargetLowering : public TargetLowering {
9494 int VarArgsFrameOffset; // Frame offset to start of varargs area.
9595 public:
96 SparcV8TargetLowering(TargetMachine &TM);
96 SparcTargetLowering(TargetMachine &TM);
9797 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
9898
9999 /// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
119119 };
120120 }
121121
122 SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
122 SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
123123 : TargetLowering(TM) {
124124
125125 // Set up the register classes.
126 addRegisterClass(MVT::i32, V8::IntRegsRegisterClass);
127 addRegisterClass(MVT::f32, V8::FPRegsRegisterClass);
128 addRegisterClass(MVT::f64, V8::DFPRegsRegisterClass);
126 addRegisterClass(MVT::i32, SP::IntRegsRegisterClass);
127 addRegisterClass(MVT::f32, SP::FPRegsRegisterClass);
128 addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass);
129129
130130 // Custom legalize GlobalAddress nodes into LO/HI parts.
131131 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
174174 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
175175 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
176176
177 // V8 has no intrinsics for these particular operations.
177 // SPARC has no intrinsics for these particular operations.
178178 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
179179 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
180180 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
217217 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
218218 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
219219
220 setStackPointerRegisterToSaveRestore(V8::O6);
221
222 if (TM.getSubtarget().isV9()) {
220 setStackPointerRegisterToSaveRestore(SP::O6);
221
222 if (TM.getSubtarget().isV9()) {
223223 setOperationAction(ISD::CTPOP, MVT::i32, Legal);
224224 }
225225
226226 computeRegisterProperties();
227227 }
228228
229 const char *SparcV8TargetLowering::getTargetNodeName(unsigned Opcode) const {
229 const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
230230 switch (Opcode) {
231231 default: return 0;
232 case V8ISD::CMPICC: return "V8ISD::CMPICC";
233 case V8ISD::CMPFCC: return "V8ISD::CMPFCC";
234 case V8ISD::BRICC: return "V8ISD::BRICC";
235 case V8ISD::BRFCC: return "V8ISD::BRFCC";
236 case V8ISD::SELECT_ICC: return "V8ISD::SELECT_ICC";
237 case V8ISD::SELECT_FCC: return "V8ISD::SELECT_FCC";
238 case V8ISD::Hi: return "V8ISD::Hi";
239 case V8ISD::Lo: return "V8ISD::Lo";
240 case V8ISD::FTOI: return "V8ISD::FTOI";
241 case V8ISD::ITOF: return "V8ISD::ITOF";
242 case V8ISD::CALL: return "V8ISD::CALL";
243 case V8ISD::RET_FLAG: return "V8ISD::RET_FLAG";
232 case SPISD::CMPICC: return "SPISD::CMPICC";
233 case SPISD::CMPFCC: return "SPISD::CMPFCC";
234 case SPISD::BRICC: return "SPISD::BRICC";
235 case SPISD::BRFCC: return "SPISD::BRFCC";
236 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC";
237 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC";
238 case SPISD::Hi: return "SPISD::Hi";
239 case SPISD::Lo: return "SPISD::Lo";
240 case SPISD::FTOI: return "SPISD::FTOI";
241 case SPISD::ITOF: return "SPISD::ITOF";
242 case SPISD::CALL: return "SPISD::CALL";
243 case SPISD::RET_FLAG: return "SPISD::RET_FLAG";
244244 }
245245 }
246246
247247 /// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
248248 /// be zero. Op is expected to be a target specific node. Used by DAG
249249 /// combiner.
250 bool SparcV8TargetLowering::
250 bool SparcTargetLowering::
251251 isMaskedValueZeroForTargetNode(const SDOperand &Op, uint64_t Mask) const {
252252 switch (Op.getOpcode()) {
253253 default: return false;
254 case V8ISD::SELECT_ICC:
255 case V8ISD::SELECT_FCC:
254 case SPISD::SELECT_ICC:
255 case SPISD::SELECT_FCC:
256256 assert(MVT::isInteger(Op.getValueType()) && "Not an integer select!");
257257 // These operations are masked zero if both the left and the right are zero.
258258 return MaskedValueIsZero(Op.getOperand(0), Mask) &&
265265 /// either one or two GPRs, including FP values. TODO: we should pass FP values
266266 /// in FP registers for fastcc functions.
267267 std::vector
268 SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
268 SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
269269 MachineFunction &MF = DAG.getMachineFunction();
270270 SSARegMap *RegMap = MF.getSSARegMap();
271271 std::vector ArgValues;
272272
273273 static const unsigned ArgRegs[] = {
274 V8::I0, V8::I1, V8::I2, V8::I3, V8::I4, V8::I5
274 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
275275 };
276276
277277 const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6;
293293 if (CurArgReg < ArgRegEnd) ++CurArgReg;
294294 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
295295 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
296 unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
296 unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
297297 MF.addLiveIn(*CurArgReg++, VReg);
298298 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
299299 if (ObjectVT != MVT::i32) {
333333 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
334334 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
335335 // FP value is passed in an integer register.
336 unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
336 unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
337337 MF.addLiveIn(*CurArgReg++, VReg);
338338 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
339339
368368 } else {
369369 SDOperand HiVal;
370370 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
371 unsigned VRegHi = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
371 unsigned VRegHi = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
372372 MF.addLiveIn(*CurArgReg++, VRegHi);
373373 HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32);
374374 } else {
379379
380380 SDOperand LoVal;
381381 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
382 unsigned VRegLo = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
382 unsigned VRegLo = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
383383 MF.addLiveIn(*CurArgReg++, VRegLo);
384384 LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32);
385385 } else {
409409 VarArgsFrameOffset = ArgOffset;
410410
411411 for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
412 unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
412 unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
413413 MF.addLiveIn(*CurArgReg, VReg);
414414 SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
415415
433433 case MVT::i8:
434434 case MVT::i16:
435435 case MVT::i32:
436 MF.addLiveOut(V8::I0);
436 MF.addLiveOut(SP::I0);
437437 break;
438438 case MVT::i64:
439 MF.addLiveOut(V8::I0);
440 MF.addLiveOut(V8::I1);
439 MF.addLiveOut(SP::I0);
440 MF.addLiveOut(SP::I1);
441441 break;
442442 case MVT::f32:
443 MF.addLiveOut(V8::F0);
443 MF.addLiveOut(SP::F0);
444444 break;
445445 case MVT::f64:
446 MF.addLiveOut(V8::D0);
446 MF.addLiveOut(SP::D0);
447447 break;
448448 }
449449
451451 }
452452
453453 std::pair
454 SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
455 bool isVarArg, unsigned CC,
456 bool isTailCall, SDOperand Callee,
457 ArgListTy &Args, SelectionDAG &DAG) {
454 SparcTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
455 bool isVarArg, unsigned CC,
456 bool isTailCall, SDOperand Callee,
457 ArgListTy &Args, SelectionDAG &DAG) {
458458 MachineFunction &MF = DAG.getMachineFunction();
459459 // Count the size of the outgoing arguments.
460460 unsigned ArgsSize = 0;
564564
565565 if (ValToStore.Val) {
566566 if (!StackPtr.Val) {
567 StackPtr = DAG.getRegister(V8::O6, MVT::i32);
567 StackPtr = DAG.getRegister(SP::O6, MVT::i32);
568568 NullSV = DAG.getSrcValue(NULL);
569569 }
570570 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
580580 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
581581
582582 static const unsigned ArgRegs[] = {
583 V8::O0, V8::O1, V8::O2, V8::O3, V8::O4, V8::O5
583 SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5
584584 };
585585
586586 // Build a sequence of copy-to-reg nodes chained together with token chain
604604 Ops.push_back(Callee);
605605 if (InFlag.Val)
606606 Ops.push_back(InFlag);
607 Chain = DAG.getNode(V8ISD::CALL, NodeTys, Ops);
607 Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops);
608608 InFlag = Chain.getValue(1);
609609
610610 MVT::ValueType RetTyVT = getValueType(RetTy);
615615 case MVT::i1:
616616 case MVT::i8:
617617 case MVT::i16:
618 RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag);
618 RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag);
619619 Chain = RetVal.getValue(1);
620620
621621 // Add a note to keep track of whether it is sign or zero extended.
624624 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
625625 break;
626626 case MVT::i32:
627 RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag);
627 RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag);
628628 Chain = RetVal.getValue(1);
629629 break;
630630 case MVT::f32:
631 RetVal = DAG.getCopyFromReg(Chain, V8::F0, MVT::f32, InFlag);
631 RetVal = DAG.getCopyFromReg(Chain, SP::F0, MVT::f32, InFlag);
632632 Chain = RetVal.getValue(1);
633633 break;
634634 case MVT::f64:
635 RetVal = DAG.getCopyFromReg(Chain, V8::D0, MVT::f64, InFlag);
635 RetVal = DAG.getCopyFromReg(Chain, SP::D0, MVT::f64, InFlag);
636636 Chain = RetVal.getValue(1);
637637 break;
638638 case MVT::i64:
639 SDOperand Lo = DAG.getCopyFromReg(Chain, V8::O1, MVT::i32, InFlag);
640 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), V8::O0, MVT::i32,
639 SDOperand Lo = DAG.getCopyFromReg(Chain, SP::O1, MVT::i32, InFlag);
640 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), SP::O0, MVT::i32,
641641 Lo.getValue(2));
642642 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
643643 Chain = Hi.getValue(1);
651651 return std::make_pair(RetVal, Chain);
652652 }
653653
654 std::pair SparcV8TargetLowering::
654 std::pair SparcTargetLowering::
655655 LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
656656 SelectionDAG &DAG) {
657657 assert(0 && "Unimp");
658658 abort();
659659 }
660660
661 // Look at LHS/RHS/CC and see if they are a lowered V8 setcc instruction. If so
662 // set LHS/RHS and V8CC to the LHS/RHS of the setcc and V8CC to the condition.
661 // Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so
662 // set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
663663 static void LookThroughSetCC(SDOperand &LHS, SDOperand &RHS,
664 ISD::CondCode CC, unsigned &V8CC) {
664 ISD::CondCode CC, unsigned &SPCC) {
665665 if (isa(RHS) && cast(RHS)->getValue() == 0 &&
666666 CC == ISD::SETNE &&
667 ((LHS.getOpcode() == V8ISD::SELECT_ICC &&
668 LHS.getOperand(3).getOpcode() == V8ISD::CMPICC) ||
669 (LHS.getOpcode() == V8ISD::SELECT_FCC &&
670 LHS.getOperand(3).getOpcode() == V8ISD::CMPFCC)) &&
667 ((LHS.getOpcode() == SPISD::SELECT_ICC &&
668 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) ||
669 (LHS.getOpcode() == SPISD::SELECT_FCC &&
670 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) &&
671671 isa(LHS.getOperand(0)) &&
672672 isa(LHS.getOperand(1)) &&
673673 cast(LHS.getOperand(0))->getValue() == 1 &&
674674 cast(LHS.getOperand(1))->getValue() == 0) {
675675 SDOperand CMPCC = LHS.getOperand(3);
676 V8CC = cast(LHS.getOperand(2))->getValue();
676 SPCC = cast(LHS.getOperand(2))->getValue();
677677 LHS = CMPCC.getOperand(0);
678678 RHS = CMPCC.getOperand(1);
679679 }
680680 }
681681
682682
683 SDOperand SparcV8TargetLowering::
683 SDOperand SparcTargetLowering::
684684 LowerOperation(SDOperand Op, SelectionDAG &DAG) {
685685 switch (Op.getOpcode()) {
686686 default: assert(0 && "Should not custom lower this!");
687687 case ISD::GlobalAddress: {
688688 GlobalValue *GV = cast(Op)->getGlobal();
689689 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
690 SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, GA);
691 SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, GA);
690 SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, GA);
691 SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, GA);
692692 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
693693 }
694694 case ISD::ConstantPool: {
695695 Constant *C = cast(Op)->get();
696696 SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32,
697697 cast(Op)->getAlignment());
698 SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, CP);
699 SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, CP);
698 SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, CP);
699 SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, CP);
700700 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
701701 }
702702 case ISD::FP_TO_SINT:
703703 // Convert the fp value to integer in an FP register.
704704 assert(Op.getValueType() == MVT::i32);
705 Op = DAG.getNode(V8ISD::FTOI, MVT::f32, Op.getOperand(0));
705 Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0));
706706 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
707707 case ISD::SINT_TO_FP: {
708708 assert(Op.getOperand(0).getValueType() == MVT::i32);
709709 SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
710710 // Convert the int value to FP in an FP register.
711 return DAG.getNode(V8ISD::ITOF, Op.getValueType(), Tmp);
711 return DAG.getNode(SPISD::ITOF, Op.getValueType(), Tmp);
712712 }
713713 case ISD::BR_CC: {
714714 SDOperand Chain = Op.getOperand(0);
716716 SDOperand LHS = Op.getOperand(2);
717717 SDOperand RHS = Op.getOperand(3);
718718 SDOperand Dest = Op.getOperand(4);
719 unsigned Opc, V8CC = ~0U;
719 unsigned Opc, SPCC = ~0U;
720720
721721 // If this is a br_cc of a "setcc", and if the setcc got lowered into
722722 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
723 LookThroughSetCC(LHS, RHS, CC, V8CC);
723 LookThroughSetCC(LHS, RHS, CC, SPCC);
724724
725725 // Get the condition flag.
726726 SDOperand CompareFlag;
731731 std::vector Ops;
732732 Ops.push_back(LHS);
733733 Ops.push_back(RHS);
734 CompareFlag = DAG.getNode(V8ISD::CMPICC, VTs, Ops).getValue(1);
735 if (V8CC == ~0U) V8CC = IntCondCCodeToICC(CC);
736 Opc = V8ISD::BRICC;
734 CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops).getValue(1);
735 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
736 Opc = SPISD::BRICC;
737737 } else {
738 CompareFlag = DAG.getNode(V8ISD::CMPFCC, MVT::Flag, LHS, RHS);
739 if (V8CC == ~0U) V8CC = FPCondCCodeToFCC(CC);
740 Opc = V8ISD::BRFCC;
738 CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS);
739 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
740 Opc = SPISD::BRFCC;
741741 }
742742 return DAG.getNode(Opc, MVT::Other, Chain, Dest,
743 DAG.getConstant(V8CC, MVT::i32), CompareFlag);
743 DAG.getConstant(SPCC, MVT::i32), CompareFlag);
744744 }
745745 case ISD::SELECT_CC: {
746746 SDOperand LHS = Op.getOperand(0);
748748 ISD::CondCode CC = cast(Op.getOperand(4))->get();
749749 SDOperand TrueVal = Op.getOperand(2);
750750 SDOperand FalseVal = Op.getOperand(3);
751 unsigned Opc, V8CC = ~0U;
751 unsigned Opc, SPCC = ~0U;
752752
753753 // If this is a select_cc of a "setcc", and if the setcc got lowered into
754754 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
755 LookThroughSetCC(LHS, RHS, CC, V8CC);
755 LookThroughSetCC(LHS, RHS, CC, SPCC);
756756
757757 SDOperand CompareFlag;
758758 if (LHS.getValueType() == MVT::i32) {
762762 std::vector Ops;
763763 Ops.push_back(LHS);
764764 Ops.push_back(RHS);
765 CompareFlag = DAG.getNode(V8ISD::CMPICC, VTs, Ops).getValue(1);
766 Opc = V8ISD::SELECT_ICC;
767 if (V8CC == ~0U) V8CC = IntCondCCodeToICC(CC);
765 CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops).getValue(1);
766 Opc = SPISD::SELECT_ICC;
767 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
768768 } else {
769 CompareFlag = DAG.getNode(V8ISD::CMPFCC, MVT::Flag, LHS, RHS);
770 Opc = V8ISD::SELECT_FCC;
771 if (V8CC == ~0U) V8CC = FPCondCCodeToFCC(CC);
769 CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS);
770 Opc = SPISD::SELECT_FCC;
771 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
772772 }
773773 return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal,
774 DAG.getConstant(V8CC, MVT::i32), CompareFlag);
774 DAG.getConstant(SPCC, MVT::i32), CompareFlag);
775775 }
776776 case ISD::VASTART: {
777777 // vastart just stores the address of the VarArgsFrameIndex slot into the
778778 // memory location argument.
779779 SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32,
780 DAG.getRegister(V8::I6, MVT::i32),
780 DAG.getRegister(SP::I6, MVT::i32),
781781 DAG.getConstant(VarArgsFrameOffset, MVT::i32));
782782 return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), Offset,
783783 Op.getOperand(1), Op.getOperand(2));
826826 unsigned ArgReg;
827827 switch(Op.getOperand(1).getValueType()) {
828828 default: assert(0 && "Unknown type to return!");
829 case MVT::i32: ArgReg = V8::I0; break;
830 case MVT::f32: ArgReg = V8::F0; break;
831 case MVT::f64: ArgReg = V8::D0; break;
829 case MVT::i32: ArgReg = SP::I0; break;
830 case MVT::f32: ArgReg = SP::F0; break;
831 case MVT::f64: ArgReg = SP::D0; break;
832832 }
833833 Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1),
834834 SDOperand());
835835 break;
836836 }
837837 case 3:
838 Copy = DAG.getCopyToReg(Op.getOperand(0), V8::I0, Op.getOperand(2),
838 Copy = DAG.getCopyToReg(Op.getOperand(0), SP::I0, Op.getOperand(2),
839839 SDOperand());
840 Copy = DAG.getCopyToReg(Copy, V8::I1, Op.getOperand(1), Copy.getValue(1));
841 break;
842 }
843 return DAG.getNode(V8ISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
840 Copy = DAG.getCopyToReg(Copy, SP::I1, Op.getOperand(1), Copy.getValue(1));
841 break;
842 }
843 return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
844844 }
845845 }
846846 }
847847
848848 MachineBasicBlock *
849 SparcV8TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
850 MachineBasicBlock *BB) {
849 SparcTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
850 MachineBasicBlock *BB) {
851851 unsigned BROpcode;
852852 unsigned CC;
853853 // Figure out the conditional branch opcode to use for this select_cc.
854854 switch (MI->getOpcode()) {
855855 default: assert(0 && "Unknown SELECT_CC!");
856 case V8::SELECT_CC_Int_ICC:
857 case V8::SELECT_CC_FP_ICC:
858 case V8::SELECT_CC_DFP_ICC:
859 BROpcode = V8::BCOND;
856 case SP::SELECT_CC_Int_ICC:
857 case SP::SELECT_CC_FP_ICC:
858 case SP::SELECT_CC_DFP_ICC:
859 BROpcode = SP::BCOND;
860860 break;
861 case V8::SELECT_CC_Int_FCC:
862 case V8::SELECT_CC_FP_FCC:
863 case V8::SELECT_CC_DFP_FCC:
864 BROpcode = V8::FBCOND;
861 case SP::SELECT_CC_Int_FCC:
862 case SP::SELECT_CC_FP_FCC:
863 case SP::SELECT_CC_DFP_FCC:
864 BROpcode = SP::FBCOND;
865865 break;
866866 }
867867
868 CC = (V8CC::CondCodes)MI->getOperand(3).getImmedValue();
868 CC = (SPCC::CondCodes)MI->getOperand(3).getImmedValue();
869869
870870 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
871871 // control-flow pattern. The incoming instruction knows the destination vreg
903903 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
904904 // ...
905905 BB = sinkMBB;
906 BuildMI(BB, V8::PHI, 4, MI->getOperand(0).getReg())
906 BuildMI(BB, SP::PHI, 4, MI->getOperand(0).getReg())
907907 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
908908 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
909909
916916 //===----------------------------------------------------------------------===//
917917
918918 //===--------------------------------------------------------------------===//
919 /// SparcV8DAGToDAGISel - SPARC specific code to select Sparc V8 machine
919 /// SparcDAGToDAGISel - SPARC specific code to select SPARC machine
920920 /// instructions for SelectionDAG operations.
921921 ///
922922 namespace {
923 class SparcV8DAGToDAGISel : public SelectionDAGISel {
924 SparcV8TargetLowering V8Lowering;
923 class SparcDAGToDAGISel : public SelectionDAGISel {
924 SparcTargetLowering Lowering;
925925
926926 /// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can
927927 /// make the right decision when generating code for different targets.
928 const SparcV8Subtarget &Subtarget;
928 const SparcSubtarget &Subtarget;
929929 public:
930 SparcV8DAGToDAGISel(TargetMachine &TM)
931 : SelectionDAGISel(V8Lowering), V8Lowering(TM),
932 Subtarget(TM.getSubtarget()) {
930 SparcDAGToDAGISel(TargetMachine &TM)
931 : SelectionDAGISel(Lowering), Lowering(TM),
932 Subtarget(TM.getSubtarget()) {
933933 }
934934
935935 SDOperand Select(SDOperand Op);
943943 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
944944
945945 virtual const char *getPassName() const {
946 return "SparcV8 DAG->DAG Pattern Instruction Selection";
946 return "SPARC DAG->DAG Pattern Instruction Selection";
947947 }
948948
949949 // Include the pieces autogenerated from the target description.
950 #include "SparcV8GenDAGISel.inc"
950 #include "SparcGenDAGISel.inc"
951951 };
952952 } // end anonymous namespace
953953
954954 /// InstructionSelectBasicBlock - This callback is invoked by
955955 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
956 void SparcV8DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
956 void SparcDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
957957 DEBUG(BB->dump());
958958
959959 // Select target instructions for the DAG.
965965 ScheduleAndEmitDAG(DAG);
966966 }
967967
968 bool SparcV8DAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base,
968 bool SparcDAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base,
969969 SDOperand &Offset) {
970970 if (FrameIndexSDNode *FIN = dyn_cast(Addr)) {
971971 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
987987 return true;
988988 }
989989 }
990 if (Addr.getOperand(0).getOpcode() == V8ISD::Lo) {
990 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) {
991991 Base = Select(Addr.getOperand(1));
992992 Offset = Addr.getOperand(0).getOperand(0);
993993 return true;
994994 }
995 if (Addr.getOperand(1).getOpcode() == V8ISD::Lo) {
995 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) {
996996 Base = Select(Addr.getOperand(0));
997997 Offset = Addr.getOperand(1).getOperand(0);
998998 return true;
10031003 return true;
10041004 }
10051005
1006 bool SparcV8DAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1,
1007 SDOperand &R2) {
1006 bool SparcDAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1,
1007 SDOperand &R2) {
10081008 if (Addr.getOpcode() == ISD::FrameIndex) return false;
10091009 if (Addr.getOpcode() == ISD::ADD) {
10101010 if (isa(Addr.getOperand(1)) &&
10111011 Predicate_simm13(Addr.getOperand(1).Val))
10121012 return false; // Let the reg+imm pattern catch this!
1013 if (Addr.getOperand(0).getOpcode() == V8ISD::Lo ||
1014 Addr.getOperand(1).getOpcode() == V8ISD::Lo)
1013 if (Addr.getOperand(0).getOpcode() == SPISD::Lo ||
1014 Addr.getOperand(1).getOpcode() == SPISD::Lo)
10151015 return false; // Let the reg+imm pattern catch this!
10161016 R1 = Select(Addr.getOperand(0));
10171017 R2 = Select(Addr.getOperand(1));
10191019 }
10201020
10211021 R1 = Select(Addr);
1022 R2 = CurDAG->getRegister(V8::G0, MVT::i32);
1022 R2 = CurDAG->getRegister(SP::G0, MVT::i32);
10231023 return true;
10241024 }
10251025
1026 SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) {
1026 SDOperand SparcDAGToDAGISel::Select(SDOperand Op) {
10271027 SDNode *N = Op.Val;
10281028 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
1029 N->getOpcode() < V8ISD::FIRST_NUMBER)
1029 N->getOpcode() < SPISD::FIRST_NUMBER)
10301030 return Op; // Already selected.
10311031 // If this has already been converted, use it.
10321032 std::map::iterator CGMI = CodeGenMap.find(Op);
10371037 case ISD::FrameIndex: {
10381038 int FI = cast(N)->getIndex();
10391039 if (N->hasOneUse())
1040 return CurDAG->SelectNodeTo(N, V8::ADDri, MVT::i32,
1040 return CurDAG->SelectNodeTo(N, SP::ADDri, MVT::i32,
10411041 CurDAG->getTargetFrameIndex(FI, MVT::i32),
10421042 CurDAG->getTargetConstant(0, MVT::i32));
10431043 return CodeGenMap[Op] =
1044 CurDAG->getTargetNode(V8::ADDri, MVT::i32,
1044 CurDAG->getTargetNode(SP::ADDri, MVT::i32,
10451045 CurDAG->getTargetFrameIndex(FI, MVT::i32),
10461046 CurDAG->getTargetConstant(0, MVT::i32));
10471047 }
10511051 SDOperand RHSL = Select(N->getOperand(2));
10521052 SDOperand RHSH = Select(N->getOperand(3));
10531053 // FIXME, handle immediate RHS.
1054 SDOperand Low = CurDAG->getTargetNode(V8::ADDCCrr, MVT::i32, MVT::Flag,
1054 SDOperand Low = CurDAG->getTargetNode(SP::ADDCCrr, MVT::i32, MVT::Flag,
10551055 LHSL, RHSL);
1056 SDOperand Hi = CurDAG->getTargetNode(V8::ADDXrr, MVT::i32, LHSH, RHSH,
1056 SDOperand Hi = CurDAG->getTargetNode(SP::ADDXrr, MVT::i32, LHSH, RHSH,
10571057 Low.getValue(1));
10581058 CodeGenMap[SDOperand(N, 0)] = Low;
10591059 CodeGenMap[SDOperand(N, 1)] = Hi;
10651065 SDOperand RHSL = Select(N->getOperand(2));
10661066 SDOperand RHSH = Select(N->getOperand(3));
10671067 // FIXME, handle immediate RHS.
1068 SDOperand Low = CurDAG->getTargetNode(V8::SUBCCrr, MVT::i32, MVT::Flag,
1068 SDOperand Low = CurDAG->getTargetNode(SP::SUBCCrr, MVT::i32, MVT::Flag,
10691069 LHSL, RHSL);
1070 SDOperand Hi = CurDAG->getTargetNode(V8::SUBXrr, MVT::i32, LHSH, RHSH,
1070 SDOperand Hi = CurDAG->getTargetNode(SP::SUBXrr, MVT::i32, LHSH, RHSH,
10711071 Low.getValue(1));
10721072 CodeGenMap[SDOperand(N, 0)] = Low;
10731073 CodeGenMap[SDOperand(N, 1)] = Hi;
10821082 // Set the Y register to the high-part.
10831083 SDOperand TopPart;
10841084 if (N->getOpcode() == ISD::SDIV) {
1085 TopPart = CurDAG->getTargetNode(V8::SRAri, MVT::i32, DivLHS,
1085 TopPart = CurDAG->getTargetNode(SP::SRAri, MVT::i32, DivLHS,
10861086 CurDAG->getTargetConstant(31, MVT::i32));
10871087 } else {
1088 TopPart = CurDAG->getRegister(V8::G0, MVT::i32);
1089 }
1090 TopPart = CurDAG->getTargetNode(V8::WRYrr, MVT::Flag, TopPart,
1091 CurDAG->getRegister(V8::G0, MVT::i32));
1088 TopPart = CurDAG->getRegister(SP::G0, MVT::i32);
1089 }
1090 TopPart = CurDAG->getTargetNode(SP::WRYrr, MVT::Flag, TopPart,
1091 CurDAG->getRegister(SP::G0, MVT::i32));
10921092
10931093 // FIXME: Handle div by immediate.
1094 unsigned Opcode = N->getOpcode() == ISD::SDIV ? V8::SDIVrr : V8::UDIVrr;
1094 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
10951095 return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart);
10961096 }
10971097 case ISD::MULHU:
10991099 // FIXME: Handle mul by immediate.
11001100 SDOperand MulLHS = Select(N->getOperand(0));
11011101 SDOperand MulRHS = Select(N->getOperand(1));
1102 unsigned Opcode = N->getOpcode() == ISD::MULHU ? V8::UMULrr : V8::SMULrr;
1102 unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
11031103 SDOperand Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag,
11041104 MulLHS, MulRHS);
11051105 // The high part is in the Y register.
1106 return CurDAG->SelectNodeTo(N, V8::RDY, MVT::i32, Mul.getValue(1));
1107 }
1108 case V8ISD::CALL:
1106 return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, Mul.getValue(1));
1107 }
1108 case SPISD::CALL:
11091109 // FIXME: This is a workaround for a bug in tblgen.
11101110 { // Pattern #47: (call:Flag (tglobaladdr:i32):$dst, ICC:Flag)
11111111 // Emits: (CALL:void (tglobaladdr:i32):$dst)
11201120 SDOperand Result;
11211121 if (N->getNumOperands() == 3) {
11221122 InFlag = Select(N->getOperand(2));
1123 Result = CurDAG->getTargetNode(V8::CALL, MVT::Other, MVT::Flag, Tmp0,
1123 Result = CurDAG->getTargetNode(SP::CALL, MVT::Other, MVT::Flag, Tmp0,
11241124 Chain, InFlag);
11251125 } else {
1126 Result = CurDAG->getTargetNode(V8::CALL, MVT::Other, MVT::Flag, Tmp0,
1126 Result = CurDAG->getTargetNode(SP::CALL, MVT::Other, MVT::Flag, Tmp0,
11271127 Chain);
11281128 }
11291129 Chain = CodeGenMap[SDOperand(N, 0)] = Result.getValue(0);
11381138 }
11391139
11401140
1141 /// createSparcV8ISelDag - This pass converts a legalized DAG into a
1141 /// createSparcISelDag - This pass converts a legalized DAG into a
11421142 /// SPARC-specific DAG, ready for instruction scheduling.
11431143 ///
1144 FunctionPass *llvm::createSparcV8ISelDag(TargetMachine &TM) {
1145 return new SparcV8DAGToDAGISel(TM);
1146 }
1144 FunctionPass *llvm::createSparcISelDag(TargetMachine &TM) {
1145 return new SparcDAGToDAGISel(TM);
1146 }
None //===- SparcV8InstrFormats.td - SparcV8 Instr Formats ------*- tablegen -*-===//
0 //===- SparcInstrFormats.td - Sparc Instruction Formats ----*- tablegen -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
66 //
77 //===----------------------------------------------------------------------===//
88
9 class InstV8 pattern> : Instruction {
9 class InstSP pattern> : Instruction {
1010 field bits<32> Inst;
1111
12 let Namespace = "V8";
12 let Namespace = "SP";
1313
1414 bits<2> op;
1515 let Inst{31-30} = op; // Top two bits are the 'op' field
2020 }
2121
2222 //===----------------------------------------------------------------------===//
23 // Format #2 instruction classes in the SparcV8
23 // Format #2 instruction classes in the Sparc
2424 //===----------------------------------------------------------------------===//
2525
2626 // Format 2 instructions
2727 class F2 pattern>
28 : InstV8 {
28 : InstSP {
2929 bits<3> op2;
3030 bits<22> imm22;
3131 let op = 0; // op = 0
5757 }
5858
5959 //===----------------------------------------------------------------------===//
60 // Format #3 instruction classes in the SparcV8
60 // Format #3 instruction classes in the Sparc
6161 //===----------------------------------------------------------------------===//
6262
6363 class F3 pattern>
64 : InstV8 {
64 : InstSP {
6565 bits<5> rd;
6666 bits<6> op3;
6767 bits<5> rs1;
7575 //
7676 class F3_1 opVal, bits<6> op3val, dag ops,
7777 string asmstr, list pattern> : F3 {
78 bits<8> asi = 0; // asi not currently used in SparcV8
78 bits<8> asi = 0; // asi not currently used
7979 bits<5> rs2;
8080
8181 let op = opVal;
None //===- SparcV8InstrInfo.cpp - SparcV8 Instruction Information ---*- C++ -*-===//
0 //===- SparcInstrInfo.cpp - Sparc Instruction Information -------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
66 //
77 //===----------------------------------------------------------------------===//
88 //
9 // This file contains the SparcV8 implementation of the TargetInstrInfo class.
9 // This file contains the Sparc implementation of the TargetInstrInfo class.
1010 //
1111 //===----------------------------------------------------------------------===//
1212
13 #include "SparcV8InstrInfo.h"
14 #include "SparcV8.h"
13 #include "SparcInstrInfo.h"
14 #include "Sparc.h"
1515 #include "llvm/CodeGen/MachineInstrBuilder.h"
16 #include "SparcV8GenInstrInfo.inc"
16 #include "SparcGenInstrInfo.inc"
1717 using namespace llvm;
1818
19 SparcV8InstrInfo::SparcV8InstrInfo(SparcV8Subtarget &ST)
20 : TargetInstrInfo(SparcV8Insts, sizeof(SparcV8Insts)/sizeof(SparcV8Insts[0])),
19 SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST)
20 : TargetInstrInfo(SparcInsts, sizeof(SparcInsts)/sizeof(SparcInsts[0])),
2121 RI(ST) {
2222 }
2323
2828 /// Return true if the instruction is a register to register move and
2929 /// leave the source and dest operands in the passed parameters.
3030 ///
31 bool SparcV8InstrInfo::isMoveInstr(const MachineInstr &MI,
32 unsigned &SrcReg, unsigned &DstReg) const {
31 bool SparcInstrInfo::isMoveInstr(const MachineInstr &MI,
32 unsigned &SrcReg, unsigned &DstReg) const {
3333 // We look for 3 kinds of patterns here:
3434 // or with G0 or 0
3535 // add with G0 or 0
3636 // fmovs or FpMOVD (pseudo double move).
37 if (MI.getOpcode() == V8::ORrr || MI.getOpcode() == V8::ADDrr) {
38 if (MI.getOperand(1).getReg() == V8::G0) {
37 if (MI.getOpcode() == SP::ORrr || MI.getOpcode() == SP::ADDrr) {
38 if (MI.getOperand(1).getReg() == SP::G0) {
3939 DstReg = MI.getOperand(0).getReg();
4040 SrcReg = MI.getOperand(2).getReg();
4141 return true;
42 } else if (MI.getOperand(2).getReg() == V8::G0) {
42 } else if (MI.getOperand(2).getReg() == SP::G0) {
4343 DstReg = MI.getOperand(0).getReg();
4444 SrcReg = MI.getOperand(1).getReg();
4545 return true;
4646 }
47 } else if ((MI.getOpcode() == V8::ORri || MI.getOpcode() == V8::ADDri) &&
47 } else if ((MI.getOpcode() == SP::ORri || MI.getOpcode() == SP::ADDri) &&
4848 isZeroImm(MI.getOperand(2)) && MI.getOperand(1).isRegister()) {
4949 DstReg = MI.getOperand(0).getReg();
5050 SrcReg = MI.getOperand(1).getReg();
5151 return true;
52 } else if (MI.getOpcode() == V8::FMOVS || MI.getOpcode() == V8::FpMOVD ||
53 MI.getOpcode() == V8::FMOVD) {
52 } else if (MI.getOpcode() == SP::FMOVS || MI.getOpcode() == SP::FpMOVD ||
53 MI.getOpcode() == SP::FMOVD) {
5454 SrcReg = MI.getOperand(1).getReg();
5555 DstReg = MI.getOperand(0).getReg();
5656 return true;
6363 /// the destination along with the FrameIndex of the loaded stack slot. If
6464 /// not, return 0. This predicate must return 0 if the instruction has
6565 /// any side effects other than loading from the stack slot.
66 unsigned SparcV8InstrInfo::isLoadFromStackSlot(MachineInstr *MI,
67 int &FrameIndex) const {
68 if (MI->getOpcode() == V8::LDri ||
69 MI->getOpcode() == V8::LDFri ||
70 MI->getOpcode() == V8::LDDFri) {
66 unsigned SparcInstrInfo::isLoadFromStackSlot(MachineInstr *MI,
67 int &FrameIndex) const {
68 if (MI->getOpcode() == SP::LDri ||
69 MI->getOpcode() == SP::LDFri ||
70 MI->getOpcode() == SP::LDDFri) {
7171 if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() &&
7272 MI->getOperand(2).getImmedValue() == 0) {
7373 FrameIndex = MI->getOperand(1).getFrameIndex();
8282 /// the source reg along with the FrameIndex of the loaded stack slot. If
8383 /// not, return 0. This predicate must return 0 if the instruction has
8484 /// any side effects other than storing to the stack slot.
85 unsigned SparcV8InstrInfo::isStoreToStackSlot(MachineInstr *MI,
86 int &FrameIndex) const {
87 if (MI->getOpcode() == V8::STri ||
88 MI->getOpcode() == V8::STFri ||
89 MI->getOpcode() == V8::STDFri) {
85 unsigned SparcInstrInfo::isStoreToStackSlot(MachineInstr *MI,
86 int &FrameIndex) const {
87 if (MI->getOpcode() == SP::STri ||
88 MI->getOpcode() == SP::STFri ||
89 MI->getOpcode() == SP::STDFri) {
9090 if (MI->getOperand(0).isFrameIndex() && MI->getOperand(1).isImmediate() &&
9191 MI->getOperand(1).getImmedValue() == 0) {
9292 FrameIndex = MI->getOperand(0).getFrameIndex();
None //===- SparcV8InstrInfo.h - SparcV8 Instruction Information -----*- C++ -*-===//
0 //===- SparcInstrInfo.h - Sparc Instruction Information ---------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
66 //
77 //===----------------------------------------------------------------------===//
88 //
9 // This file contains the SparcV8 implementation of the TargetInstrInfo class.
9 // This file contains the Sparc implementation of the TargetInstrInfo class.
1010 //
1111 //===----------------------------------------------------------------------===//
1212
13 #ifndef SPARCV8INSTRUCTIONINFO_H
14 #define SPARCV8INSTRUCTIONINFO_H
13 #ifndef SPARCINSTRUCTIONINFO_H
14 #define SPARCINSTRUCTIONINFO_H
1515
1616 #include "llvm/Target/TargetInstrInfo.h"
17 #include "SparcV8RegisterInfo.h"
17 #include "SparcRegisterInfo.h"
1818
1919 namespace llvm {
2020
21 /// V8II - This namespace holds all of the target specific flags that
21 /// SPII - This namespace holds all of the target specific flags that
2222 /// instruction info tracks.
2323 ///
24 namespace V8II {
24 namespace SPII {
2525 enum {
2626 Pseudo = (1<<0),
2727 Load = (1<<1),
3030 };
3131 };
3232
33 class SparcV8InstrInfo : public TargetInstrInfo {
34 const SparcV8RegisterInfo RI;
33 class SparcInstrInfo : public TargetInstrInfo {
34 const SparcRegisterInfo RI;
3535 public:
36 SparcV8InstrInfo(SparcV8Subtarget &ST);
36 SparcInstrInfo(SparcSubtarget &ST);
3737
3838 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
3939 /// such, whenever a client has an instance of instruction info, it should
None //===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===//
0 //===- SparcInstrInfo.td - Target Description for Sparc Target ------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
66 //
77 //===----------------------------------------------------------------------===//
88 //
9 // This file describes the SparcV8 instructions in TableGen format.
9 // This file describes the Sparc instructions in TableGen format.
1010 //
1111 //===----------------------------------------------------------------------===//
1212
1414 // Instruction format superclass
1515 //===----------------------------------------------------------------------===//
1616
17 include "SparcV8InstrFormats.td"
17 include "SparcInstrFormats.td"
1818
1919 //===----------------------------------------------------------------------===//
2020 // Feature predicates.
8686 def calltarget : Operand;
8787
8888 // Operand for printing out a condition code.
89 let PrintMethod = "printV8CCOperand" in
90 def V8CC : Operand;
91
92 def SDTV8cmpfcc :
89 let PrintMethod = "printCCOperand" in
90 def CCOp : Operand;
91
92 def SDTSPcmpfcc :
9393 SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisFP<1>, SDTCisSameAs<1, 2>]>;
94 def SDTV8brcc :
94 def SDTSPbrcc :
9595 SDTypeProfile<0, 3, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>,
9696 SDTCisVT<2, FlagVT>]>;
97 def SDTV8selectcc :
97 def SDTSPselectcc :
9898 SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
9999 SDTCisVT<3, i32>, SDTCisVT<4, FlagVT>]>;
100 def SDTV8FTOI :
100 def SDTSPFTOI :
101101 SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
102 def SDTV8ITOF :
102 def SDTSPITOF :
103103 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
104104
105 def V8cmpicc : SDNode<"V8ISD::CMPICC", SDTIntBinOp, [SDNPOutFlag]>;
106 def V8cmpfcc : SDNode<"V8ISD::CMPFCC", SDTV8cmpfcc, [SDNPOutFlag]>;
107 def V8bricc : SDNode<"V8ISD::BRICC", SDTV8brcc, [SDNPHasChain]>;
108 def V8brfcc : SDNode<"V8ISD::BRFCC", SDTV8brcc, [SDNPHasChain]>;
109
110 def V8hi : SDNode<"V8ISD::Hi", SDTIntUnaryOp>;
111 def V8lo : SDNode<"V8ISD::Lo", SDTIntUnaryOp>;
112
113 def V8ftoi : SDNode<"V8ISD::FTOI", SDTV8FTOI>;
114 def V8itof : SDNode<"V8ISD::ITOF", SDTV8ITOF>;
115
116 def V8selecticc : SDNode<"V8ISD::SELECT_ICC", SDTV8selectcc>;
117 def V8selectfcc : SDNode<"V8ISD::SELECT_FCC", SDTV8selectcc>;
105 def SPcmpicc : SDNode<"SPISD::CMPICC", SDTIntBinOp, [SDNPOutFlag]>;
106 def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutFlag]>;
107 def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain]>;
108 def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain]>;
109
110 def SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>;
111 def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>;
112
113 def SPftoi : SDNode<"SPISD::FTOI", SDTSPFTOI>;
114 def SPitof : SDNode<"SPISD::ITOF", SDTSPITOF>;
115
116 def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc>;
117 def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc>;
118118
119119 // These are target-independent nodes, but have target-specific formats.
120 def SDT_V8CallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
121 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_V8CallSeq, [SDNPHasChain]>;
122 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_V8CallSeq, [SDNPHasChain]>;
123
124 def SDT_V8Call : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
125 def call : SDNode<"V8ISD::CALL", SDT_V8Call,
120 def SDT_SPCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
121 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeq, [SDNPHasChain]>;
122 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeq, [SDNPHasChain]>;
123
124 def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
125 def call : SDNode<"SPISD::CALL", SDT_SPCall,
126126 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
127127
128 def SDT_V8RetFlag : SDTypeProfile<0, 0, []>;
129 def retflag : SDNode<"V8ISD::RET_FLAG", SDT_V8RetFlag,
128 def SDT_SPRetFlag : SDTypeProfile<0, 0, []>;
129 def retflag : SDNode<"SPISD::RET_FLAG", SDT_SPRetFlag,
130130 [SDNPHasChain, SDNPOptInFlag]>;
131131
132132 //===----------------------------------------------------------------------===//
133133 // SPARC Flag Conditions
134134 //===----------------------------------------------------------------------===//
135135
136 // Note that these values must be kept in sync with the V8CC::CondCode enum
136 // Note that these values must be kept in sync with the CCOp::CondCode enum
137137 // values.
138138 class ICC_VAL : PatLeaf<(i32 N)>;
139139 def ICC_NE : ICC_VAL< 9>; // Not Equal
174174
175175 // Pseudo instructions.
176176 class Pseudo pattern>
177 : InstV8;
177 : InstSP;
178178
179179 def ADJCALLSTACKDOWN : Pseudo<(ops i32imm:$amt),
180180 "!ADJCALLSTACKDOWN $amt",
192192
193193 // FpMOVD/FpNEGD/FpABSD - These are lowered to single-precision ops by the
194194 // fpmover pass.
195 let Predicates = [HasNoV9] in { // Only emit these in V8 mode.
195 let Predicates = [HasNoV9] in { // Only emit these in SP mode.
196196 def FpMOVD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src),
197197 "!FpMOVD $src, $dst", []>;
198198 def FpNEGD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src),
211211 def SELECT_CC_Int_ICC
212212 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond),
213213 "; SELECT_CC_Int_ICC PSEUDO!",
214 [(set IntRegs:$dst, (V8selecticc IntRegs:$T, IntRegs:$F,
214 [(set IntRegs:$dst, (SPselecticc IntRegs:$T, IntRegs:$F,
215215 imm:$Cond, ICC))]>;
216216 def SELECT_CC_Int_FCC
217217 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond),
218218 "; SELECT_CC_Int_FCC PSEUDO!",
219 [(set IntRegs:$dst, (V8selectfcc IntRegs:$T, IntRegs:$F,
219 [(set IntRegs:$dst, (SPselectfcc IntRegs:$T, IntRegs:$F,
220220 imm:$Cond, FCC))]>;
221221 def SELECT_CC_FP_ICC
222222 : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, i32imm:$Cond),
223223 "; SELECT_CC_FP_ICC PSEUDO!",
224 [(set FPRegs:$dst, (V8selecticc FPRegs:$T, FPRegs:$F,
224 [(set FPRegs:$dst, (SPselecticc FPRegs:$T, FPRegs:$F,
225225 imm:$Cond, ICC))]>;
226226 def SELECT_CC_FP_FCC
227227 : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, i32imm:$Cond),
228228 "; SELECT_CC_FP_FCC PSEUDO!",
229 [(set FPRegs:$dst, (V8selectfcc FPRegs:$T, FPRegs:$F,
229 [(set FPRegs:$dst, (SPselectfcc FPRegs:$T, FPRegs:$F,
230230 imm:$Cond, FCC))]>;
231231 def SELECT_CC_DFP_ICC
232232 : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
233233 "; SELECT_CC_DFP_ICC PSEUDO!",
234 [(set DFPRegs:$dst, (V8selecticc DFPRegs:$T, DFPRegs:$F,
234 [(set DFPRegs:$dst, (SPselecticc DFPRegs:$T, DFPRegs:$F,
235235 imm:$Cond, ICC))]>;
236236 def SELECT_CC_DFP_FCC
237237 : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
238238 "; SELECT_CC_DFP_FCC PSEUDO!",
239 [(set DFPRegs:$dst, (V8selectfcc DFPRegs:$T, DFPRegs:$F,
239 [(set DFPRegs:$dst, (SPselectfcc DFPRegs:$T, DFPRegs:$F,
240240 imm:$Cond, FCC))]>;
241241 }
242242
476476 def SUBCCrr : F3_1<2, 0b010100,
477477 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
478478 "subcc $b, $c, $dst",
479 [(set IntRegs:$dst, (V8cmpicc IntRegs:$b, IntRegs:$c))]>;
479 [(set IntRegs:$dst, (SPcmpicc IntRegs:$b, IntRegs:$c))]>;
480480 def SUBCCri : F3_2<2, 0b010100,
481481 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
482482 "subcc $b, $c, $dst",
483 [(set IntRegs:$dst, (V8cmpicc IntRegs:$b, simm13:$c))]>;
483 [(set IntRegs:$dst, (SPcmpicc IntRegs:$b, simm13:$c))]>;
484484 def SUBXCCrr: F3_1<2, 0b011100,
485485 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
486486 "subxcc $b, $c, $dst", []>;
532532 // Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
533533
534534 // conditional branch class:
535 class BranchV8 cc, dag ops, string asmstr, list pattern>
535 class BranchSP cc, dag ops, string asmstr, list pattern>
536536 : F2_2 {
537537 let isBranch = 1;
538538 let isTerminator = 1;
541541 }
542542
543543 let isBarrier = 1 in
544 def BA : BranchV8<0b1000, (ops brtarget:$dst),
544 def BA : BranchSP<0b1000, (ops brtarget:$dst),
545545 "ba $dst",
546546 [(br bb:$dst)]>;
547547
548548 // FIXME: the encoding for the JIT should look at the condition field.
549 def BCOND : BranchV8<0, (ops brtarget:$dst, V8CC:$cc),
549 def BCOND : BranchSP<0, (ops brtarget:$dst, CCOp:$cc),
550550 "b$cc $dst",
551 [(V8bricc bb:$dst, imm:$cc, ICC)]>;
551 [(SPbricc bb:$dst, imm:$cc, ICC)]>;
552552
553553
554554 // Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
555555
556556 // floating-point conditional branch class:
557 class FPBranchV8 cc, dag ops, string asmstr, list pattern>
557 class FPBranchSP cc, dag ops, string asmstr, list pattern>
558558 : F2_2 {
559559 let isBranch = 1;
560560 let isTerminator = 1;
563563 }
564564
565565 // FIXME: the encoding for the JIT should look at the condition field.
566 def FBCOND : FPBranchV8<0, (ops brtarget:$dst, V8CC:$cc),
566 def FBCOND : FPBranchSP<0, (ops brtarget:$dst, CCOp:$cc),
567567 "fb$cc $dst",
568 [(V8brfcc bb:$dst, imm:$cc, FCC)]>;
568 [(SPbrfcc bb:$dst, imm:$cc, FCC)]>;
569569
570570
571571 // Section B.24 - Call and Link Instruction, p. 125
574574 hasDelaySlot = 1, isCall = 1, noResults = 1,
575575 Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
576576 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in {
577 def CALL : InstV8<(ops calltarget:$dst),
577 def CALL : InstSP<(ops calltarget:$dst),
578578 "call $dst", []> {
579579 bits<30> disp;
580580 let op = 1;
609609 def FITOS : F3_3<2, 0b110100, 0b011000100,
610610 (ops FPRegs:$dst, FPRegs:$src),
611611 "fitos $src, $dst",
612 [(set FPRegs:$dst, (V8itof FPRegs:$src))]>;
612 [(set FPRegs:$dst, (SPitof FPRegs:$src))]>;
613613 def FITOD : F3_3<2, 0b110100, 0b011001000,
614614 (ops DFPRegs:$dst, FPRegs:$src),
615615 "fitod $src, $dst",
616 [(set DFPRegs:$dst, (V8itof FPRegs:$src))]>;
616 [(set DFPRegs:$dst, (SPitof FPRegs:$src))]>;
617617
618618 // Convert Floating-point to Integer Instructions, p. 142
619619 def FSTOI : F3_3<2, 0b110100, 0b011010001,
620620 (ops FPRegs:$dst, FPRegs:$src),
621621 "fstoi $src, $dst",
622 [(set FPRegs:$dst, (V8ftoi FPRegs:$src))]>;
622 [(set FPRegs:$dst, (SPftoi FPRegs:$src))]>;
623623 def FDTOI : F3_3<2, 0b110100, 0b011010010,
624624 (ops FPRegs:$dst, DFPRegs:$src),
625625 "fdtoi $src, $dst",
626 [(set FPRegs:$dst, (V8ftoi DFPRegs:$src))]>;
626 [(set FPRegs:$dst, (SPftoi DFPRegs:$src))]>;
627627
628628 // Convert between Floating-point Formats Instructions, p. 143
629629 def FSTOD : F3_3<2, 0b110100, 0b011001001,
710710 def FCMPS : F3_3<2, 0b110101, 0b001010001,
711711 (ops FPRegs:$src1, FPRegs:$src2),
712712 "fcmps $src1, $src2\n\tnop",
713 [(set FCC, (V8cmpfcc FPRegs:$src1, FPRegs:$src2))]>;
713 [(set FCC, (SPcmpfcc FPRegs:$src1, FPRegs:$src2))]>;
714714 def FCMPD : F3_3<2, 0b110101, 0b001010010,
715715 (ops DFPRegs:$src1, DFPRegs:$src2),
716716 "fcmpd $src1, $src2\n\tnop",
717 [(set FCC, (V8cmpfcc DFPRegs:$src1, DFPRegs:$src2))]>;
717 [(set FCC, (SPcmpfcc DFPRegs:$src1, DFPRegs:$src2))]>;
718718
719719
720720 //===----------------------------------------------------------------------===//
726726 // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual.
727727 // FIXME: Add instruction encodings for the JIT some day.
728728 def MOVICCrr
729 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, V8CC:$cc),
729 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, CCOp:$cc),
730730 "mov$cc %icc, $F, $dst",
731731 [(set IntRegs:$dst,
732 (V8selecticc IntRegs:$F, IntRegs:$T, imm:$cc, ICC))]>;
732 (SPselecticc IntRegs:$F, IntRegs:$T, imm:$cc, ICC))]>;
733733 def MOVICCri
734 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, i32imm:$F, V8CC:$cc),
734 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, i32imm:$F, CCOp:$cc),
735735 "mov$cc %icc, $F, $dst",
736736 [(set IntRegs:$dst,
737 (V8selecticc simm11:$F, IntRegs:$T, imm:$cc, ICC))]>;
737 (SPselecticc simm11:$F, IntRegs:$T, imm:$cc, ICC))]>;
738738
739739 def MOVFCCrr
740 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, V8CC:$cc),
740 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, CCOp:$cc),
741741 "mov$cc %fcc0, $F, $dst",
742742 [(set IntRegs:$dst,
743 (V8selectfcc IntRegs:$F, IntRegs:$T, imm:$cc, FCC))]>;
743 (SPselectfcc IntRegs:$F, IntRegs:$T, imm:$cc, FCC))]>;
744744 def MOVFCCri
745 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, i32imm:$F, V8CC:$cc),
745 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, i32imm:$F, CCOp:$cc),
746746 "mov$cc %fcc0, $F, $dst",
747747 [(set IntRegs:$dst,
748 (V8selectfcc simm11:$F, IntRegs:$T, imm:$cc, FCC))]>;
748 (SPselectfcc simm11:$F, IntRegs:$T, imm:$cc, FCC))]>;
749749
750750 def FMOVS_ICC
751 : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, V8CC:$cc),
751 : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, CCOp:$cc),
752752 "fmovs$cc %icc, $F, $dst",
753753 [(set FPRegs:$dst,
754 (V8selecticc FPRegs:$F, FPRegs:$T, imm:$cc, ICC))]>;
754 (SPselecticc FPRegs:$F, FPRegs:$T, imm:$cc, ICC))]>;
755755 def FMOVD_ICC
756 : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, V8CC:$cc),
756 : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, CCOp:$cc),
757757 "fmovd$cc %icc, $F, $dst",
758758 [(set DFPRegs:$dst,
759 (V8selecticc DFPRegs:$F, DFPRegs:$T, imm:$cc, ICC))]>;
759 (SPselecticc DFPRegs:$F, DFPRegs:$T, imm:$cc, ICC))]>;
760760 def FMOVS_FCC
761 : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, V8CC:$cc),
761 : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, CCOp:$cc),
762762 "fmovs$cc %fcc0, $F, $dst",
763763 [(set FPRegs:$dst,
764 (V8selectfcc FPRegs:$F, FPRegs:$T, imm:$cc, FCC))]>;
764 (SPselectfcc FPRegs:$F, FPRegs:$T, imm:$cc, FCC))]>;
765765 def FMOVD_FCC
766 : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, V8CC:$cc),
766 : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, CCOp:$cc),
767767 "fmovd$cc %fcc0, $F, $dst",
768768 [(set DFPRegs:$dst,
769 (V8selectfcc DFPRegs:$F, DFPRegs:$T, imm:$cc, FCC))]>;
769 (SPselectfcc DFPRegs:$F, DFPRegs:$T, imm:$cc, FCC))]>;
770770
771771 }
772772
805805 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
806806
807807 // Global addresses, constant pool entries
808 def : Pat<(V8hi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
809 def : Pat<(V8lo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>;
810 def : Pat<(V8hi tconstpool:$in), (SETHIi tconstpool:$in)>;
811 def : Pat<(V8lo tconstpool:$in), (ORri G0, tconstpool:$in)>;
808 def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
809 def : Pat<(SPlo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>;
810 def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>;
811 def : Pat<(SPlo tconstpool:$in), (ORri G0, tconstpool:$in)>;
812812
813813 // Add reg, lo. This is used when taking the addr of a global/constpool entry.
814 def : Pat<(add IntRegs:$r, (V8lo tglobaladdr:$in)),
814 def : Pat<(add IntRegs:$r, (SPlo tglobaladdr:$in)),
815815 (ADDri IntRegs:$r, tglobaladdr:$in)>;
816 def : Pat<(add IntRegs:$r, (V8lo tconstpool:$in)),
816 def : Pat<(add IntRegs:$r, (SPlo tconstpool:$in)),
817817 (ADDri IntRegs:$r, tconstpool:$in)>;
818818
819819
None //===- SparcV8RegisterInfo.cpp - SparcV8 Register Information ---*- C++ -*-===//
0 //===- SparcRegisterInfo.cpp - SPARC Register Information -------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
66 //
77 //===----------------------------------------------------------------------===//
88 //
9 // This file contains the SparcV8 implementation of the MRegisterInfo class.
9 // This file contains the SPARC implementation of the MRegisterInfo class.
1010 //
1111 //===----------------------------------------------------------------------===//
1212
13 #include "SparcV8.h"
14 #include "SparcV8RegisterInfo.h"
15 #include "SparcV8Subtarget.h"
13 #include "Sparc.h"
14 #include "SparcRegisterInfo.h"
15 #include "SparcSubtarget.h"
1616 #include "llvm/CodeGen/MachineInstrBuilder.h"
1717 #include "llvm/CodeGen/MachineFunction.h"
1818 #include "llvm/CodeGen/MachineFrameInfo.h"
2121 #include
2222 using namespace llvm;
2323
24 SparcV8RegisterInfo::SparcV8RegisterInfo(SparcV8Subtarget &st)
25 : SparcV8GenRegisterInfo(V8::ADJCALLSTACKDOWN,
26 V8::ADJCALLSTACKUP), Subtarget(st) {
27 }
28
29 void SparcV8RegisterInfo::
24 SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st)
25 : SparcGenRegisterInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
26 Subtarget(st) {
27 }
28
29 void SparcRegisterInfo::
3030 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
3131 unsigned SrcReg, int FI,
3232 const TargetRegisterClass *RC) const {
3333 // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
34 if (RC == V8::IntRegsRegisterClass)
35 BuildMI(MBB, I, V8::STri, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg);
36 else if (RC == V8::FPRegsRegisterClass)
37 BuildMI(MBB, I, V8::STFri, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg);
38 else if (RC == V8::DFPRegsRegisterClass)
39 BuildMI(MBB, I, V8::STDFri, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg);
34 if (RC == SP::IntRegsRegisterClass)
35 BuildMI(MBB, I, SP::STri, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg);
36 else if (RC == SP::FPRegsRegisterClass)
37 BuildMI(MBB, I, SP::STFri, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg);
38 else if (RC == SP::DFPRegsRegisterClass)
39 BuildMI(MBB, I, SP::STDFri, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg);
4040 else
4141 assert(0 && "Can't store this register to stack slot");
4242 }
4343
44 void SparcV8RegisterInfo::
44 void SparcRegisterInfo::
4545 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
4646 unsigned DestReg, int FI,
4747 const TargetRegisterClass *RC) const {
48 if (RC == V8::IntRegsRegisterClass)
49 BuildMI(MBB, I, V8::LDri, 2, DestReg).addFrameIndex(FI).addImm(0);
50 else if (RC == V8::FPRegsRegisterClass)
51 BuildMI(MBB, I, V8::LDFri, 2, DestReg).addFrameIndex(FI).addImm (0);
52 else if (RC == V8::DFPRegsRegisterClass)
53 BuildMI(MBB, I, V8::LDDFri, 2, DestReg).addFrameIndex(FI).addImm(0);
48 if (RC == SP::IntRegsRegisterClass)
49 BuildMI(MBB, I, SP::LDri, 2, DestReg).addFrameIndex(FI).addImm(0);
50 else if (RC == SP::FPRegsRegisterClass)
51 BuildMI(MBB, I, SP::LDFri, 2, DestReg).addFrameIndex(FI).addImm (0);
52 else if (RC == SP::DFPRegsRegisterClass)
53 BuildMI(MBB, I, SP::LDDFri, 2, DestReg).addFrameIndex(FI).addImm(0);
5454 else
5555 assert(0 && "Can't load this register from stack slot");
5656 }
5757
58 void SparcV8RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
59 MachineBasicBlock::iterator I,
60 unsigned DestReg, unsigned SrcReg,
61 const TargetRegisterClass *RC) const {
62 if (RC == V8::IntRegsRegisterClass)
63 BuildMI(MBB, I, V8::ORrr, 2, DestReg).addReg(V8::G0).addReg(SrcReg);
64 else if (RC == V8::FPRegsRegisterClass)
65 BuildMI(MBB, I, V8::FMOVS, 1, DestReg).addReg(SrcReg);
66 else if (RC == V8::DFPRegsRegisterClass)
67 BuildMI(MBB, I, Subtarget.isV9() ? V8::FMOVD : V8::FpMOVD,
58 void SparcRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
59 MachineBasicBlock::iterator I,
60 unsigned DestReg, unsigned SrcReg,
61 const TargetRegisterClass *RC) const {
62 if (RC == SP::IntRegsRegisterClass)
63 BuildMI(MBB, I, SP::ORrr, 2, DestReg).addReg(SP::G0).addReg(SrcReg);
64 else if (RC == SP::FPRegsRegisterClass)
65 BuildMI(MBB, I, SP::FMOVS, 1, DestReg).addReg(SrcReg);
66 else if (RC == SP::DFPRegsRegisterClass)
67 BuildMI(MBB, I, Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD,
6868 1, DestReg).addReg(SrcReg);
6969 else
7070 assert (0 && "Can't copy this register");
7171 }
7272
73 MachineInstr *SparcV8RegisterInfo::foldMemoryOperand(MachineInstr* MI,
74 unsigned OpNum,
75 int FI) const {
73 MachineInstr *SparcRegisterInfo::foldMemoryOperand(MachineInstr* MI,
74 unsigned OpNum,
75 int FI) const {
7676 bool isFloat = false;
7777 switch (MI->getOpcode()) {
78 case V8::ORrr:
79 if (MI->getOperand(1).isRegister() && MI->getOperand(1).getReg() == V8::G0&&
78 case SP::ORrr:
79 if (MI->getOperand(1).isRegister() && MI->getOperand(1).getReg() == SP::G0&&
8080 MI->getOperand(0).isRegister() && MI->getOperand(2).isRegister()) {
8181 if (OpNum == 0) // COPY -> STORE
82 return BuildMI(V8::STri, 3).addFrameIndex(FI).addImm(0)
82 return BuildMI(SP::STri, 3).addFrameIndex(FI).addImm(0)
8383 .addReg(MI->getOperand(2).getReg());
8484 else // COPY -> LOAD
85 return BuildMI(V8::LDri, 2, MI->getOperand(0).getReg())
85 return BuildMI(SP::LDri, 2, MI->getOperand(0).getReg())
8686 .addFrameIndex(FI).addImm(0);
8787 }
8888 break;
89 case V8::FMOVS:
89 case SP::FMOVS:
9090 isFloat = true;
9191 // FALLTHROUGH
92 case V8::FMOVD:
92 case SP::FMOVD:
9393 if (OpNum == 0) // COPY -> STORE
94 return BuildMI(isFloat ? V8::STFri : V8::STDFri, 3)
94 return BuildMI(isFloat ? SP::STFri : SP::STDFri, 3)
9595 .addFrameIndex(FI).addImm(0).addReg(MI->getOperand(1).getReg());
9696 else // COPY -> LOAD
97 return BuildMI(isFloat ? V8::LDFri : V8::LDDFri, 2,
97 return BuildMI(isFloat ? SP::LDFri : SP::LDDFri, 2,
9898 MI->getOperand(0).getReg()).addFrameIndex(FI).addImm(0);
9999 break;
100100 }
101101 return 0;
102102 }
103103
104 void SparcV8RegisterInfo::
104 void SparcRegisterInfo::
105105 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
106106 MachineBasicBlock::iterator I) const {
107107 MachineInstr &MI = *I;
108108 int Size = MI.getOperand(0).getImmedValue();
109 if (MI.getOpcode() == V8::ADJCALLSTACKDOWN)
109 if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
110110 Size = -Size;
111111 if (Size)
112 BuildMI(MBB, I, V8::ADDri, 2, V8::O6).addReg(V8::O6).addSImm(Size);
112 BuildMI(MBB, I, SP::ADDri, 2, SP::O6).addReg(SP::O6).addSImm(Size);
113113 MBB.erase(I);
114114 }
115115
116116 void
117 SparcV8RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
117 SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
118118 unsigned i = 0;
119119 MachineInstr &MI = *II;
120120 while (!MI.getOperand(i).isFrameIndex()) {
133133 if (Offset >= -4096 && Offset <= 4095) {
134134 // If the offset is small enough to fit in the immediate field, directly
135135 // encode it.
136 MI.SetMachineOperandReg(i, V8::I6);
136 MI.SetMachineOperandReg(i, SP::I6);
137137 MI.SetMachineOperandConst(i+1, MachineOperand::MO_SignExtendedImmed,Offset);
138138 } else {
139139 // Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to
140140 // scavenge a register here instead of reserving G1 all of the time.
141141 unsigned OffHi = (unsigned)Offset >> 10U;
142 BuildMI(*MI.getParent(), II, V8::SETHIi, 1, V8::G1).addImm(OffHi);
142 BuildMI(*MI.getParent(), II, SP::SETHIi, 1, SP::G1).addImm(OffHi);
143143 // Emit G1 = G1 + I6
144 BuildMI(*MI.getParent(), II, V8::ADDrr, 2,
145 V8::G1).addReg(V8::G1).addReg(V8::I6);
144 BuildMI(*MI.getParent(), II, SP::ADDrr, 2,
145 SP::G1).addReg(SP::G1).addReg(SP::I6);
146146 // Insert: G1+%lo(offset) into the user.
147 MI.SetMachineOperandReg(i, V8::G1);
147 MI.SetMachineOperandReg(i, SP::G1);
148148 MI.SetMachineOperandConst(i+1, MachineOperand::MO_SignExtendedImmed,
149149 Offset & ((1 << 10)-1));
150150 }
151151 }
152152
153 void SparcV8RegisterInfo::
153 void SparcRegisterInfo::
154154 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
155155
156 void SparcV8RegisterInfo::emitPrologue(MachineFunction &MF) const {
156 void SparcRegisterInfo::emitPrologue(MachineFunction &MF) const {
157157 MachineBasicBlock &MBB = MF.front();
158158 MachineFrameInfo *MFI = MF.getFrameInfo();
159159
174174 NumBytes = -NumBytes;
175175
176176 if (NumBytes >= -4096) {
177 BuildMI(MBB, MBB.begin(), V8::SAVEri, 2,
178 V8::O6).addImm(NumBytes).addReg(V8::O6);
177 BuildMI(MBB, MBB.begin(), SP::SAVEri, 2,
178 SP::O6).addImm(NumBytes).addReg(SP::O6);
179179 } else {
180180 MachineBasicBlock::iterator InsertPt = MBB.begin();
181181 // Emit this the hard way. This clobbers G1 which we always know is
182182 // available here.
183183 unsigned OffHi = (unsigned)NumBytes >> 10U;
184 BuildMI(MBB, InsertPt, V8::SETHIi, 1, V8::G1).addImm(OffHi);
184 BuildMI(MBB, InsertPt, SP::SETHIi, 1, SP::G1).addImm(OffHi);
185185 // Emit G1 = G1 + I6
186 BuildMI(MBB, InsertPt, V8::ORri, 2, V8::G1)
187 .addReg(V8::G1).addImm(NumBytes & ((1 << 10)-1));
188 BuildMI(MBB, InsertPt, V8::SAVErr, 2,
189 V8::O6).addReg(V8::O6).addReg(V8::G1);
190 }
191 }
192
193 void SparcV8RegisterInfo::emitEpilogue(MachineFunction &MF,
194 MachineBasicBlock &MBB) const {
186 BuildMI(MBB, InsertPt, SP::ORri, 2, SP::G1)
187 .addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1));
188 BuildMI(MBB, InsertPt, SP::SAVErr, 2,
189 SP::O6).addReg(SP::O6).addReg(SP::G1);
190 }
191 }
192
193 void SparcRegisterInfo::emitEpilogue(MachineFunction &MF,
194 MachineBasicBlock &MBB) const {
195195 MachineBasicBlock::iterator MBBI = prior(MBB.end());
196 assert(MBBI->getOpcode() == V8::RETL &&
196 assert(MBBI->getOpcode() == SP::RETL &&
197197 "Can only put epilog before 'retl' instruction!");
198 BuildMI(MBB, MBBI, V8::RESTORErr, 2, V8::G0).addReg(V8::G0).addReg(V8::G0);
199 }
200
201 #include "SparcV8GenRegisterInfo.inc"
202
198 BuildMI(MBB, MBBI, SP::RESTORErr, 2, SP::G0).addReg(SP::G0).addReg(SP::G0);
199 }
200
201 #include "SparcGenRegisterInfo.inc"
202
None //===- SparcV8RegisterInfo.h - SparcV8 Register Information Impl -*- C++ -*-==//
0 //===- SparcRegisterInfo.h - Sparc Register Information Impl ----*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
66 //
77 //===----------------------------------------------------------------------===//
88 //
9 // This file contains the SparcV8 implementation of the MRegisterInfo class.
9 // This file contains the Sparc implementation of the MRegisterInfo class.
1010 //
1111 //===----------------------------------------------------------------------===//
1212
13 #ifndef SPARCV8REGISTERINFO_H
14 #define SPARCV8REGISTERINFO_H
13 #ifndef SPARCREGISTERINFO_H
14 #define SPARCREGISTERINFO_H
1515
1616 #include "llvm/Target/MRegisterInfo.h"
17 #include "SparcV8GenRegisterInfo.h.inc"
17 #include "SparcGenRegisterInfo.h.inc"
1818
1919 namespace llvm {
2020
21 class SparcV8Subtarget;
21 class SparcSubtarget;
2222 class Type;
2323
24 struct SparcV8RegisterInfo : public SparcV8GenRegisterInfo {
25 SparcV8Subtarget &Subtarget;
24 struct SparcRegisterInfo : public SparcGenRegisterInfo {
25 SparcSubtarget &Subtarget;
2626
27 SparcV8RegisterInfo(SparcV8Subtarget &st);
27 SparcRegisterInfo(SparcSubtarget &st);
2828
2929 /// Code Generation virtual methods...
3030 void storeRegToStackSlot(MachineBasicBlock &MBB,
None //===- SparcV8RegisterInfo.td - SparcV8 Register defs ------*- tablegen -*-===//
0 //===- SparcRegisterInfo.td - Sparc Register defs ----------*- tablegen -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
77 //===----------------------------------------------------------------------===//
88
99 //===----------------------------------------------------------------------===//
10 // Declarations that describe the SparcV8 register file
10 // Declarations that describe the Sparc register file
1111 //===----------------------------------------------------------------------===//
1212
1313 class SparcReg : Register {
1414 field bits<5> Num;
15 let Namespace = "V8";
15 let Namespace = "SP";
1616 }
1717
1818 // Registers are identified with 5-bit ID numbers.
6868 def D14 : Rd<28, "F28", [F28, F29]>; def D15 : Rd<30, "F30", [F30, F31]>;
6969
7070 /// Integer and FP Condition codes.
71 let Namespace = "V8" in {
71 let Namespace = "SP" in {
7272 def ICC : Register<"ICC">;
7373 def FCC : Register<"FCC">;
7474 }
75 def FLAGS_REGS : RegisterClass<"V8", [FlagVT], 32, [ICC, FCC]> {
75 def FLAGS_REGS : RegisterClass<"SP", [FlagVT], 32, [ICC, FCC]> {
7676 let Size = 32;
7777 }
7878
8181 // FIXME: the register order should be defined in terms of the preferred
8282 // allocation order...
8383 //
84 def IntRegs : RegisterClass<"V8", [i32], 32, [L0, L1, L2, L3, L4, L5, L6, L7,
84 def IntRegs : RegisterClass<"SP", [i32], 32, [L0, L1, L2, L3, L4, L5, L6, L7,
8585 I0, I1, I2, I3, I4, I5,
8686 O0, O1, O2, O3, O4, O5, O7,
8787
109109 }];
110110 }
111111
112 def FPRegs : RegisterClass<"V8", [f32], 32, [F0, F1, F2, F3, F4, F5, F6, F7, F8,
112 def FPRegs : RegisterClass<"SP", [f32], 32, [F0, F1, F2, F3, F4, F5, F6, F7, F8,
113113 F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21, F22,
114114 F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
115115
116 def DFPRegs : RegisterClass<"V8", [f64], 64, [D0, D1, D2, D3, D4, D5, D6, D7,
116 def DFPRegs : RegisterClass<"SP", [f64], 64, [D0, D1, D2, D3, D4, D5, D6, D7,
117117 D8, D9, D10, D11, D12, D13, D14, D15]>;
None //===- SparcV8Subtarget.cpp - SPARC Subtarget Information -----------------===//
0 //===- SparcSubtarget.cpp - SPARC Subtarget Information -------------------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
1010 //
1111 //===----------------------------------------------------------------------===//
1212
13 #include "SparcV8Subtarget.h"
14 #include "SparcV8GenSubtarget.inc"
13 #include "SparcSubtarget.h"
14 #include "SparcGenSubtarget.inc"
1515 using namespace llvm;
1616
1717 // FIXME: temporary.
2121 cl::desc("Enable V9 instructions in the V8 target"));
2222 }
2323
24 SparcV8Subtarget::SparcV8Subtarget(const Module &M, const std::string &FS) {
24 SparcSubtarget::SparcSubtarget(const Module &M, const std::string &FS) {
2525 // Set the default features.
2626 IsV9 = false;
2727 V8DeprecatedInsts = false;
None //=====-- SparcV8Subtarget.h - Define Subtarget for the SPARC -*- C++ -*--====//
0 //=====-- SparcSubtarget.h - Define Subtarget for the SPARC ----*- C++ -*-====//
11 //
22 // The LLVM Compiler Infrastructure
33 //
1919 namespace llvm {
2020 class Module;
2121
22 class SparcV8Subtarget : public TargetSubtarget {
22 class SparcSubtarget : public TargetSubtarget {
2323 bool IsV9;
2424 bool V8DeprecatedInsts;
2525 bool IsVIS;
2626 public:
27 SparcV8Subtarget(const Module &M, const std::string &FS);
27 SparcSubtarget(const Module &M, const std::string &FS);
2828
2929 bool isV9() const { return IsV9; }
3030 bool isVIS() const { return IsVIS; }
None //===-- SparcV8TargetMachine.cpp - Define TargetMachine for SparcV8 -------===//
0 //===-- SparcTargetMachine.cpp - Define TargetMachine for Sparc -----------===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
99 //
1010 //===----------------------------------------------------------------------===//
1111
12 #include "SparcV8TargetMachine.h"
13 #include "SparcV8.h"
12 #include "SparcTargetMachine.h"
13 #include "Sparc.h"
1414 #include "llvm/Assembly/PrintModulePass.h"
1515 #include "llvm/Module.h"
1616 #include "llvm/PassManager.h"
2525
2626 namespace {
2727 // Register the target.
28 RegisterTargetV8TargetMachine> X("sparcv8"," SPARC V8 (experimental)");
28 RegisterTargetTargetMachine> X("sparc", " SPARC");
2929 }
3030
31 /// SparcV8TargetMachine ctor - Create an ILP32 architecture model
31 /// SparcTargetMachine ctor - Create an ILP32 architecture model
3232 ///
33 SparcV8TargetMachine::SparcV8TargetMachine(const Module &M,
34 IntrinsicLowering *IL,
35 const std::string &FS)
36 : TargetMachine("SparcV8", IL, false, 4, 4),
33 SparcTargetMachine::SparcTargetMachine(const Module &M, IntrinsicLowering *IL,
34 const std::string &FS)
35 : TargetMachine("Sparc", IL, false, 4, 4),
3736 Subtarget(M, FS), InstrInfo(Subtarget),
3837 FrameInfo(TargetFrameInfo::StackGrowsDown, 8, 0) {
3938 }
4039
41 unsigned SparcV8TargetMachine::getModuleMatchQuality(const Module &M) {
40 unsigned SparcTargetMachine::getModuleMatchQuality(const Module &M) {
4241 std::string TT = M.getTargetTriple();
4342 if (TT.size() >= 6 && std::string(TT.begin(), TT.begin()+6) == "sparc-")
4443 return 20;
4645 if (M.getEndianness() == Module::BigEndian &&
4746 M.getPointerSize() == Module::Pointer32)
4847 #ifdef __sparc__
49 return 20; // BE/32 ==> Prefer sparcv8 on sparc
48 return 20; // BE/32 ==> Prefer sparc on sparc
5049 #else
5150 return 5; // BE/32 ==> Prefer ppc elsewhere
5251 #endif
6059 /// addPassesToEmitFile - Add passes to the specified pass manager
6160 /// to implement a static compiler for this target.
6261 ///
63 bool SparcV8TargetMachine::addPassesToEmitFile(PassManager &PM,
64 std::ostream &Out,
65 CodeGenFileType FileType,
66 bool Fast) {
62 bool SparcTargetMachine::addPassesToEmitFile(PassManager &PM, std::ostream &Out,
63 CodeGenFileType FileType,
64 bool Fast) {
6765 if (FileType != TargetMachine::AssemblyFile) return true;
6866
6967 // FIXME: Implement efficient support for garbage collection intrinsics.
8280 // Make sure that no unreachable blocks are instruction selected.
8381 PM.add(createUnreachableBlockEliminationPass());
8482
85 PM.add(createSparcV8ISelDag(*this));
83 PM.add(createSparcISelDag(*this));
8684
8785 // Print machine instructions as they were initially generated.
8886 if (PrintMachineCode)
9694 if (PrintMachineCode)
9795 PM.add(createMachineFunctionPrinterPass(&std::cerr));
9896
99 PM.add(createSparcV8FPMoverPass(*this));
97 PM.add(createSparcFPMoverPass(*this));
10098
101 PM.add(createSparcV8DelaySlotFillerPass(*this));
99 PM.add(createSparcDelaySlotFillerPass(*this));
102100
103101 // Print machine instructions after filling delay slots.
104102 if (PrintMachineCode)
105103 PM.add(createMachineFunctionPrinterPass(&std::cerr));
106104
107105 // Output assembly language.
108 PM.add(createSparcV8CodePrinterPass(Out, *this));
106 PM.add(createSparcCodePrinterPass(Out, *this));
109107
110108 // Delete the MachineInstrs we generated, since they're no longer needed.
111109 PM.add(createMachineCodeDeleter());
None //===-- SparcV8TargetMachine.h - Define TargetMachine for SparcV8 -*- C++ -*-=//
0 //===-- SparcTargetMachine.h - Define TargetMachine for Sparc ---*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
66 //
77 //===----------------------------------------------------------------------===//
88 //
9 // This file declares the SparcV8 specific subclass of TargetMachine.
9 // This file declares the Sparc specific subclass of TargetMachine.
1010 //
1111 //===----------------------------------------------------------------------===//
1212
13 #ifndef SPARCV8TARGETMACHINE_H
14 #define SPARCV8TARGETMACHINE_H
13 #ifndef SPARCTARGETMACHINE_H
14 #define SPARCTARGETMACHINE_H
1515
1616 #include "llvm/Target/TargetMachine.h"
1717 #include "llvm/Target/TargetFrameInfo.h"
1818 #include "llvm/PassManager.h"
19 #include "SparcV8InstrInfo.h"
20 #include "SparcV8Subtarget.h"
19 #include "SparcInstrInfo.h"
20 #include "SparcSubtarget.h"
2121
2222 namespace llvm {
2323
2424 class IntrinsicLowering;
2525 class Module;
2626
27 class SparcV8TargetMachine : public TargetMachine {
28 SparcV8Subtarget Subtarget;
29 SparcV8InstrInfo InstrInfo;
27 class SparcTargetMachine : public TargetMachine {
28 SparcSubtarget Subtarget;
29 SparcInstrInfo InstrInfo;
3030 TargetFrameInfo FrameInfo;
3131 public:
32 SparcV8TargetMachine(const Module &M, IntrinsicLowering *IL,
33 const std::string &FS);
32 SparcTargetMachine(const Module &M, IntrinsicLowering *IL,
33 const std::string &FS);
3434
35 virtual const SparcV8InstrInfo *getInstrInfo() const { return &InstrInfo; }
35 virtual const SparcInstrInfo *getInstrInfo() const { return &InstrInfo; }
3636 virtual const TargetFrameInfo *getFrameInfo() const { return &FrameInfo; }
3737 virtual const TargetSubtarget *getSubtargetImpl() const{ return &Subtarget; }
3838 virtual const MRegisterInfo *getRegisterInfo() const {