llvm.org GIT mirror llvm / 7c4ce30
Change the PassManager from a reference to a pointer. The TargetPassManager's default constructor wants to initialize the PassManager to 'null'. But it's illegal to bind a null reference to a null l-value. Make the ivar a pointer instead. PR12468 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155902 91177308-0d34-0410-b5e6-96231b3b80d8 Bill Wendling 8 years ago
13 changed file(s) with 72 addition(s) and 74 deletion(s). Raw diff Collapse all Expand all
5555
5656 protected:
5757 TargetMachine *TM;
58 PassManagerBase ±
58 PassManagerBase *PM;
5959 PassConfigImpl *Impl; // Internal data structures
6060 bool Initialized; // Flagged after all passes are configured.
6161
206206 // Out of line constructor provides default values for pass options and
207207 // registers all common codegen passes.
208208 TargetPassConfig::TargetPassConfig(TargetMachine *tm, PassManagerBase &pm)
209 : ImmutablePass(ID), TM(tm), PM(pm), Impl(0), Initialized(false),
209 : ImmutablePass(ID), TM(tm), PM(&pm), Impl(0), Initialized(false),
210210 DisableVerify(false),
211211 EnableTailMerge(true) {
212212
233233 }
234234
235235 TargetPassConfig::TargetPassConfig()
236 : ImmutablePass(ID), PM(*(PassManagerBase*)0) {
236 : ImmutablePass(ID), PM(0) {
237237 llvm_unreachable("TargetPassConfig should not be constructed on-the-fly");
238238 }
239239
268268 Pass *P = Pass::createPass(FinalID);
269269 if (!P)
270270 llvm_unreachable("Pass ID not registered");
271 PM.add(P);
271 PM->add(P);
272272 return FinalID;
273273 }
274274
275275 void TargetPassConfig::printAndVerify(const char *Banner) const {
276276 if (TM->shouldPrintMachineCode())
277 PM.add(createMachineFunctionPrinterPass(dbgs(), Banner));
277 PM->add(createMachineFunctionPrinterPass(dbgs(), Banner));
278278
279279 if (VerifyMachineCode)
280 PM.add(createMachineVerifierPass(Banner));
280 PM->add(createMachineVerifierPass(Banner));
281281 }
282282
283283 /// Add common target configurable passes that perform LLVM IR to IR transforms
287287 // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
288288 // BasicAliasAnalysis wins if they disagree. This is intended to help
289289 // support "obvious" type-punning idioms.
290 PM.add(createTypeBasedAliasAnalysisPass());
291 PM.add(createBasicAliasAnalysisPass());
290 PM->add(createTypeBasedAliasAnalysisPass());
291 PM->add(createBasicAliasAnalysisPass());
292292
293293 // Before running any passes, run the verifier to determine if the input
294294 // coming from the front-end and/or optimizer is valid.
295295 if (!DisableVerify)
296 PM.add(createVerifierPass());
296 PM->add(createVerifierPass());
297297
298298 // Run loop strength reduction before anything else.
299299 if (getOptLevel() != CodeGenOpt::None && !DisableLSR) {
300 PM.add(createLoopStrengthReducePass(getTargetLowering()));
300 PM->add(createLoopStrengthReducePass(getTargetLowering()));
301301 if (PrintLSR)
302 PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &dbgs()));
303 }
304
305 PM.add(createGCLoweringPass());
302 PM->add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &dbgs()));
303 }
304
305 PM->add(createGCLoweringPass());
306306
307307 // Make sure that no unreachable blocks are instruction selected.
308 PM.add(createUnreachableBlockEliminationPass());
308 PM->add(createUnreachableBlockEliminationPass());
309309 }
310310
311311 /// Add common passes that perform LLVM IR to IR transforms in preparation for
312312 /// instruction selection.
313313 void TargetPassConfig::addISelPrepare() {
314314 if (getOptLevel() != CodeGenOpt::None && !DisableCGP)
315 PM.add(createCodeGenPreparePass(getTargetLowering()));
316
317 PM.add(createStackProtectorPass(getTargetLowering()));
315 PM->add(createCodeGenPreparePass(getTargetLowering()));
316
317 PM->add(createStackProtectorPass(getTargetLowering()));
318318
319319 addPreISel();
320320
321321 if (PrintISelInput)
322 PM.add(createPrintFunctionPass("\n\n"
323 "*** Final LLVM Code input to ISel ***\n",
324 &dbgs()));
322 PM->add(createPrintFunctionPass("\n\n"
323 "*** Final LLVM Code input to ISel ***\n",
324 &dbgs()));
325325
326326 // All passes which modify the LLVM IR are now complete; run the verifier
327327 // to ensure that the IR is valid.
328328 if (!DisableVerify)
329 PM.add(createVerifierPass());
329 PM->add(createVerifierPass());
330330 }
331331
332332 /// Add the complete set of target-independent postISel code generator passes.
404404 // GC
405405 addPass(GCMachineCodeAnalysisID);
406406 if (PrintGCInfo)
407 PM.add(createGCInfoPrinter(dbgs()));
407 PM->add(createGCInfoPrinter(dbgs()));
408408
409409 // Basic block placement.
410410 if (getOptLevel() != CodeGenOpt::None)
521521 addPass(PHIEliminationID);
522522 addPass(TwoAddressInstructionPassID);
523523
524 PM.add(RegAllocPass);
524 PM->add(RegAllocPass);
525525 printAndVerify("After Register Allocation");
526526 }
527527
563563 printAndVerify("After Machine Scheduling");
564564
565565 // Add the selected register allocation pass.
566 PM.add(RegAllocPass);
566 PM->add(RegAllocPass);
567567 printAndVerify("After Register Allocation");
568568
569569 // FinalizeRegAlloc is convenient until MachineInstrBundles is more mature,
135135
136136 bool ARMPassConfig::addPreISel() {
137137 if (TM->getOptLevel() != CodeGenOpt::None && EnableGlobalMerge)
138 PM.add(createGlobalMergePass(TM->getTargetLowering()));
138 PM->add(createGlobalMergePass(TM->getTargetLowering()));
139139
140140 return false;
141141 }
142142
143143 bool ARMPassConfig::addInstSelector() {
144 PM.add(createARMISelDag(getARMTargetMachine(), getOptLevel()));
144 PM->add(createARMISelDag(getARMTargetMachine(), getOptLevel()));
145145 return false;
146146 }
147147
148148 bool ARMPassConfig::addPreRegAlloc() {
149149 // FIXME: temporarily disabling load / store optimization pass for Thumb1.
150150 if (getOptLevel() != CodeGenOpt::None && !getARMSubtarget().isThumb1Only())
151 PM.add(createARMLoadStoreOptimizationPass(true));
151 PM->add(createARMLoadStoreOptimizationPass(true));
152152 if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA9())
153 PM.add(createMLxExpansionPass());
153 PM->add(createMLxExpansionPass());
154154 return true;
155155 }
156156
158158 // FIXME: temporarily disabling load / store optimization pass for Thumb1.
159159 if (getOptLevel() != CodeGenOpt::None) {
160160 if (!getARMSubtarget().isThumb1Only()) {
161 PM.add(createARMLoadStoreOptimizationPass());
161 PM->add(createARMLoadStoreOptimizationPass());
162162 printAndVerify("After ARM load / store optimizer");
163163 }
164164 if (getARMSubtarget().hasNEON())
165 PM.add(createExecutionDependencyFixPass(&ARM::DPRRegClass));
165 PM->add(createExecutionDependencyFixPass(&ARM::DPRRegClass));
166166 }
167167
168168 // Expand some pseudo instructions into multiple instructions to allow
169169 // proper scheduling.
170 PM.add(createARMExpandPseudoPass());
170 PM->add(createARMExpandPseudoPass());
171171
172172 if (getOptLevel() != CodeGenOpt::None) {
173173 if (!getARMSubtarget().isThumb1Only())
174174 addPass(IfConverterID);
175175 }
176176 if (getARMSubtarget().isThumb2())
177 PM.add(createThumb2ITBlockPass());
177 PM->add(createThumb2ITBlockPass());
178178
179179 return true;
180180 }
182182 bool ARMPassConfig::addPreEmitPass() {
183183 if (getARMSubtarget().isThumb2()) {
184184 if (!getARMSubtarget().prefers32BitThumb())
185 PM.add(createThumb2SizeReductionPass());
185 PM->add(createThumb2SizeReductionPass());
186186
187187 // Constant island pass work on unbundled instructions.
188188 addPass(UnpackMachineBundlesID);
189189 }
190190
191 PM.add(createARMConstantIslandPass());
191 PM->add(createARMConstantIslandPass());
192192
193193 return true;
194194 }
7171
7272 bool SPUPassConfig::addInstSelector() {
7373 // Install an instruction selector.
74 PM.add(createSPUISelDag(getSPUTargetMachine()));
74 PM->add(createSPUISelDag(getSPUTargetMachine()));
7575 return false;
7676 }
7777
8484 (BuilderFunc)(intptr_t)sys::DynamicLibrary::SearchForAddressOfSymbol(
8585 "createTCESchedulerPass");
8686 if (schedulerCreator != NULL)
87 PM.add(schedulerCreator("cellspu"));
87 PM->add(schedulerCreator("cellspu"));
8888
8989 //align instructions with nops/lnops for dual issue
90 PM.add(createSPUNopFillerPass(getSPUTargetMachine()));
90 PM->add(createSPUNopFillerPass(getSPUTargetMachine()));
9191 return true;
9292 }
9999 }
100100
101101 bool HexagonPassConfig::addInstSelector() {
102 PM.add(createHexagonRemoveExtendOps(getHexagonTargetMachine()));
103 PM.add(createHexagonISelDag(getHexagonTargetMachine()));
104 PM.add(createHexagonPeephole());
102 PM->add(createHexagonRemoveExtendOps(getHexagonTargetMachine()));
103 PM->add(createHexagonISelDag(getHexagonTargetMachine()));
104 PM->add(createHexagonPeephole());
105105 return false;
106106 }
107107
108108
109109 bool HexagonPassConfig::addPreRegAlloc() {
110110 if (!DisableHardwareLoops) {
111 PM.add(createHexagonHardwareLoops());
111 PM->add(createHexagonHardwareLoops());
112112 }
113113
114114 return false;
115115 }
116116
117117 bool HexagonPassConfig::addPostRegAlloc() {
118 PM.add(createHexagonCFGOptimizer(getHexagonTargetMachine()));
118 PM->add(createHexagonCFGOptimizer(getHexagonTargetMachine()));
119119 return true;
120120 }
121121
128128 bool HexagonPassConfig::addPreEmitPass() {
129129
130130 if (!DisableHardwareLoops) {
131 PM.add(createHexagonFixupHwLoops());
131 PM->add(createHexagonFixupHwLoops());
132132 }
133133
134134 // Expand Spill code for predicate registers.
135 PM.add(createHexagonExpandPredSpillCode(getHexagonTargetMachine()));
135 PM->add(createHexagonExpandPredSpillCode(getHexagonTargetMachine()));
136136
137137 // Split up TFRcondsets into conditional transfers.
138 PM.add(createHexagonSplitTFRCondSets(getHexagonTargetMachine()));
138 PM->add(createHexagonSplitTFRCondSets(getHexagonTargetMachine()));
139139
140140 return false;
141141 }
6767 // Install an instruction selector pass using
6868 // the ISelDag to gen MBlaze code.
6969 bool MBlazePassConfig::addInstSelector() {
70 PM.add(createMBlazeISelDag(getMBlazeTargetMachine()));
70 PM->add(createMBlazeISelDag(getMBlazeTargetMachine()));
7171 return false;
7272 }
7373
7575 // machine code is emitted. return true if -print-machineinstrs should
7676 // print out the code after the passes.
7777 bool MBlazePassConfig::addPreEmitPass() {
78 PM.add(createMBlazeDelaySlotFillerPass(getMBlazeTargetMachine()));
78 PM->add(createMBlazeDelaySlotFillerPass(getMBlazeTargetMachine()));
7979 return true;
8080 }
5959
6060 bool MSP430PassConfig::addInstSelector() {
6161 // Install an instruction selector.
62 PM.add(createMSP430ISelDag(getMSP430TargetMachine(), getOptLevel()));
62 PM->add(createMSP430ISelDag(getMSP430TargetMachine(), getOptLevel()));
6363 return false;
6464 }
6565
6666 bool MSP430PassConfig::addPreEmitPass() {
6767 // Must run branch selection immediately preceding the asm printer.
68 PM.add(createMSP430BranchSelectionPass());
68 PM->add(createMSP430BranchSelectionPass());
6969 return false;
7070 }
116116
117117 // Install an instruction selector pass using
118118 // the ISelDag to gen Mips code.
119 bool MipsPassConfig::addInstSelector()
120 {
121 PM.add(createMipsISelDag(getMipsTargetMachine()));
119 bool MipsPassConfig::addInstSelector() {
120 PM->add(createMipsISelDag(getMipsTargetMachine()));
122121 return false;
123122 }
124123
125124 // Implemented by targets that want to run passes immediately before
126125 // machine code is emitted. return true if -print-machineinstrs should
127126 // print out the code after the passes.
128 bool MipsPassConfig::addPreEmitPass()
129 {
130 PM.add(createMipsDelaySlotFillerPass(getMipsTargetMachine()));
127 bool MipsPassConfig::addPreEmitPass() {
128 PM->add(createMipsDelaySlotFillerPass(getMipsTargetMachine()));
131129 return true;
132130 }
133131
135133 // Do not restore $gp if target is Mips64.
136134 // In N32/64, $gp is a callee-saved register.
137135 if (!getMipsSubtarget().hasMips64())
138 PM.add(createMipsEmitGPRestorePass(getMipsTargetMachine()));
136 PM->add(createMipsEmitGPRestorePass(getMipsTargetMachine()));
139137 return true;
140138 }
141139
142140 bool MipsPassConfig::addPreSched2() {
143 PM.add(createMipsExpandPseudoPass(getMipsTargetMachine()));
141 PM->add(createMipsExpandPseudoPass(getMipsTargetMachine()));
144142 return true;
145143 }
146144
129129 }
130130
131131 bool PTXPassConfig::addInstSelector() {
132 PM.add(createPTXISelDag(getPTXTargetMachine(), getOptLevel()));
132 PM->add(createPTXISelDag(getPTXTargetMachine(), getOptLevel()));
133133 return false;
134134 }
135135
144144
145145 bool PTXPassConfig::addPostRegAlloc() {
146146 // PTXMFInfoExtract must after register allocation!
147 //PM.add(createPTXMFInfoExtract(getPTXTargetMachine()));
147 //PM->add(createPTXMFInfoExtract(getPTXTargetMachine()));
148148 return false;
149149 }
150150
158158 }
159159
160160 bool PTXPassConfig::addPreEmitPass() {
161 PM.add(createPTXMFInfoExtract(getPTXTargetMachine(), getOptLevel()));
162 PM.add(createPTXFPRoundingModePass(getPTXTargetMachine(), getOptLevel()));
161 PM->add(createPTXMFInfoExtract(getPTXTargetMachine(), getOptLevel()));
162 PM->add(createPTXFPRoundingModePass(getPTXTargetMachine(), getOptLevel()));
163163 return true;
164164 }
9797
9898 bool PPCPassConfig::addInstSelector() {
9999 // Install an instruction selector.
100 PM.add(createPPCISelDag(getPPCTargetMachine()));
100 PM->add(createPPCISelDag(getPPCTargetMachine()));
101101 return false;
102102 }
103103
104104 bool PPCPassConfig::addPreEmitPass() {
105105 // Must run branch selection immediately preceding the asm printer.
106 PM.add(createPPCBranchSelectionPass());
106 PM->add(createPPCBranchSelectionPass());
107107 return false;
108108 }
109109
5858 }
5959
6060 bool SparcPassConfig::addInstSelector() {
61 PM.add(createSparcISelDag(getSparcTargetMachine()));
61 PM->add(createSparcISelDag(getSparcTargetMachine()));
6262 return false;
6363 }
6464
6666 /// passes immediately before machine code is emitted. This should return
6767 /// true if -print-machineinstrs should print out the code after the passes.
6868 bool SparcPassConfig::addPreEmitPass(){
69 PM.add(createSparcFPMoverPass(getSparcTargetMachine()));
70 PM.add(createSparcDelaySlotFillerPass(getSparcTargetMachine()));
69 PM->add(createSparcFPMoverPass(getSparcTargetMachine()));
70 PM->add(createSparcDelaySlotFillerPass(getSparcTargetMachine()));
7171 return true;
7272 }
7373
144144
145145 bool X86PassConfig::addInstSelector() {
146146 // Install an instruction selector.
147 PM.add(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
147 PM->add(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
148148
149149 // For 32-bit, prepend instructions to set the "global base reg" for PIC.
150150 if (!getX86Subtarget().is64Bit())
151 PM.add(createGlobalBaseRegPass());
151 PM->add(createGlobalBaseRegPass());
152152
153153 return false;
154154 }
155155
156156 bool X86PassConfig::addPreRegAlloc() {
157 PM.add(createX86MaxStackAlignmentHeuristicPass());
157 PM->add(createX86MaxStackAlignmentHeuristicPass());
158158 return false; // -print-machineinstr shouldn't print after this.
159159 }
160160
161161 bool X86PassConfig::addPostRegAlloc() {
162 PM.add(createX86FloatingPointStackifierPass());
162 PM->add(createX86FloatingPointStackifierPass());
163163 return true; // -print-machineinstr should print after this.
164164 }
165165
166166 bool X86PassConfig::addPreEmitPass() {
167167 bool ShouldPrint = false;
168168 if (getOptLevel() != CodeGenOpt::None && getX86Subtarget().hasSSE2()) {
169 PM.add(createExecutionDependencyFixPass(&X86::VR128RegClass));
169 PM->add(createExecutionDependencyFixPass(&X86::VR128RegClass));
170170 ShouldPrint = true;
171171 }
172172
173173 if (getX86Subtarget().hasAVX() && UseVZeroUpper) {
174 PM.add(createX86IssueVZeroUpperPass());
174 PM->add(createX86IssueVZeroUpperPass());
175175 ShouldPrint = true;
176176 }
177177
5454 }
5555
5656 bool XCorePassConfig::addInstSelector() {
57 PM.add(createXCoreISelDag(getXCoreTargetMachine(), getOptLevel()));
57 PM->add(createXCoreISelDag(getXCoreTargetMachine(), getOptLevel()));
5858 return false;
5959 }
6060